include/linux/usb/langwell_otg.h

   1 /*
   2  * Intel Langwell USB OTG transceiver driver
   3  * Copyright (C) 2008 - 2010, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  */
  19
  20 #ifndef __LANGWELL_OTG_H
  21 #define __LANGWELL_OTG_H
  22
  23 #include <linux/usb/intel_mid_otg.h>
  24
  25 #define CI_USBCMD               0x30
  26 #       define USBCMD_RST               BIT(1)
  27 #       define USBCMD_RS                BIT(0)
  28 #define CI_USBSTS               0x34
  29 #       define USBSTS_SLI               BIT(8)
  30 #       define USBSTS_URI               BIT(6)
  31 #       define USBSTS_PCI               BIT(2)
  32 #define CI_PORTSC1              0x74
  33 #       define PORTSC_PP                BIT(12)
  34 #       define PORTSC_LS                (BIT(11) | BIT(10))
  35 #       define PORTSC_SUSP              BIT(7)
  36 #       define PORTSC_CCS               BIT(0)
  37 #define CI_HOSTPC1              0xb4
  38 #       define HOSTPC1_PHCD             BIT(22)
  39 #define CI_OTGSC                0xf4
  40 #       define OTGSC_DPIE               BIT(30)
  41 #       define OTGSC_1MSE               BIT(29)
  42 #       define OTGSC_BSEIE              BIT(28)
  43 #       define OTGSC_BSVIE              BIT(27)
  44 #       define OTGSC_ASVIE              BIT(26)
  45 #       define OTGSC_AVVIE              BIT(25)
  46 #       define OTGSC_IDIE               BIT(24)
  47 #       define OTGSC_DPIS               BIT(22)
  48 #       define OTGSC_1MSS               BIT(21)
  49 #       define OTGSC_BSEIS              BIT(20)
  50 #       define OTGSC_BSVIS              BIT(19)
  51 #       define OTGSC_ASVIS              BIT(18)
  52 #       define OTGSC_AVVIS              BIT(17)
  53 #       define OTGSC_IDIS               BIT(16)
  54 #       define OTGSC_DPS                BIT(14)
  55 #       define OTGSC_1MST               BIT(13)
  56 #       define OTGSC_BSE                BIT(12)
  57 #       define OTGSC_BSV                BIT(11)
  58 #       define OTGSC_ASV                BIT(10)
  59 #       define OTGSC_AVV                BIT(9)
  60 #       define OTGSC_ID                 BIT(8)
  61 #       define OTGSC_HABA               BIT(7)
  62 #       define OTGSC_HADP               BIT(6)
  63 #       define OTGSC_IDPU               BIT(5)
  64 #       define OTGSC_DP                 BIT(4)
  65 #       define OTGSC_OT                 BIT(3)
  66 #       define OTGSC_HAAR               BIT(2)
  67 #       define OTGSC_VC                 BIT(1)
  68 #       define OTGSC_VD                 BIT(0)
  69 #       define OTGSC_INTEN_MASK         (0x7f << 24)
  70 #       define OTGSC_INT_MASK           (0x5f << 24)
  71 #       define OTGSC_INTSTS_MASK        (0x7f << 16)
  72 #define CI_USBMODE              0xf8
  73 #       define USBMODE_CM               (BIT(1) | BIT(0))
  74 #       define USBMODE_IDLE             0
  75 #       define USBMODE_DEVICE           0x2
  76 #       define USBMODE_HOST             0x3
  77 #define USBCFG_ADDR                     0xff10801c
  78 #define USBCFG_LEN                      4
  79 #       define USBCFG_VBUSVAL           BIT(14)
  80 #       define USBCFG_AVALID            BIT(13)
  81 #       define USBCFG_BVALID            BIT(12)
  82 #       define USBCFG_SESEND            BIT(11)
  83
  84 #define INTR_DUMMY_MASK (USBSTS_SLI | USBSTS_URI | USBSTS_PCI)
  85
  86 enum langwell_otg_timer_type {
  87         TA_WAIT_VRISE_TMR,
  88         TA_WAIT_BCON_TMR,
  89         TA_AIDL_BDIS_TMR,
  90         TB_ASE0_BRST_TMR,
  91         TB_SE0_SRP_TMR,
  92         TB_SRP_INIT_TMR,
  93         TB_SRP_FAIL_TMR,
  94         TB_BUS_SUSPEND_TMR
  95 };
  96
  97 #define TA_WAIT_VRISE   100
  98 #define TA_WAIT_BCON    30000
  99 #define TA_AIDL_BDIS    15000
 100 #define TB_ASE0_BRST    5000
 101 #define TB_SE0_SRP      2
 102 #define TB_SRP_INIT     100
 103 #define TB_SRP_FAIL     5500
 104 #define TB_BUS_SUSPEND  500
 105
 106 struct langwell_otg_timer {
 107         unsigned long expires;  /* Number of count increase to timeout */
 108         unsigned long count;    /* Tick counter */
 109         void (*function)(unsigned long);        /* Timeout function */
 110         unsigned long data;     /* Data passed to function */
 111         struct list_head list;
 112 };
 113
 114 struct langwell_otg {
 115         struct intel_mid_otg_xceiv      iotg;
 116         struct device                   *dev;
 117
 118         void __iomem                    *usbcfg;        /* SCCBUSB config Reg */
 119
 120         unsigned                        region;
 121         unsigned                        cfg_region;
 122
 123         struct work_struct              work;
 124         struct workqueue_struct         *qwork;
 125         struct timer_list               hsm_timer;
 126
 127         spinlock_t                      lock;
 128         spinlock_t                      wq_lock;
 129
 130         struct notifier_block           iotg_notifier;
 131 };
 132
 133 static inline
 134 struct langwell_otg *mid_xceiv_to_lnw(struct intel_mid_otg_xceiv *iotg)
 135 {
 136         return container_of(iotg, struct langwell_otg, iotg);
 137 }
 138
 139 #endif /* __LANGWELL_OTG_H__ */