include/linux/via-core.h

   1 /*
   2  * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4  * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
   5  * Copyright 2010 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public
   9  * License as published by the Free Software Foundation;
  10  * either version 2, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  14  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  15  * A PARTICULAR PURPOSE.See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc.,
  21  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22  */
  23
  24 #ifndef __VIA_CORE_H__
  25 #define __VIA_CORE_H__
  26 #include <linux/types.h>
  27 #include <linux/io.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/pci.h>
  30
  31 /*
  32  * A description of each known serial I2C/GPIO port.
  33  */
  34 enum via_port_type {
  35         VIA_PORT_NONE = 0,
  36         VIA_PORT_I2C,
  37         VIA_PORT_GPIO,
  38 };
  39
  40 enum via_port_mode {
  41         VIA_MODE_OFF = 0,
  42         VIA_MODE_I2C,           /* Used as I2C port */
  43         VIA_MODE_GPIO,  /* Two GPIO ports */
  44 };
  45
  46 enum viafb_i2c_adap {
  47         VIA_PORT_26 = 0,
  48         VIA_PORT_31,
  49         VIA_PORT_25,
  50         VIA_PORT_2C,
  51         VIA_PORT_3D,
  52 };
  53 #define VIAFB_NUM_PORTS 5
  54
  55 struct via_port_cfg {
  56         enum via_port_type      type;
  57         enum via_port_mode      mode;
  58         u16                     io_port;
  59         u8                      ioport_index;
  60 };
  61
  62 /*
  63  * This is the global viafb "device" containing stuff needed by
  64  * all subdevs.
  65  */
  66 struct viafb_dev {
  67         struct pci_dev *pdev;
  68         int chip_type;
  69         struct via_port_cfg *port_cfg;
  70         /*
  71          * Spinlock for access to device registers.  Not yet
  72          * globally used.
  73          */
  74         spinlock_t reg_lock;
  75         /*
  76          * The framebuffer MMIO region.  Little, if anything, touches
  77          * this memory directly, and certainly nothing outside of the
  78          * framebuffer device itself.  We *do* have to be able to allocate
  79          * chunks of this memory for other devices, though.
  80          */
  81         unsigned long fbmem_start;
  82         long fbmem_len;
  83         void __iomem *fbmem;
  84 #if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE)
  85         long camera_fbmem_offset;
  86         long camera_fbmem_size;
  87 #endif
  88         /*
  89          * The MMIO region for device registers.
  90          */
  91         unsigned long engine_start;
  92         unsigned long engine_len;
  93         void __iomem *engine_mmio;
  94
  95 };
  96
  97 /*
  98  * Interrupt management.
  99  */
 100
 101 void viafb_irq_enable(u32 mask);
 102 void viafb_irq_disable(u32 mask);
 103
 104 /*
 105  * The global interrupt control register and its bits.
 106  */
 107 #define VDE_INTERRUPT   0x200   /* Video interrupt flags/masks */
 108 #define   VDE_I_DVISENSE  0x00000001  /* DVI sense int status */
 109 #define   VDE_I_VBLANK    0x00000002  /* Vertical blank status */
 110 #define   VDE_I_MCCFI     0x00000004  /* MCE compl. frame int status */
 111 #define   VDE_I_VSYNC     0x00000008  /* VGA VSYNC int status */
 112 #define   VDE_I_DMA0DDONE 0x00000010  /* DMA 0 descr done */
 113 #define   VDE_I_DMA0TDONE 0x00000020  /* DMA 0 transfer done */
 114 #define   VDE_I_DMA1DDONE 0x00000040  /* DMA 1 descr done */
 115 #define   VDE_I_DMA1TDONE 0x00000080  /* DMA 1 transfer done */
 116 #define   VDE_I_C1AV      0x00000100  /* Cap Eng 1 act vid end */
 117 #define   VDE_I_HQV0      0x00000200  /* First HQV engine */
 118 #define   VDE_I_HQV1      0x00000400  /* Second HQV engine */
 119 #define   VDE_I_HQV1EN    0x00000800  /* Second HQV engine enable */
 120 #define   VDE_I_C0AV      0x00001000  /* Cap Eng 0 act vid end */
 121 #define   VDE_I_C0VBI     0x00002000  /* Cap Eng 0 VBI end */
 122 #define   VDE_I_C1VBI     0x00004000  /* Cap Eng 1 VBI end */
 123 #define   VDE_I_VSYNC2    0x00008000  /* Sec. Disp. VSYNC */
 124 #define   VDE_I_DVISNSEN  0x00010000  /* DVI sense enable */
 125 #define   VDE_I_VSYNC2EN  0x00020000  /* Sec Disp VSYNC enable */
 126 #define   VDE_I_MCCFIEN   0x00040000  /* MC comp frame int mask enable */
 127 #define   VDE_I_VSYNCEN   0x00080000  /* VSYNC enable */
 128 #define   VDE_I_DMA0DDEN  0x00100000  /* DMA 0 descr done enable */
 129 #define   VDE_I_DMA0TDEN  0x00200000  /* DMA 0 trans done enable */
 130 #define   VDE_I_DMA1DDEN  0x00400000  /* DMA 1 descr done enable */
 131 #define   VDE_I_DMA1TDEN  0x00800000  /* DMA 1 trans done enable */
 132 #define   VDE_I_C1AVEN    0x01000000  /* cap 1 act vid end enable */
 133 #define   VDE_I_HQV0EN    0x02000000  /* First hqv engine enable */
 134 #define   VDE_I_C1VBIEN   0x04000000  /* Cap 1 VBI end enable */
 135 #define   VDE_I_LVDSSI    0x08000000  /* LVDS sense interrupt */
 136 #define   VDE_I_C0AVEN    0x10000000  /* Cap 0 act vid end enable */
 137 #define   VDE_I_C0VBIEN   0x20000000  /* Cap 0 VBI end enable */
 138 #define   VDE_I_LVDSSIEN  0x40000000  /* LVDS Sense enable */
 139 #define   VDE_I_ENABLE    0x80000000  /* Global interrupt enable */
 140
 141 /*
 142  * DMA management.
 143  */
 144 int viafb_request_dma(void);
 145 void viafb_release_dma(void);
 146 /* void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len); */
 147 int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg);
 148
 149 /*
 150  * DMA Controller registers.
 151  */
 152 #define VDMA_MR0        0xe00           /* Mod reg 0 */
 153 #define   VDMA_MR_CHAIN   0x01          /* Chaining mode */
 154 #define   VDMA_MR_TDIE    0x02          /* Transfer done int enable */
 155 #define VDMA_CSR0       0xe04           /* Control/status */
 156 #define   VDMA_C_ENABLE   0x01            /* DMA Enable */
 157 #define   VDMA_C_START    0x02            /* Start a transfer */
 158 #define   VDMA_C_ABORT    0x04            /* Abort a transfer */
 159 #define   VDMA_C_DONE     0x08            /* Transfer is done */
 160 #define VDMA_MARL0      0xe20           /* Mem addr low */
 161 #define VDMA_MARH0      0xe24           /* Mem addr high */
 162 #define VDMA_DAR0       0xe28           /* Device address */
 163 #define VDMA_DQWCR0     0xe2c           /* Count (16-byte) */
 164 #define VDMA_TMR0       0xe30           /* Tile mode reg */
 165 #define VDMA_DPRL0      0xe34           /* Not sure */
 166 #define   VDMA_DPR_IN     0x08          /* Inbound transfer to FB */
 167 #define VDMA_DPRH0      0xe38
 168 #define VDMA_PMR0       (0xe00 + 0x134) /* Pitch mode */
 169
 170 /*
 171  * Useful stuff that probably belongs somewhere global.
 172  */
 173 #define VGA_WIDTH       640
 174 #define VGA_HEIGHT      480
 175
 176 /*
 177  * Indexed port operations.  Note that these are all multi-op
 178  * functions; every invocation will be racy if you're not holding
 179  * reg_lock.
 180  */
 181
 182 #define VIAStatus   0x3DA  /* Non-indexed port */
 183 #define VIACR       0x3D4
 184 #define VIASR       0x3C4
 185 #define VIAGR       0x3CE
 186 #define VIAAR       0x3C0
 187
 188 static inline u8 via_read_reg(u16 port, u8 index)
 189 {
 190         outb(index, port);
 191         return inb(port + 1);
 192 }
 193
 194 static inline void via_write_reg(u16 port, u8 index, u8 data)
 195 {
 196         outb(index, port);
 197         outb(data, port + 1);
 198 }
 199
 200 static inline void via_write_reg_mask(u16 port, u8 index, u8 data, u8 mask)
 201 {
 202         u8 old;
 203
 204         outb(index, port);
 205         old = inb(port + 1);
 206         outb((data & mask) | (old & ~mask), port + 1);
 207 }
 208
 209 #define VIA_MISC_REG_READ       0x03CC
 210 #define VIA_MISC_REG_WRITE      0x03C2
 211
 212 static inline void via_write_misc_reg_mask(u8 data, u8 mask)
 213 {
 214         u8 old = inb(VIA_MISC_REG_READ);
 215         outb((data & mask) | (old & ~mask), VIA_MISC_REG_WRITE);
 216 }
 217
 218
 219 #endif /* __VIA_CORE_H__ */