arch/blackfin/mach-bf561/include/mach/pll.h

   1 /*
   2  * Copyright 2005-2010 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _MACH_PLL_H
   8 #define _MACH_PLL_H
   9
  10 #ifndef __ASSEMBLY__
  11
  12 #ifdef CONFIG_SMP
  13
  14 #include <asm/blackfin.h>
  15 #include <asm/irqflags.h>
  16 #include <mach/irq.h>
  17
  18 #define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
  19
  20 static inline void
  21 bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
  22 {
  23         unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
  24
  25         bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
  26         bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
  27 }
  28 #define bfin_iwr_restore bfin_iwr_restore
  29
  30 static inline void
  31 bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
  32               unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
  33 {
  34         unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
  35
  36         *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
  37         *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
  38         bfin_iwr_restore(niwr0, niwr1, niwr2);
  39 }
  40 #define bfin_iwr_save bfin_iwr_save
  41
  42 static inline void
  43 bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
  44 {
  45         bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP), 0, iwr0, iwr1, iwr2);
  46 }
  47
  48 #endif
  49
  50 #endif
  51
  52 #include <mach-common/pll.h>
  53
  54 #endif