arch/x86/include/asm/io.h

   1 #ifndef _ASM_X86_IO_H
   2 #define _ASM_X86_IO_H
   3
   4 /*
   5  * This file contains the definitions for the x86 IO instructions
   6  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
   7  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
   8  * versions of the single-IO instructions (inb_p/inw_p/..).
   9  *
  10  * This file is not meant to be obfuscating: it's just complicated
  11  * to (a) handle it all in a way that makes gcc able to optimize it
  12  * as well as possible and (b) trying to avoid writing the same thing
  13  * over and over again with slight variations and possibly making a
  14  * mistake somewhere.
  15  */
  16
  17 /*
  18  * Thanks to James van Artsdalen for a better timing-fix than
  19  * the two short jumps: using outb's to a nonexistent port seems
  20  * to guarantee better timings even on fast machines.
  21  *
  22  * On the other hand, I'd like to be sure of a non-existent port:
  23  * I feel a bit unsafe about using 0x80 (should be safe, though)
  24  *
  25  *              Linus
  26  */
  27
  28  /*
  29   *  Bit simplified and optimized by Jan Hubicka
  30   *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
  31   *
  32   *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
  33   *  isa_read[wl] and isa_write[wl] fixed
  34   *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  35   */
  36
  37 #define ARCH_HAS_IOREMAP_WC
  38
  39 #include <linux/string.h>
  40 #include <linux/compiler.h>
  41 #include <asm/page.h>
  42
  43 #include <xen/xen.h>
  44
  45 #define build_mmio_read(name, size, type, reg, barrier) \
  46 static inline type name(const volatile void __iomem *addr) \
  47 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
  48 :"m" (*(volatile type __force *)addr) barrier); return ret; }
  49
  50 #define build_mmio_write(name, size, type, reg, barrier) \
  51 static inline void name(type val, volatile void __iomem *addr) \
  52 { asm volatile("mov" size " %0,%1": :reg (val), \
  53 "m" (*(volatile type __force *)addr) barrier); }
  54
  55 build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
  56 build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
  57 build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
  58
  59 build_mmio_read(__readb, "b", unsigned char, "=q", )
  60 build_mmio_read(__readw, "w", unsigned short, "=r", )
  61 build_mmio_read(__readl, "l", unsigned int, "=r", )
  62
  63 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
  64 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
  65 build_mmio_write(writel, "l", unsigned int, "r", :"memory")
  66
  67 build_mmio_write(__writeb, "b", unsigned char, "q", )
  68 build_mmio_write(__writew, "w", unsigned short, "r", )
  69 build_mmio_write(__writel, "l", unsigned int, "r", )
  70
  71 #define readb_relaxed(a) __readb(a)
  72 #define readw_relaxed(a) __readw(a)
  73 #define readl_relaxed(a) __readl(a)
  74 #define __raw_readb __readb
  75 #define __raw_readw __readw
  76 #define __raw_readl __readl
  77
  78 #define __raw_writeb __writeb
  79 #define __raw_writew __writew
  80 #define __raw_writel __writel
  81
  82 #define mmiowb() barrier()
  83
  84 #ifdef CONFIG_X86_64
  85
  86 build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
  87 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
  88
  89 #define readq_relaxed(a)        readq(a)
  90
  91 #define __raw_readq(a)          readq(a)
  92 #define __raw_writeq(val, addr) writeq(val, addr)
  93
  94 /* Let people know that we have them */
  95 #define readq                   readq
  96 #define writeq                  writeq
  97
  98 #endif
  99
 100 /**
 101  *      virt_to_phys    -       map virtual addresses to physical
 102  *      @address: address to remap
 103  *
 104  *      The returned physical address is the physical (CPU) mapping for
 105  *      the memory address given. It is only valid to use this function on
 106  *      addresses directly mapped or allocated via kmalloc.
 107  *
 108  *      This function does not give bus mappings for DMA transfers. In
 109  *      almost all conceivable cases a device driver should not be using
 110  *      this function
 111  */
 112
 113 static inline phys_addr_t virt_to_phys(volatile void *address)
 114 {
 115         return __pa(address);
 116 }
 117
 118 /**
 119  *      phys_to_virt    -       map physical address to virtual
 120  *      @address: address to remap
 121  *
 122  *      The returned virtual address is a current CPU mapping for
 123  *      the memory address given. It is only valid to use this function on
 124  *      addresses that have a kernel mapping
 125  *
 126  *      This function does not handle bus mappings for DMA transfers. In
 127  *      almost all conceivable cases a device driver should not be using
 128  *      this function
 129  */
 130
 131 static inline void *phys_to_virt(phys_addr_t address)
 132 {
 133         return __va(address);
 134 }
 135
 136 /*
 137  * Change "struct page" to physical address.
 138  */
 139 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 140
 141 /*
 142  * ISA I/O bus memory addresses are 1:1 with the physical address.
 143  * However, we truncate the address to unsigned int to avoid undesirable
 144  * promitions in legacy drivers.
 145  */
 146 static inline unsigned int isa_virt_to_bus(volatile void *address)
 147 {
 148         return (unsigned int)virt_to_phys(address);
 149 }
 150 #define isa_page_to_bus(page)   ((unsigned int)page_to_phys(page))
 151 #define isa_bus_to_virt         phys_to_virt
 152
 153 /*
 154  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 155  * are forbidden in portable PCI drivers.
 156  *
 157  * Allow them on x86 for legacy drivers, though.
 158  */
 159 #define virt_to_bus virt_to_phys
 160 #define bus_to_virt phys_to_virt
 161
 162 /**
 163  * ioremap     -   map bus memory into CPU space
 164  * @offset:    bus address of the memory
 165  * @size:      size of the resource to map
 166  *
 167  * ioremap performs a platform specific sequence of operations to
 168  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 169  * writew/writel functions and the other mmio helpers. The returned
 170  * address is not guaranteed to be usable directly as a virtual
 171  * address.
 172  *
 173  * If the area you are trying to map is a PCI BAR you should have a
 174  * look at pci_iomap().
 175  */
 176 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
 177 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
 178 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
 179                                 unsigned long prot_val);
 180
 181 /*
 182  * The default ioremap() behavior is non-cached:
 183  */
 184 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
 185 {
 186         return ioremap_nocache(offset, size);
 187 }
 188
 189 extern void iounmap(volatile void __iomem *addr);
 190
 191 extern void set_iounmap_nonlazy(void);
 192
 193 #ifdef __KERNEL__
 194
 195 #include <asm-generic/iomap.h>
 196
 197 #include <linux/vmalloc.h>
 198
 199 /*
 200  * Convert a virtual cached pointer to an uncached pointer
 201  */
 202 #define xlate_dev_kmem_ptr(p)   p
 203
 204 static inline void
 205 memset_io(volatile void __iomem *addr, unsigned char val, size_t count)
 206 {
 207         memset((void __force *)addr, val, count);
 208 }
 209
 210 static inline void
 211 memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count)
 212 {
 213         memcpy(dst, (const void __force *)src, count);
 214 }
 215
 216 static inline void
 217 memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
 218 {
 219         memcpy((void __force *)dst, src, count);
 220 }
 221
 222 /*
 223  * ISA space is 'always mapped' on a typical x86 system, no need to
 224  * explicitly ioremap() it. The fact that the ISA IO space is mapped
 225  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 226  * are physical addresses. The following constant pointer can be
 227  * used as the IO-area pointer (it can be iounmapped as well, so the
 228  * analogy with PCI is quite large):
 229  */
 230 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
 231
 232 /*
 233  *      Cache management
 234  *
 235  *      This needed for two cases
 236  *      1. Out of order aware processors
 237  *      2. Accidentally out of order processors (PPro errata #51)
 238  */
 239
 240 static inline void flush_write_buffers(void)
 241 {
 242 #if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
 243         asm volatile("lock; addl $0,0(%%esp)": : :"memory");
 244 #endif
 245 }
 246
 247 #endif /* __KERNEL__ */
 248
 249 extern void native_io_delay(void);
 250
 251 extern int io_delay_type;
 252 extern void io_delay_init(void);
 253
 254 #if defined(CONFIG_PARAVIRT)
 255 #include <asm/paravirt.h>
 256 #else
 257
 258 static inline void slow_down_io(void)
 259 {
 260         native_io_delay();
 261 #ifdef REALLY_SLOW_IO
 262         native_io_delay();
 263         native_io_delay();
 264         native_io_delay();
 265 #endif
 266 }
 267
 268 #endif
 269
 270 #define BUILDIO(bwl, bw, type)                                          \
 271 static inline void out##bwl(unsigned type value, int port)              \
 272 {                                                                       \
 273         asm volatile("out" #bwl " %" #bw "0, %w1"                       \
 274                      : : "a"(value), "Nd"(port));                       \
 275 }                                                                       \
 276                                                                         \
 277 static inline unsigned type in##bwl(int port)                           \
 278 {                                                                       \
 279         unsigned type value;                                            \
 280         asm volatile("in" #bwl " %w1, %" #bw "0"                        \
 281                      : "=a"(value) : "Nd"(port));                       \
 282         return value;                                                   \
 283 }                                                                       \
 284                                                                         \
 285 static inline void out##bwl##_p(unsigned type value, int port)          \
 286 {                                                                       \
 287         out##bwl(value, port);                                          \
 288         slow_down_io();                                                 \
 289 }                                                                       \
 290                                                                         \
 291 static inline unsigned type in##bwl##_p(int port)                       \
 292 {                                                                       \
 293         unsigned type value = in##bwl(port);                            \
 294         slow_down_io();                                                 \
 295         return value;                                                   \
 296 }                                                                       \
 297                                                                         \
 298 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
 299 {                                                                       \
 300         asm volatile("rep; outs" #bwl                                   \
 301                      : "+S"(addr), "+c"(count) : "d"(port));            \
 302 }                                                                       \
 303                                                                         \
 304 static inline void ins##bwl(int port, void *addr, unsigned long count)  \
 305 {                                                                       \
 306         asm volatile("rep; ins" #bwl                                    \
 307                      : "+D"(addr), "+c"(count) : "d"(port));            \
 308 }
 309
 310 BUILDIO(b, b, char)
 311 BUILDIO(w, w, short)
 312 BUILDIO(l, , int)
 313
 314 extern void *xlate_dev_mem_ptr(unsigned long phys);
 315 extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
 316
 317 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
 318                                 unsigned long prot_val);
 319 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
 320
 321 /*
 322  * early_ioremap() and early_iounmap() are for temporary early boot-time
 323  * mappings, before the real ioremap() is functional.
 324  * A boot-time mapping is currently limited to at most 16 pages.
 325  */
 326 extern void early_ioremap_init(void);
 327 extern void early_ioremap_reset(void);
 328 extern void __iomem *early_ioremap(resource_size_t phys_addr,
 329                                    unsigned long size);
 330 extern void __iomem *early_memremap(resource_size_t phys_addr,
 331                                     unsigned long size);
 332 extern void early_iounmap(void __iomem *addr, unsigned long size);
 333 extern void fixup_early_ioremap(void);
 334 extern bool is_early_ioremap_ptep(pte_t *ptep);
 335
 336 #ifdef CONFIG_XEN
 337 struct bio_vec;
 338
 339 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
 340                                       const struct bio_vec *vec2);
 341
 342 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
 343         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
 344          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
 345 #endif  /* CONFIG_XEN */
 346
 347 #define IO_SPACE_LIMIT 0xffff
 348
 349 #endif /* _ASM_X86_IO_H */