This client driver allows you to use a GPIO pin as a source for PPS
[linux-2.6/next.git] / arch / arm / mach-pnx4008 / serial.c
blob374c138ac1ac2efe8ec6a099cab37e2f4d85be0c
1 /*
2 * linux/arch/arm/mach-pnx4008/serial.c
4 * PNX4008 UART initialization
6 * Copyright: MontaVista Software Inc. (c) 2005
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/io.h>
16 #include <mach/platform.h>
17 #include <mach/hardware.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial_reg.h>
22 #include <mach/gpio-pnx4008.h>
23 #include <mach/clock.h>
25 #define UART_3 0
26 #define UART_4 1
27 #define UART_5 2
28 #define UART_6 3
29 #define UART_UNKNOWN (-1)
31 #define UART3_BASE_VA IO_ADDRESS(PNX4008_UART3_BASE)
32 #define UART4_BASE_VA IO_ADDRESS(PNX4008_UART4_BASE)
33 #define UART5_BASE_VA IO_ADDRESS(PNX4008_UART5_BASE)
34 #define UART6_BASE_VA IO_ADDRESS(PNX4008_UART6_BASE)
36 #define UART_FCR_OFFSET 8
37 #define UART_FIFO_SIZE 64
39 void pnx4008_uart_init(void)
41 u32 tmp;
42 int i = UART_FIFO_SIZE;
44 __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
45 __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
47 /* Send a NULL to fix the UART HW bug */
48 __raw_writel(0x00, UART5_BASE_VA);
49 __raw_writel(0x00, UART3_BASE_VA);
51 while (i--) {
52 tmp = __raw_readl(UART5_BASE_VA);
53 tmp = __raw_readl(UART3_BASE_VA);
55 __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
56 __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
58 /* setup wakeup interrupt */
59 start_int_set_rising_edge(SE_U3_RX_INT);
60 start_int_ack(SE_U3_RX_INT);
61 start_int_umask(SE_U3_RX_INT);
63 start_int_set_rising_edge(SE_U5_RX_INT);
64 start_int_ack(SE_U5_RX_INT);
65 start_int_umask(SE_U5_RX_INT);