arch/arm/mach-tegra/irq.c

   1 /*
   2  * Copyright (C) 2011 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@android.com>
   6  *
   7  * Copyright (C) 2010, NVIDIA Corporation
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24
  25 #include <asm/hardware/gic.h>
  26
  27 #include <mach/iomap.h>
  28
  29 #include "board.h"
  30
  31 #define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
  32 #define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
  33 #define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
  34
  35 #define ICTLR_CPU_IEP_VFIQ      0x08
  36 #define ICTLR_CPU_IEP_FIR       0x14
  37 #define ICTLR_CPU_IEP_FIR_SET   0x18
  38 #define ICTLR_CPU_IEP_FIR_CLR   0x1c
  39
  40 #define ICTLR_CPU_IER           0x20
  41 #define ICTLR_CPU_IER_SET       0x24
  42 #define ICTLR_CPU_IER_CLR       0x28
  43 #define ICTLR_CPU_IEP_CLASS     0x2C
  44
  45 #define ICTLR_COP_IER           0x30
  46 #define ICTLR_COP_IER_SET       0x34
  47 #define ICTLR_COP_IER_CLR       0x38
  48 #define ICTLR_COP_IEP_CLASS     0x3c
  49
  50 #define NUM_ICTLRS 4
  51 #define FIRST_LEGACY_IRQ 32
  52
  53 static void __iomem *ictlr_reg_base[] = {
  54         IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
  55         IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
  56         IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
  57         IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
  58 };
  59
  60 static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
  61 {
  62         void __iomem *base;
  63         u32 mask;
  64
  65         BUG_ON(irq < FIRST_LEGACY_IRQ ||
  66                 irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
  67
  68         base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
  69         mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
  70
  71         __raw_writel(mask, base + reg);
  72 }
  73
  74 static void tegra_mask(struct irq_data *d)
  75 {
  76         if (d->irq < FIRST_LEGACY_IRQ)
  77                 return;
  78
  79         tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
  80 }
  81
  82 static void tegra_unmask(struct irq_data *d)
  83 {
  84         if (d->irq < FIRST_LEGACY_IRQ)
  85                 return;
  86
  87         tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
  88 }
  89
  90 static void tegra_ack(struct irq_data *d)
  91 {
  92         if (d->irq < FIRST_LEGACY_IRQ)
  93                 return;
  94
  95         tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
  96 }
  97
  98 static void tegra_eoi(struct irq_data *d)
  99 {
 100         if (d->irq < FIRST_LEGACY_IRQ)
 101                 return;
 102
 103         tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
 104 }
 105
 106 static int tegra_retrigger(struct irq_data *d)
 107 {
 108         if (d->irq < FIRST_LEGACY_IRQ)
 109                 return 0;
 110
 111         tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
 112
 113         return 1;
 114 }
 115
 116 void __init tegra_init_irq(void)
 117 {
 118         int i;
 119
 120         for (i = 0; i < NUM_ICTLRS; i++) {
 121                 void __iomem *ictlr = ictlr_reg_base[i];
 122                 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
 123                 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
 124         }
 125
 126         gic_arch_extn.irq_ack = tegra_ack;
 127         gic_arch_extn.irq_eoi = tegra_eoi;
 128         gic_arch_extn.irq_mask = tegra_mask;
 129         gic_arch_extn.irq_unmask = tegra_unmask;
 130         gic_arch_extn.irq_retrigger = tegra_retrigger;
 131
 132         gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
 133                  IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 134 }