arch/unicore32/include/mach/regs-dmac.h

   1 /*
   2  * PKUnity Direct Memory Access Controller (DMAC)
   3  */
   4
   5 /*
   6  * Interrupt Status Reg DMAC_ISR.
   7  */
   8 #define DMAC_ISR                (PKUNITY_DMAC_BASE + 0x0020)
   9 /*
  10  * Interrupt Transfer Complete Status Reg DMAC_ITCSR.
  11  */
  12 #define DMAC_ITCSR              (PKUNITY_DMAC_BASE + 0x0050)
  13 /*
  14  * Interrupt Transfer Complete Clear Reg DMAC_ITCCR.
  15  */
  16 #define DMAC_ITCCR              (PKUNITY_DMAC_BASE + 0x0060)
  17 /*
  18  * Interrupt Error Status Reg DMAC_IESR.
  19  */
  20 #define DMAC_IESR               (PKUNITY_DMAC_BASE + 0x0080)
  21 /*
  22  * Interrupt Error Clear Reg DMAC_IECR.
  23  */
  24 #define DMAC_IECR               (PKUNITY_DMAC_BASE + 0x0090)
  25 /*
  26  * Enable Channels Reg DMAC_ENCH.
  27  */
  28 #define DMAC_ENCH               (PKUNITY_DMAC_BASE + 0x00B0)
  29
  30 /*
  31  * DMA control reg. Space [byte]
  32  */
  33 #define DMASp                   0x00000100
  34
  35 /*
  36  * Source Addr DMAC_SRCADDR(ch).
  37  */
  38 #define DMAC_SRCADDR(ch)        (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
  39 /*
  40  * Destination Addr DMAC_DESTADDR(ch).
  41  */
  42 #define DMAC_DESTADDR(ch)       (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
  43 /*
  44  * Control Reg DMAC_CONTROL(ch).
  45  */
  46 #define DMAC_CONTROL(ch)        (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
  47 /*
  48  * Configuration Reg DMAC_CONFIG(ch).
  49  */
  50 #define DMAC_CONFIG(ch)         (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
  51
  52 #define DMAC_IR_MASK            FMASK(6, 0)
  53 /*
  54  * select channel (ch)
  55  */
  56 #define DMAC_CHANNEL(ch)        FIELD(1, 1, (ch))
  57
  58 #define DMAC_CONTROL_SIZE_BYTE(v)       (FIELD((v), 12, 14) | \
  59                                         FIELD(0, 3, 9) | FIELD(0, 3, 6))
  60 #define DMAC_CONTROL_SIZE_HWORD(v)      (FIELD((v) >> 1, 12, 14) | \
  61                                         FIELD(1, 3, 9) | FIELD(1, 3, 6))
  62 #define DMAC_CONTROL_SIZE_WORD(v)       (FIELD((v) >> 2, 12, 14) | \
  63                                         FIELD(2, 3, 9) | FIELD(2, 3, 6))
  64 #define DMAC_CONTROL_DI                 FIELD(1, 1, 13)
  65 #define DMAC_CONTROL_SI                 FIELD(1, 1, 12)
  66 #define DMAC_CONTROL_BURST_1BYTE        (FIELD(0, 3, 3) | FIELD(0, 3, 0))
  67 #define DMAC_CONTROL_BURST_4BYTE        (FIELD(3, 3, 3) | FIELD(3, 3, 0))
  68 #define DMAC_CONTROL_BURST_8BYTE        (FIELD(5, 3, 3) | FIELD(5, 3, 0))
  69 #define DMAC_CONTROL_BURST_16BYTE       (FIELD(7, 3, 3) | FIELD(7, 3, 0))
  70
  71 #define DMAC_CONFIG_UART0_WR    (FIELD(2, 4, 11) | FIELD(1, 2, 1))
  72 #define DMAC_CONFIG_UART0_RD    (FIELD(2, 4, 7)  | FIELD(2, 2, 1))
  73 #define DMAC_CONFIG_UART1_WR    (FIELD(3, 4, 11) | FIELD(1, 2, 1))
  74 #define DMAC_CONFIG_UART1RD     (FIELD(3, 4, 7)  | FIELD(2, 2, 1))
  75 #define DMAC_CONFIG_AC97WR      (FIELD(4, 4, 11) | FIELD(1, 2, 1))
  76 #define DMAC_CONFIG_AC97RD      (FIELD(4, 4, 7)  | FIELD(2, 2, 1))
  77 #define DMAC_CONFIG_MMCWR       (FIELD(7, 4, 11) | FIELD(1, 2, 1))
  78 #define DMAC_CONFIG_MMCRD       (FIELD(7, 4, 7)  | FIELD(2, 2, 1))
  79 #define DMAC_CONFIG_MASKITC     FIELD(1, 1, 4)
  80 #define DMAC_CONFIG_MASKIE      FIELD(1, 1, 3)
  81 #define DMAC_CONFIG_EN          FIELD(1, 1, 0)