arch/unicore32/include/mach/regs-spi.h

   1 /*
   2  * PKUnity Serial Peripheral Interface (SPI) Registers
   3  */
   4 /*
   5  * Control reg. 0 SPI_CR0
   6  */
   7 #define SPI_CR0         (PKUNITY_SPI_BASE + 0x0000)
   8 /*
   9  * Control reg. 1 SPI_CR1
  10  */
  11 #define SPI_CR1         (PKUNITY_SPI_BASE + 0x0004)
  12 /*
  13  * Enable reg SPI_SSIENR
  14  */
  15 #define SPI_SSIENR      (PKUNITY_SPI_BASE + 0x0008)
  16 /*
  17  * Status reg SPI_SR
  18  */
  19 #define SPI_SR          (PKUNITY_SPI_BASE + 0x0028)
  20 /*
  21  * Interrupt Mask reg SPI_IMR
  22  */
  23 #define SPI_IMR         (PKUNITY_SPI_BASE + 0x002C)
  24 /*
  25  * Interrupt Status reg SPI_ISR
  26  */
  27 #define SPI_ISR         (PKUNITY_SPI_BASE + 0x0030)
  28
  29 /*
  30  * Enable SPI Controller SPI_SSIENR_EN
  31  */
  32 #define SPI_SSIENR_EN           FIELD(1, 1, 0)
  33
  34 /*
  35  * SPI Busy SPI_SR_BUSY
  36  */
  37 #define SPI_SR_BUSY             FIELD(1, 1, 0)
  38 /*
  39  * Transmit FIFO Not Full SPI_SR_TFNF
  40  */
  41 #define SPI_SR_TFNF             FIELD(1, 1, 1)
  42 /*
  43  * Transmit FIFO Empty SPI_SR_TFE
  44  */
  45 #define SPI_SR_TFE              FIELD(1, 1, 2)
  46 /*
  47  * Receive FIFO Not Empty SPI_SR_RFNE
  48  */
  49 #define SPI_SR_RFNE             FIELD(1, 1, 3)
  50 /*
  51  * Receive FIFO Full SPI_SR_RFF
  52  */
  53 #define SPI_SR_RFF              FIELD(1, 1, 4)
  54
  55 /*
  56  * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS
  57  */
  58 #define SPI_ISR_TXEIS           FIELD(1, 1, 0)
  59 /*
  60  * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS
  61  */
  62 #define SPI_ISR_TXOIS           FIELD(1, 1, 1)
  63 /*
  64  * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS
  65  */
  66 #define SPI_ISR_RXUIS           FIELD(1, 1, 2)
  67 /*
  68  * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS
  69  */
  70 #define SPI_ISR_RXOIS           FIELD(1, 1, 3)
  71 /*
  72  * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS
  73  */
  74 #define SPI_ISR_RXFIS           FIELD(1, 1, 4)
  75 #define SPI_ISR_MSTIS           FIELD(1, 1, 5)
  76
  77 /*
  78  * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM
  79  */
  80 #define SPI_IMR_TXEIM           FIELD(1, 1, 0)
  81 /*
  82  * Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM
  83  */
  84 #define SPI_IMR_TXOIM           FIELD(1, 1, 1)
  85 /*
  86  * Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM
  87  */
  88 #define SPI_IMR_RXUIM           FIELD(1, 1, 2)
  89 /*
  90  * Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM
  91  */
  92 #define SPI_IMR_RXOIM           FIELD(1, 1, 3)
  93 /*
  94  * Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM
  95  */
  96 #define SPI_IMR_RXFIM           FIELD(1, 1, 4)
  97 #define SPI_IMR_MSTIM           FIELD(1, 1, 5)
  98