drivers/i2c/busses/i2c-ibm_iic.c

   1 /*
   2  * drivers/i2c/busses/i2c-ibm_iic.c
   3  *
   4  * Support for the IIC peripheral on IBM PPC 4xx
   5  *
   6  * Copyright (c) 2003, 2004 Zultys Technologies.
   7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   8  *
   9  * Copyright (c) 2008 PIKA Technologies
  10  * Sean MacLennan <smaclennan@pikatech.com>
  11  *
  12  * Based on original work by
  13  *      Ian DaSilva  <idasilva@mvista.com>
  14  *      Armin Kuster <akuster@mvista.com>
  15  *      Matt Porter  <mporter@mvista.com>
  16  *
  17  *      Copyright 2000-2003 MontaVista Software Inc.
  18  *
  19  * Original driver version was highly leveraged from i2c-elektor.c
  20  *
  21  *      Copyright 1995-97 Simon G. Vogl
  22  *                1998-99 Hans Berglund
  23  *
  24  *      With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
  25  *      and even Frodo Looijaard <frodol@dds.nl>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  *
  32  */
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/delay.h>
  38 #include <linux/slab.h>
  39 #include <linux/init.h>
  40 #include <linux/interrupt.h>
  41 #include <asm/irq.h>
  42 #include <linux/io.h>
  43 #include <linux/i2c.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/of_i2c.h>
  46
  47 #include "i2c-ibm_iic.h"
  48
  49 #define DRIVER_VERSION "2.2"
  50
  51 MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
  52 MODULE_LICENSE("GPL");
  53
  54 static int iic_force_poll;
  55 module_param(iic_force_poll, bool, 0);
  56 MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
  57
  58 static int iic_force_fast;
  59 module_param(iic_force_fast, bool, 0);
  60 MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
  61
  62 #define DBG_LEVEL 0
  63
  64 #ifdef DBG
  65 #undef DBG
  66 #endif
  67
  68 #ifdef DBG2
  69 #undef DBG2
  70 #endif
  71
  72 #if DBG_LEVEL > 0
  73 #  define DBG(f,x...)   printk(KERN_DEBUG "ibm-iic" f, ##x)
  74 #else
  75 #  define DBG(f,x...)   ((void)0)
  76 #endif
  77 #if DBG_LEVEL > 1
  78 #  define DBG2(f,x...)  DBG(f, ##x)
  79 #else
  80 #  define DBG2(f,x...)  ((void)0)
  81 #endif
  82 #if DBG_LEVEL > 2
  83 static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
  84 {
  85         volatile struct iic_regs __iomem *iic = dev->vaddr;
  86         printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
  87         printk(KERN_DEBUG
  88                "  cntl     = 0x%02x, mdcntl = 0x%02x\n"
  89                "  sts      = 0x%02x, extsts = 0x%02x\n"
  90                "  clkdiv   = 0x%02x, xfrcnt = 0x%02x\n"
  91                "  xtcntlss = 0x%02x, directcntl = 0x%02x\n",
  92                 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
  93                 in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
  94                 in_8(&iic->xtcntlss), in_8(&iic->directcntl));
  95 }
  96 #  define DUMP_REGS(h,dev)      dump_iic_regs((h),(dev))
  97 #else
  98 #  define DUMP_REGS(h,dev)      ((void)0)
  99 #endif
 100
 101 /* Bus timings (in ns) for bit-banging */
 102 static struct i2c_timings {
 103         unsigned int hd_sta;
 104         unsigned int su_sto;
 105         unsigned int low;
 106         unsigned int high;
 107         unsigned int buf;
 108 } timings [] = {
 109 /* Standard mode (100 KHz) */
 110 {
 111         .hd_sta = 4000,
 112         .su_sto = 4000,
 113         .low    = 4700,
 114         .high   = 4000,
 115         .buf    = 4700,
 116 },
 117 /* Fast mode (400 KHz) */
 118 {
 119         .hd_sta = 600,
 120         .su_sto = 600,
 121         .low    = 1300,
 122         .high   = 600,
 123         .buf    = 1300,
 124 }};
 125
 126 /* Enable/disable interrupt generation */
 127 static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
 128 {
 129         out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
 130 }
 131
 132 /*
 133  * Initialize IIC interface.
 134  */
 135 static void iic_dev_init(struct ibm_iic_private* dev)
 136 {
 137         volatile struct iic_regs __iomem *iic = dev->vaddr;
 138
 139         DBG("%d: init\n", dev->idx);
 140
 141         /* Clear master address */
 142         out_8(&iic->lmadr, 0);
 143         out_8(&iic->hmadr, 0);
 144
 145         /* Clear slave address */
 146         out_8(&iic->lsadr, 0);
 147         out_8(&iic->hsadr, 0);
 148
 149         /* Clear status & extended status */
 150         out_8(&iic->sts, STS_SCMP | STS_IRQA);
 151         out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
 152                             | EXTSTS_ICT | EXTSTS_XFRA);
 153
 154         /* Set clock divider */
 155         out_8(&iic->clkdiv, dev->clckdiv);
 156
 157         /* Clear transfer count */
 158         out_8(&iic->xfrcnt, 0);
 159
 160         /* Clear extended control and status */
 161         out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
 162                             | XTCNTLSS_SWS);
 163
 164         /* Clear control register */
 165         out_8(&iic->cntl, 0);
 166
 167         /* Enable interrupts if possible */
 168         iic_interrupt_mode(dev, dev->irq >= 0);
 169
 170         /* Set mode control */
 171         out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
 172                             | (dev->fast_mode ? MDCNTL_FSM : 0));
 173
 174         DUMP_REGS("iic_init", dev);
 175 }
 176
 177 /*
 178  * Reset IIC interface
 179  */
 180 static void iic_dev_reset(struct ibm_iic_private* dev)
 181 {
 182         volatile struct iic_regs __iomem *iic = dev->vaddr;
 183         int i;
 184         u8 dc;
 185
 186         DBG("%d: soft reset\n", dev->idx);
 187         DUMP_REGS("reset", dev);
 188
 189         /* Place chip in the reset state */
 190         out_8(&iic->xtcntlss, XTCNTLSS_SRST);
 191
 192         /* Check if bus is free */
 193         dc = in_8(&iic->directcntl);
 194         if (!DIRCTNL_FREE(dc)){
 195                 DBG("%d: trying to regain bus control\n", dev->idx);
 196
 197                 /* Try to set bus free state */
 198                 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 199
 200                 /* Wait until we regain bus control */
 201                 for (i = 0; i < 100; ++i){
 202                         dc = in_8(&iic->directcntl);
 203                         if (DIRCTNL_FREE(dc))
 204                                 break;
 205
 206                         /* Toggle SCL line */
 207                         dc ^= DIRCNTL_SCC;
 208                         out_8(&iic->directcntl, dc);
 209                         udelay(10);
 210                         dc ^= DIRCNTL_SCC;
 211                         out_8(&iic->directcntl, dc);
 212
 213                         /* be nice */
 214                         cond_resched();
 215                 }
 216         }
 217
 218         /* Remove reset */
 219         out_8(&iic->xtcntlss, 0);
 220
 221         /* Reinitialize interface */
 222         iic_dev_init(dev);
 223 }
 224
 225 /*
 226  * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
 227  */
 228
 229 /* Wait for SCL and/or SDA to be high */
 230 static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
 231 {
 232         unsigned long x = jiffies + HZ / 28 + 2;
 233         while ((in_8(&iic->directcntl) & mask) != mask){
 234                 if (unlikely(time_after(jiffies, x)))
 235                         return -1;
 236                 cond_resched();
 237         }
 238         return 0;
 239 }
 240
 241 static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
 242 {
 243         volatile struct iic_regs __iomem *iic = dev->vaddr;
 244         const struct i2c_timings* t = &timings[dev->fast_mode ? 1 : 0];
 245         u8 mask, v, sda;
 246         int i, res;
 247
 248         /* Only 7-bit addresses are supported */
 249         if (unlikely(p->flags & I2C_M_TEN)){
 250                 DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
 251                         dev->idx);
 252                 return -EINVAL;
 253         }
 254
 255         DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
 256
 257         /* Reset IIC interface */
 258         out_8(&iic->xtcntlss, XTCNTLSS_SRST);
 259
 260         /* Wait for bus to become free */
 261         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 262         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
 263                 goto err;
 264         ndelay(t->buf);
 265
 266         /* START */
 267         out_8(&iic->directcntl, DIRCNTL_SCC);
 268         sda = 0;
 269         ndelay(t->hd_sta);
 270
 271         /* Send address */
 272         v = (u8)((p->addr << 1) | ((p->flags & I2C_M_RD) ? 1 : 0));
 273         for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
 274                 out_8(&iic->directcntl, sda);
 275                 ndelay(t->low / 2);
 276                 sda = (v & mask) ? DIRCNTL_SDAC : 0;
 277                 out_8(&iic->directcntl, sda);
 278                 ndelay(t->low / 2);
 279
 280                 out_8(&iic->directcntl, DIRCNTL_SCC | sda);
 281                 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 282                         goto err;
 283                 ndelay(t->high);
 284         }
 285
 286         /* ACK */
 287         out_8(&iic->directcntl, sda);
 288         ndelay(t->low / 2);
 289         out_8(&iic->directcntl, DIRCNTL_SDAC);
 290         ndelay(t->low / 2);
 291         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 292         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 293                 goto err;
 294         res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
 295         ndelay(t->high);
 296
 297         /* STOP */
 298         out_8(&iic->directcntl, 0);
 299         ndelay(t->low);
 300         out_8(&iic->directcntl, DIRCNTL_SCC);
 301         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 302                 goto err;
 303         ndelay(t->su_sto);
 304         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 305
 306         ndelay(t->buf);
 307
 308         DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
 309 out:
 310         /* Remove reset */
 311         out_8(&iic->xtcntlss, 0);
 312
 313         /* Reinitialize interface */
 314         iic_dev_init(dev);
 315
 316         return res;
 317 err:
 318         DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
 319         res = -EREMOTEIO;
 320         goto out;
 321 }
 322
 323 /*
 324  * IIC interrupt handler
 325  */
 326 static irqreturn_t iic_handler(int irq, void *dev_id)
 327 {
 328         struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
 329         volatile struct iic_regs __iomem *iic = dev->vaddr;
 330
 331         DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
 332              dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
 333
 334         /* Acknowledge IRQ and wakeup iic_wait_for_tc */
 335         out_8(&iic->sts, STS_IRQA | STS_SCMP);
 336         wake_up_interruptible(&dev->wq);
 337
 338         return IRQ_HANDLED;
 339 }
 340
 341 /*
 342  * Get master transfer result and clear errors if any.
 343  * Returns the number of actually transferred bytes or error (<0)
 344  */
 345 static int iic_xfer_result(struct ibm_iic_private* dev)
 346 {
 347         volatile struct iic_regs __iomem *iic = dev->vaddr;
 348
 349         if (unlikely(in_8(&iic->sts) & STS_ERR)){
 350                 DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
 351                         in_8(&iic->extsts));
 352
 353                 /* Clear errors and possible pending IRQs */
 354                 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
 355                         EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
 356
 357                 /* Flush master data buffer */
 358                 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
 359
 360                 /* Is bus free?
 361                  * If error happened during combined xfer
 362                  * IIC interface is usually stuck in some strange
 363                  * state, the only way out - soft reset.
 364                  */
 365                 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 366                         DBG("%d: bus is stuck, resetting\n", dev->idx);
 367                         iic_dev_reset(dev);
 368                 }
 369                 return -EREMOTEIO;
 370         }
 371         else
 372                 return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
 373 }
 374
 375 /*
 376  * Try to abort active transfer.
 377  */
 378 static void iic_abort_xfer(struct ibm_iic_private* dev)
 379 {
 380         volatile struct iic_regs __iomem *iic = dev->vaddr;
 381         unsigned long x;
 382
 383         DBG("%d: iic_abort_xfer\n", dev->idx);
 384
 385         out_8(&iic->cntl, CNTL_HMT);
 386
 387         /*
 388          * Wait for the abort command to complete.
 389          * It's not worth to be optimized, just poll (timeout >= 1 tick)
 390          */
 391         x = jiffies + 2;
 392         while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 393                 if (time_after(jiffies, x)){
 394                         DBG("%d: abort timeout, resetting...\n", dev->idx);
 395                         iic_dev_reset(dev);
 396                         return;
 397                 }
 398                 schedule();
 399         }
 400
 401         /* Just to clear errors */
 402         iic_xfer_result(dev);
 403 }
 404
 405 /*
 406  * Wait for master transfer to complete.
 407  * It puts current process to sleep until we get interrupt or timeout expires.
 408  * Returns the number of transferred bytes or error (<0)
 409  */
 410 static int iic_wait_for_tc(struct ibm_iic_private* dev){
 411
 412         volatile struct iic_regs __iomem *iic = dev->vaddr;
 413         int ret = 0;
 414
 415         if (dev->irq >= 0){
 416                 /* Interrupt mode */
 417                 ret = wait_event_interruptible_timeout(dev->wq,
 418                         !(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
 419
 420                 if (unlikely(ret < 0))
 421                         DBG("%d: wait interrupted\n", dev->idx);
 422                 else if (unlikely(in_8(&iic->sts) & STS_PT)){
 423                         DBG("%d: wait timeout\n", dev->idx);
 424                         ret = -ETIMEDOUT;
 425                 }
 426         }
 427         else {
 428                 /* Polling mode */
 429                 unsigned long x = jiffies + dev->adap.timeout;
 430
 431                 while (in_8(&iic->sts) & STS_PT){
 432                         if (unlikely(time_after(jiffies, x))){
 433                                 DBG("%d: poll timeout\n", dev->idx);
 434                                 ret = -ETIMEDOUT;
 435                                 break;
 436                         }
 437
 438                         if (unlikely(signal_pending(current))){
 439                                 DBG("%d: poll interrupted\n", dev->idx);
 440                                 ret = -ERESTARTSYS;
 441                                 break;
 442                         }
 443                         schedule();
 444                 }
 445         }
 446
 447         if (unlikely(ret < 0))
 448                 iic_abort_xfer(dev);
 449         else
 450                 ret = iic_xfer_result(dev);
 451
 452         DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
 453
 454         return ret;
 455 }
 456
 457 /*
 458  * Low level master transfer routine
 459  */
 460 static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
 461                           int combined_xfer)
 462 {
 463         volatile struct iic_regs __iomem *iic = dev->vaddr;
 464         char* buf = pm->buf;
 465         int i, j, loops, ret = 0;
 466         int len = pm->len;
 467
 468         u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
 469         if (pm->flags & I2C_M_RD)
 470                 cntl |= CNTL_RW;
 471
 472         loops = (len + 3) / 4;
 473         for (i = 0; i < loops; ++i, len -= 4){
 474                 int count = len > 4 ? 4 : len;
 475                 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
 476
 477                 if (!(cntl & CNTL_RW))
 478                         for (j = 0; j < count; ++j)
 479                                 out_8((void __iomem *)&iic->mdbuf, *buf++);
 480
 481                 if (i < loops - 1)
 482                         cmd |= CNTL_CHT;
 483                 else if (combined_xfer)
 484                         cmd |= CNTL_RPST;
 485
 486                 DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
 487
 488                 /* Start transfer */
 489                 out_8(&iic->cntl, cmd);
 490
 491                 /* Wait for completion */
 492                 ret = iic_wait_for_tc(dev);
 493
 494                 if (unlikely(ret < 0))
 495                         break;
 496                 else if (unlikely(ret != count)){
 497                         DBG("%d: xfer_bytes, requested %d, transferred %d\n",
 498                                 dev->idx, count, ret);
 499
 500                         /* If it's not a last part of xfer, abort it */
 501                         if (combined_xfer || (i < loops - 1))
 502                                 iic_abort_xfer(dev);
 503
 504                         ret = -EREMOTEIO;
 505                         break;
 506                 }
 507
 508                 if (cntl & CNTL_RW)
 509                         for (j = 0; j < count; ++j)
 510                                 *buf++ = in_8((void __iomem *)&iic->mdbuf);
 511         }
 512
 513         return ret > 0 ? 0 : ret;
 514 }
 515
 516 /*
 517  * Set target slave address for master transfer
 518  */
 519 static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
 520 {
 521         volatile struct iic_regs __iomem *iic = dev->vaddr;
 522         u16 addr = msg->addr;
 523
 524         DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
 525                 addr, msg->flags & I2C_M_TEN ? 10 : 7);
 526
 527         if (msg->flags & I2C_M_TEN){
 528             out_8(&iic->cntl, CNTL_AMD);
 529             out_8(&iic->lmadr, addr);
 530             out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
 531         }
 532         else {
 533             out_8(&iic->cntl, 0);
 534             out_8(&iic->lmadr, addr << 1);
 535         }
 536 }
 537
 538 static inline int iic_invalid_address(const struct i2c_msg* p)
 539 {
 540         return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
 541 }
 542
 543 static inline int iic_address_neq(const struct i2c_msg* p1,
 544                                   const struct i2c_msg* p2)
 545 {
 546         return (p1->addr != p2->addr)
 547                 || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
 548 }
 549
 550 /*
 551  * Generic master transfer entrypoint.
 552  * Returns the number of processed messages or error (<0)
 553  */
 554 static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 555 {
 556         struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
 557         volatile struct iic_regs __iomem *iic = dev->vaddr;
 558         int i, ret = 0;
 559
 560         DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
 561
 562         if (!num)
 563                 return 0;
 564
 565         /* Check the sanity of the passed messages.
 566          * Uhh, generic i2c layer is more suitable place for such code...
 567          */
 568         if (unlikely(iic_invalid_address(&msgs[0]))){
 569                 DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
 570                         msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
 571                 return -EINVAL;
 572         }
 573         for (i = 0; i < num; ++i){
 574                 if (unlikely(msgs[i].len <= 0)){
 575                         if (num == 1 && !msgs[0].len){
 576                                 /* Special case for I2C_SMBUS_QUICK emulation.
 577                                  * IBM IIC doesn't support 0-length transactions
 578                                  * so we have to emulate them using bit-banging.
 579                                  */
 580                                 return iic_smbus_quick(dev, &msgs[0]);
 581                         }
 582                         DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
 583                                 msgs[i].len, i);
 584                         return -EINVAL;
 585                 }
 586                 if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
 587                         DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
 588                         return -EINVAL;
 589                 }
 590         }
 591
 592         /* Check bus state */
 593         if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
 594                 DBG("%d: iic_xfer, bus is not free\n", dev->idx);
 595
 596                 /* Usually it means something serious has happened.
 597                  * We *cannot* have unfinished previous transfer
 598                  * so it doesn't make any sense to try to stop it.
 599                  * Probably we were not able to recover from the
 600                  * previous error.
 601                  * The only *reasonable* thing I can think of here
 602                  * is soft reset.  --ebs
 603                  */
 604                 iic_dev_reset(dev);
 605
 606                 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 607                         DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
 608                         return -EREMOTEIO;
 609                 }
 610         }
 611         else {
 612                 /* Flush master data buffer (just in case) */
 613                 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
 614         }
 615
 616         /* Load slave address */
 617         iic_address(dev, &msgs[0]);
 618
 619         /* Do real transfer */
 620         for (i = 0; i < num && !ret; ++i)
 621                 ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
 622
 623         return ret < 0 ? ret : num;
 624 }
 625
 626 static u32 iic_func(struct i2c_adapter *adap)
 627 {
 628         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 629 }
 630
 631 static const struct i2c_algorithm iic_algo = {
 632         .master_xfer    = iic_xfer,
 633         .functionality  = iic_func
 634 };
 635
 636 /*
 637  * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
 638  */
 639 static inline u8 iic_clckdiv(unsigned int opb)
 640 {
 641         /* Compatibility kludge, should go away after all cards
 642          * are fixed to fill correct value for opbfreq.
 643          * Previous driver version used hardcoded divider value 4,
 644          * it corresponds to OPB frequency from the range (40, 50] MHz
 645          */
 646         if (!opb){
 647                 printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
 648                         " fix your board specific setup\n");
 649                 opb = 50000000;
 650         }
 651
 652         /* Convert to MHz */
 653         opb /= 1000000;
 654
 655         if (opb < 20 || opb > 150){
 656                 printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
 657                         opb);
 658                 opb = opb < 20 ? 20 : 150;
 659         }
 660         return (u8)((opb + 9) / 10 - 1);
 661 }
 662
 663 static int __devinit iic_request_irq(struct platform_device *ofdev,
 664                                      struct ibm_iic_private *dev)
 665 {
 666         struct device_node *np = ofdev->dev.of_node;
 667         int irq;
 668
 669         if (iic_force_poll)
 670                 return 0;
 671
 672         irq = irq_of_parse_and_map(np, 0);
 673         if (!irq) {
 674                 dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
 675                 return 0;
 676         }
 677
 678         /* Disable interrupts until we finish initialization, assumes
 679          *  level-sensitive IRQ setup...
 680          */
 681         iic_interrupt_mode(dev, 0);
 682         if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
 683                 dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
 684                 /* Fallback to the polling mode */
 685                 return 0;
 686         }
 687
 688         return irq;
 689 }
 690
 691 /*
 692  * Register single IIC interface
 693  */
 694 static int __devinit iic_probe(struct platform_device *ofdev)
 695 {
 696         struct device_node *np = ofdev->dev.of_node;
 697         struct ibm_iic_private *dev;
 698         struct i2c_adapter *adap;
 699         const u32 *freq;
 700         int ret;
 701
 702         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 703         if (!dev) {
 704                 dev_err(&ofdev->dev, "failed to allocate device data\n");
 705                 return -ENOMEM;
 706         }
 707
 708         dev_set_drvdata(&ofdev->dev, dev);
 709
 710         dev->vaddr = of_iomap(np, 0);
 711         if (dev->vaddr == NULL) {
 712                 dev_err(&ofdev->dev, "failed to iomap device\n");
 713                 ret = -ENXIO;
 714                 goto error_cleanup;
 715         }
 716
 717         init_waitqueue_head(&dev->wq);
 718
 719         dev->irq = iic_request_irq(ofdev, dev);
 720         if (!dev->irq)
 721                 dev_warn(&ofdev->dev, "using polling mode\n");
 722
 723         /* Board specific settings */
 724         if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
 725                 dev->fast_mode = 1;
 726
 727         freq = of_get_property(np, "clock-frequency", NULL);
 728         if (freq == NULL) {
 729                 freq = of_get_property(np->parent, "clock-frequency", NULL);
 730                 if (freq == NULL) {
 731                         dev_err(&ofdev->dev, "Unable to get bus frequency\n");
 732                         ret = -EINVAL;
 733                         goto error_cleanup;
 734                 }
 735         }
 736
 737         dev->clckdiv = iic_clckdiv(*freq);
 738         dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
 739
 740         /* Initialize IIC interface */
 741         iic_dev_init(dev);
 742
 743         /* Register it with i2c layer */
 744         adap = &dev->adap;
 745         adap->dev.parent = &ofdev->dev;
 746         adap->dev.of_node = of_node_get(np);
 747         strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
 748         i2c_set_adapdata(adap, dev);
 749         adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 750         adap->algo = &iic_algo;
 751         adap->timeout = HZ;
 752
 753         ret = i2c_add_adapter(adap);
 754         if (ret  < 0) {
 755                 dev_err(&ofdev->dev, "failed to register i2c adapter\n");
 756                 goto error_cleanup;
 757         }
 758
 759         dev_info(&ofdev->dev, "using %s mode\n",
 760                  dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
 761
 762         /* Now register all the child nodes */
 763         of_i2c_register_devices(adap);
 764
 765         return 0;
 766
 767 error_cleanup:
 768         if (dev->irq) {
 769                 iic_interrupt_mode(dev, 0);
 770                 free_irq(dev->irq, dev);
 771         }
 772
 773         if (dev->vaddr)
 774                 iounmap(dev->vaddr);
 775
 776         dev_set_drvdata(&ofdev->dev, NULL);
 777         kfree(dev);
 778         return ret;
 779 }
 780
 781 /*
 782  * Cleanup initialized IIC interface
 783  */
 784 static int __devexit iic_remove(struct platform_device *ofdev)
 785 {
 786         struct ibm_iic_private *dev = dev_get_drvdata(&ofdev->dev);
 787
 788         dev_set_drvdata(&ofdev->dev, NULL);
 789
 790         i2c_del_adapter(&dev->adap);
 791
 792         if (dev->irq) {
 793                 iic_interrupt_mode(dev, 0);
 794                 free_irq(dev->irq, dev);
 795         }
 796
 797         iounmap(dev->vaddr);
 798         kfree(dev);
 799
 800         return 0;
 801 }
 802
 803 static const struct of_device_id ibm_iic_match[] = {
 804         { .compatible = "ibm,iic", },
 805         {}
 806 };
 807
 808 static struct platform_driver ibm_iic_driver = {
 809         .driver = {
 810                 .name = "ibm-iic",
 811                 .owner = THIS_MODULE,
 812                 .of_match_table = ibm_iic_match,
 813         },
 814         .probe  = iic_probe,
 815         .remove = __devexit_p(iic_remove),
 816 };
 817
 818 static int __init iic_init(void)
 819 {
 820         return platform_driver_register(&ibm_iic_driver);
 821 }
 822
 823 static void __exit iic_exit(void)
 824 {
 825         platform_driver_unregister(&ibm_iic_driver);
 826 }
 827
 828 module_init(iic_init);
 829 module_exit(iic_exit);