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This client driver allows you to use a GPIO pin as a source for PPS
[linux-2.6/next.git] / drivers / i2c / busses / i2c-omap.c
blob5df938ff0e919530b4b81dee95b3eff638087dd6
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40 #include <linux/slab.h>
41 #include <linux/i2c-omap.h>
42 #include <linux/pm_runtime.h>
43
44 /* I2C controller revisions */
45 #define OMAP_I2C_OMAP1_REV_2 0x20
46
47 /* I2C controller revisions present on specific hardware */
48 #define OMAP_I2C_REV_ON_2430 0x36
49 #define OMAP_I2C_REV_ON_3430 0x3C
50 #define OMAP_I2C_REV_ON_3530_4430 0x40
51
52 /* timeout waiting for the controller to respond */
53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 enum {
57 OMAP_I2C_REV_REG = 0,
58 OMAP_I2C_IE_REG,
59 OMAP_I2C_STAT_REG,
60 OMAP_I2C_IV_REG,
61 OMAP_I2C_WE_REG,
62 OMAP_I2C_SYSS_REG,
63 OMAP_I2C_BUF_REG,
64 OMAP_I2C_CNT_REG,
65 OMAP_I2C_DATA_REG,
66 OMAP_I2C_SYSC_REG,
67 OMAP_I2C_CON_REG,
68 OMAP_I2C_OA_REG,
69 OMAP_I2C_SA_REG,
70 OMAP_I2C_PSC_REG,
71 OMAP_I2C_SCLL_REG,
72 OMAP_I2C_SCLH_REG,
73 OMAP_I2C_SYSTEST_REG,
74 OMAP_I2C_BUFSTAT_REG,
75 /* only on OMAP4430 */
76 OMAP_I2C_IP_V2_REVNB_LO,
77 OMAP_I2C_IP_V2_REVNB_HI,
78 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
79 OMAP_I2C_IP_V2_IRQENABLE_SET,
80 OMAP_I2C_IP_V2_IRQENABLE_CLR,
81 };
82
83 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
84 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
85 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
86 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
87 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
88 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
89 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
90 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
91
92 /* I2C Status Register (OMAP_I2C_STAT): */
93 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
94 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
95 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
96 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
97 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
98 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
99 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
100 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
101 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
102 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
103 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
104 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
105
106 /* I2C WE wakeup enable register */
107 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
108 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
109 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
110 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
111 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
112 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
113 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
114 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
115 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
116 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
117
118 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
119 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
120 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
121 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
122 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
123
124 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
125 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
126 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
127 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
128 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
129
130 /* I2C Configuration Register (OMAP_I2C_CON): */
131 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
132 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
133 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
134 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
135 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
136 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
137 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
138 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
139 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
140 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
141
142 /* I2C SCL time value when Master */
143 #define OMAP_I2C_SCLL_HSSCLL 8
144 #define OMAP_I2C_SCLH_HSSCLH 8
145
146 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
147 #ifdef DEBUG
148 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
149 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
150 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
151 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
152 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
153 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
154 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
155 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
156 #endif
157
158 /* OCP_SYSSTATUS bit definitions */
159 #define SYSS_RESETDONE_MASK (1 << 0)
160
161 /* OCP_SYSCONFIG bit definitions */
162 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
163 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
164 #define SYSC_ENAWAKEUP_MASK (1 << 2)
165 #define SYSC_SOFTRESET_MASK (1 << 1)
166 #define SYSC_AUTOIDLE_MASK (1 << 0)
167
168 #define SYSC_IDLEMODE_SMART 0x2
169 #define SYSC_CLOCKACTIVITY_FCLK 0x2
170
171 /* Errata definitions */
172 #define I2C_OMAP_ERRATA_I207 (1 << 0)
173 #define I2C_OMAP3_1P153 (1 << 1)
174
175 struct omap_i2c_dev {
176 struct device *dev;
177 void __iomem *base; /* virtual */
178 int irq;
179 int reg_shift; /* bit shift for I2C register addresses */
180 struct completion cmd_complete;
181 struct resource *ioarea;
182 u32 latency; /* maximum mpu wkup latency */
183 void (*set_mpu_wkup_lat)(struct device *dev,
184 long latency);
185 u32 speed; /* Speed of bus in Khz */
186 u16 cmd_err;
187 u8 *buf;
188 u8 *regs;
189 size_t buf_len;
190 struct i2c_adapter adapter;
191 u8 fifo_size; /* use as flag and value
192 * fifo_size==0 implies no fifo
193 * if set, should be trsh+1
194 */
195 u8 rev;
196 unsigned b_hw:1; /* bad h/w fixes */
197 unsigned idle:1;
198 u16 iestate; /* Saved interrupt register */
199 u16 pscstate;
200 u16 scllstate;
201 u16 sclhstate;
202 u16 bufstate;
203 u16 syscstate;
204 u16 westate;
205 u16 errata;
206 };
207
208 static const u8 reg_map_ip_v1[] = {
209 [OMAP_I2C_REV_REG] = 0x00,
210 [OMAP_I2C_IE_REG] = 0x01,
211 [OMAP_I2C_STAT_REG] = 0x02,
212 [OMAP_I2C_IV_REG] = 0x03,
213 [OMAP_I2C_WE_REG] = 0x03,
214 [OMAP_I2C_SYSS_REG] = 0x04,
215 [OMAP_I2C_BUF_REG] = 0x05,
216 [OMAP_I2C_CNT_REG] = 0x06,
217 [OMAP_I2C_DATA_REG] = 0x07,
218 [OMAP_I2C_SYSC_REG] = 0x08,
219 [OMAP_I2C_CON_REG] = 0x09,
220 [OMAP_I2C_OA_REG] = 0x0a,
221 [OMAP_I2C_SA_REG] = 0x0b,
222 [OMAP_I2C_PSC_REG] = 0x0c,
223 [OMAP_I2C_SCLL_REG] = 0x0d,
224 [OMAP_I2C_SCLH_REG] = 0x0e,
225 [OMAP_I2C_SYSTEST_REG] = 0x0f,
226 [OMAP_I2C_BUFSTAT_REG] = 0x10,
227 };
228
229 static const u8 reg_map_ip_v2[] = {
230 [OMAP_I2C_REV_REG] = 0x04,
231 [OMAP_I2C_IE_REG] = 0x2c,
232 [OMAP_I2C_STAT_REG] = 0x28,
233 [OMAP_I2C_IV_REG] = 0x34,
234 [OMAP_I2C_WE_REG] = 0x34,
235 [OMAP_I2C_SYSS_REG] = 0x90,
236 [OMAP_I2C_BUF_REG] = 0x94,
237 [OMAP_I2C_CNT_REG] = 0x98,
238 [OMAP_I2C_DATA_REG] = 0x9c,
239 [OMAP_I2C_SYSC_REG] = 0x20,
240 [OMAP_I2C_CON_REG] = 0xa4,
241 [OMAP_I2C_OA_REG] = 0xa8,
242 [OMAP_I2C_SA_REG] = 0xac,
243 [OMAP_I2C_PSC_REG] = 0xb0,
244 [OMAP_I2C_SCLL_REG] = 0xb4,
245 [OMAP_I2C_SCLH_REG] = 0xb8,
246 [OMAP_I2C_SYSTEST_REG] = 0xbC,
247 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
248 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
249 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
250 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
251 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
252 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
253 };
254
255 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
256 int reg, u16 val)
257 {
258 __raw_writew(val, i2c_dev->base +
259 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
260 }
261
262 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
263 {
264 return __raw_readw(i2c_dev->base +
265 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
266 }
267
268 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
269 {
270 struct platform_device *pdev;
271 struct omap_i2c_bus_platform_data *pdata;
272
273 WARN_ON(!dev->idle);
274
275 pdev = to_platform_device(dev->dev);
276 pdata = pdev->dev.platform_data;
277
278 pm_runtime_get_sync(&pdev->dev);
279
280 if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
281 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
282 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
283 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
284 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
285 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
286 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
287 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
288 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
289 }
290 dev->idle = 0;
291
292 /*
293 * Don't write to this register if the IE state is 0 as it can
294 * cause deadlock.
295 */
296 if (dev->iestate)
297 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
298 }
299
300 static void omap_i2c_idle(struct omap_i2c_dev *dev)
301 {
302 struct platform_device *pdev;
303 struct omap_i2c_bus_platform_data *pdata;
304 u16 iv;
305
306 WARN_ON(dev->idle);
307
308 pdev = to_platform_device(dev->dev);
309 pdata = pdev->dev.platform_data;
310
311 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
312 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
313 omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
314 else
315 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
316
317 if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
318 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
319 } else {
320 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
321
322 /* Flush posted write before the dev->idle store occurs */
323 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
324 }
325 dev->idle = 1;
326
327 pm_runtime_put_sync(&pdev->dev);
328 }
329
330 static int omap_i2c_init(struct omap_i2c_dev *dev)
331 {
332 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
333 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
334 unsigned long fclk_rate = 12000000;
335 unsigned long timeout;
336 unsigned long internal_clk = 0;
337 struct clk *fclk;
338 struct platform_device *pdev;
339 struct omap_i2c_bus_platform_data *pdata;
340
341 pdev = to_platform_device(dev->dev);
342 pdata = pdev->dev.platform_data;
343
344 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
345 /* Disable I2C controller before soft reset */
346 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
347 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
348 ~(OMAP_I2C_CON_EN));
349
350 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
351 /* For some reason we need to set the EN bit before the
352 * reset done bit gets set. */
353 timeout = jiffies + OMAP_I2C_TIMEOUT;
354 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
355 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
356 SYSS_RESETDONE_MASK)) {
357 if (time_after(jiffies, timeout)) {
358 dev_warn(dev->dev, "timeout waiting "
359 "for controller reset\n");
360 return -ETIMEDOUT;
361 }
362 msleep(1);
363 }
364
365 /* SYSC register is cleared by the reset; rewrite it */
366 if (dev->rev == OMAP_I2C_REV_ON_2430) {
367
368 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
369 SYSC_AUTOIDLE_MASK);
370
371 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
372 dev->syscstate = SYSC_AUTOIDLE_MASK;
373 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
374 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
375 __ffs(SYSC_SIDLEMODE_MASK));
376 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
377 __ffs(SYSC_CLOCKACTIVITY_MASK));
378
379 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
380 dev->syscstate);
381 /*
382 * Enabling all wakup sources to stop I2C freezing on
383 * WFI instruction.
384 * REVISIT: Some wkup sources might not be needed.
385 */
386 dev->westate = OMAP_I2C_WE_ALL;
387 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
388 dev->westate);
389 }
390 }
391 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
392
393 if (pdata->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
394 /*
395 * The I2C functional clock is the armxor_ck, so there's
396 * no need to get "armxor_ck" separately. Now, if OMAP2420
397 * always returns 12MHz for the functional clock, we can
398 * do this bit unconditionally.
399 */
400 fclk = clk_get(dev->dev, "fck");
401 fclk_rate = clk_get_rate(fclk);
402 clk_put(fclk);
403
404 /* TRM for 5912 says the I2C clock must be prescaled to be
405 * between 7 - 12 MHz. The XOR input clock is typically
406 * 12, 13 or 19.2 MHz. So we should have code that produces:
407 *
408 * XOR MHz Divider Prescaler
409 * 12 1 0
410 * 13 2 1
411 * 19.2 2 1
412 */
413 if (fclk_rate > 12000000)
414 psc = fclk_rate / 12000000;
415 }
416
417 if (!(pdata->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
418
419 /*
420 * HSI2C controller internal clk rate should be 19.2 Mhz for
421 * HS and for all modes on 2430. On 34xx we can use lower rate
422 * to get longer filter period for better noise suppression.
423 * The filter is iclk (fclk for HS) period.
424 */
425 if (dev->speed > 400 ||
426 pdata->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
427 internal_clk = 19200;
428 else if (dev->speed > 100)
429 internal_clk = 9600;
430 else
431 internal_clk = 4000;
432 fclk = clk_get(dev->dev, "fck");
433 fclk_rate = clk_get_rate(fclk) / 1000;
434 clk_put(fclk);
435
436 /* Compute prescaler divisor */
437 psc = fclk_rate / internal_clk;
438 psc = psc - 1;
439
440 /* If configured for High Speed */
441 if (dev->speed > 400) {
442 unsigned long scl;
443
444 /* For first phase of HS mode */
445 scl = internal_clk / 400;
446 fsscll = scl - (scl / 3) - 7;
447 fssclh = (scl / 3) - 5;
448
449 /* For second phase of HS mode */
450 scl = fclk_rate / dev->speed;
451 hsscll = scl - (scl / 3) - 7;
452 hssclh = (scl / 3) - 5;
453 } else if (dev->speed > 100) {
454 unsigned long scl;
455
456 /* Fast mode */
457 scl = internal_clk / dev->speed;
458 fsscll = scl - (scl / 3) - 7;
459 fssclh = (scl / 3) - 5;
460 } else {
461 /* Standard mode */
462 fsscll = internal_clk / (dev->speed * 2) - 7;
463 fssclh = internal_clk / (dev->speed * 2) - 5;
464 }
465 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
466 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
467 } else {
468 /* Program desired operating rate */
469 fclk_rate /= (psc + 1) * 1000;
470 if (psc > 2)
471 psc = 2;
472 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
473 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
474 }
475
476 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
477 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
478
479 /* SCL low and high time values */
480 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
481 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
482
483 if (dev->fifo_size) {
484 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
485 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
486 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
487 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
488 }
489
490 /* Take the I2C module out of reset: */
491 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
492
493 dev->errata = 0;
494
495 if (pdata->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
496 dev->errata |= I2C_OMAP_ERRATA_I207;
497
498 /* Enable interrupts */
499 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
500 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
501 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
502 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
503 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
504 if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
505 dev->pscstate = psc;
506 dev->scllstate = scll;
507 dev->sclhstate = sclh;
508 dev->bufstate = buf;
509 }
510 return 0;
511 }
512
513 /*
514 * Waiting on Bus Busy
515 */
516 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
517 {
518 unsigned long timeout;
519
520 timeout = jiffies + OMAP_I2C_TIMEOUT;
521 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
522 if (time_after(jiffies, timeout)) {
523 dev_warn(dev->dev, "timeout waiting for bus ready\n");
524 return -ETIMEDOUT;
525 }
526 msleep(1);
527 }
528
529 return 0;
530 }
531
532 /*
533 * Low level master read/write transaction.
534 */
535 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
536 struct i2c_msg *msg, int stop)
537 {
538 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
539 int r;
540 u16 w;
541
542 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
543 msg->addr, msg->len, msg->flags, stop);
544
545 if (msg->len == 0)
546 return -EINVAL;
547
548 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
549
550 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
551 dev->buf = msg->buf;
552 dev->buf_len = msg->len;
553
554 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
555
556 /* Clear the FIFO Buffers */
557 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
558 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
559 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
560
561 init_completion(&dev->cmd_complete);
562 dev->cmd_err = 0;
563
564 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
565
566 /* High speed configuration */
567 if (dev->speed > 400)
568 w |= OMAP_I2C_CON_OPMODE_HS;
569
570 if (msg->flags & I2C_M_TEN)
571 w |= OMAP_I2C_CON_XA;
572 if (!(msg->flags & I2C_M_RD))
573 w |= OMAP_I2C_CON_TRX;
574
575 if (!dev->b_hw && stop)
576 w |= OMAP_I2C_CON_STP;
577
578 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
579
580 /*
581 * Don't write stt and stp together on some hardware.
582 */
583 if (dev->b_hw && stop) {
584 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
585 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
586 while (con & OMAP_I2C_CON_STT) {
587 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
588
589 /* Let the user know if i2c is in a bad state */
590 if (time_after(jiffies, delay)) {
591 dev_err(dev->dev, "controller timed out "
592 "waiting for start condition to finish\n");
593 return -ETIMEDOUT;
594 }
595 cpu_relax();
596 }
597
598 w |= OMAP_I2C_CON_STP;
599 w &= ~OMAP_I2C_CON_STT;
600 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
601 }
602
603 /*
604 * REVISIT: We should abort the transfer on signals, but the bus goes
605 * into arbitration and we're currently unable to recover from it.
606 */
607 r = wait_for_completion_timeout(&dev->cmd_complete,
608 OMAP_I2C_TIMEOUT);
609 dev->buf_len = 0;
610 if (r < 0)
611 return r;
612 if (r == 0) {
613 dev_err(dev->dev, "controller timed out\n");
614 omap_i2c_init(dev);
615 return -ETIMEDOUT;
616 }
617
618 if (likely(!dev->cmd_err))
619 return 0;
620
621 /* We have an error */
622 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
623 OMAP_I2C_STAT_XUDF)) {
624 omap_i2c_init(dev);
625 return -EIO;
626 }
627
628 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
629 if (msg->flags & I2C_M_IGNORE_NAK)
630 return 0;
631 if (stop) {
632 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
633 w |= OMAP_I2C_CON_STP;
634 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
635 }
636 return -EREMOTEIO;
637 }
638 return -EIO;
639 }
640
641
642 /*
643 * Prepare controller for a transaction and call omap_i2c_xfer_msg
644 * to do the work during IRQ processing.
645 */
646 static int
647 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
648 {
649 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
650 int i;
651 int r;
652
653 omap_i2c_unidle(dev);
654
655 r = omap_i2c_wait_for_bb(dev);
656 if (r < 0)
657 goto out;
658
659 if (dev->set_mpu_wkup_lat != NULL)
660 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
661
662 for (i = 0; i < num; i++) {
663 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
664 if (r != 0)
665 break;
666 }
667
668 if (dev->set_mpu_wkup_lat != NULL)
669 dev->set_mpu_wkup_lat(dev->dev, -1);
670
671 if (r == 0)
672 r = num;
673
674 omap_i2c_wait_for_bb(dev);
675 out:
676 omap_i2c_idle(dev);
677 return r;
678 }
679
680 static u32
681 omap_i2c_func(struct i2c_adapter *adap)
682 {
683 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
684 }
685
686 static inline void
687 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
688 {
689 dev->cmd_err |= err;
690 complete(&dev->cmd_complete);
691 }
692
693 static inline void
694 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
695 {
696 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
697 }
698
699 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
700 {
701 /*
702 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
703 * Not applicable for OMAP4.
704 * Under certain rare conditions, RDR could be set again
705 * when the bus is busy, then ignore the interrupt and
706 * clear the interrupt.
707 */
708 if (stat & OMAP_I2C_STAT_RDR) {
709 /* Step 1: If RDR is set, clear it */
710 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
711
712 /* Step 2: */
713 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
714 & OMAP_I2C_STAT_BB)) {
715
716 /* Step 3: */
717 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
718 & OMAP_I2C_STAT_RDR) {
719 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
720 dev_dbg(dev->dev, "RDR when bus is busy.\n");
721 }
722
723 }
724 }
725 }
726
727 /* rev1 devices are apparently only on some 15xx */
728 #ifdef CONFIG_ARCH_OMAP15XX
729
730 static irqreturn_t
731 omap_i2c_omap1_isr(int this_irq, void *dev_id)
732 {
733 struct omap_i2c_dev *dev = dev_id;
734 u16 iv, w;
735
736 if (dev->idle)
737 return IRQ_NONE;
738
739 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
740 switch (iv) {
741 case 0x00: /* None */
742 break;
743 case 0x01: /* Arbitration lost */
744 dev_err(dev->dev, "Arbitration lost\n");
745 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
746 break;
747 case 0x02: /* No acknowledgement */
748 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
749 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
750 break;
751 case 0x03: /* Register access ready */
752 omap_i2c_complete_cmd(dev, 0);
753 break;
754 case 0x04: /* Receive data ready */
755 if (dev->buf_len) {
756 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
757 *dev->buf++ = w;
758 dev->buf_len--;
759 if (dev->buf_len) {
760 *dev->buf++ = w >> 8;
761 dev->buf_len--;
762 }
763 } else
764 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
765 break;
766 case 0x05: /* Transmit data ready */
767 if (dev->buf_len) {
768 w = *dev->buf++;
769 dev->buf_len--;
770 if (dev->buf_len) {
771 w |= *dev->buf++ << 8;
772 dev->buf_len--;
773 }
774 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
775 } else
776 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
777 break;
778 default:
779 return IRQ_NONE;
780 }
781
782 return IRQ_HANDLED;
783 }
784 #else
785 #define omap_i2c_omap1_isr NULL
786 #endif
787
788 /*
789 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
790 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
791 * them from the memory to the I2C interface.
792 */
793 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
794 {
795 unsigned long timeout = 10000;
796
797 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
798 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
799 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
800 OMAP_I2C_STAT_XDR));
801 *err |= OMAP_I2C_STAT_XUDF;
802 return -ETIMEDOUT;
803 }
804
805 cpu_relax();
806 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
807 }
808
809 if (!timeout) {
810 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
811 return 0;
812 }
813
814 return 0;
815 }
816
817 static irqreturn_t
818 omap_i2c_isr(int this_irq, void *dev_id)
819 {
820 struct omap_i2c_dev *dev = dev_id;
821 u16 bits;
822 u16 stat, w;
823 int err, count = 0;
824 struct platform_device *pdev;
825 struct omap_i2c_bus_platform_data *pdata;
826
827 pdev = to_platform_device(dev->dev);
828 pdata = pdev->dev.platform_data;
829
830 if (dev->idle)
831 return IRQ_NONE;
832
833 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
834 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
835 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
836 if (count++ == 100) {
837 dev_warn(dev->dev, "Too much work in one IRQ\n");
838 break;
839 }
840
841 err = 0;
842 complete:
843 /*
844 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
845 * acked after the data operation is complete.
846 * Ref: TRM SWPU114Q Figure 18-31
847 */
848 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
849 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
850 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
851
852 if (stat & OMAP_I2C_STAT_NACK) {
853 err |= OMAP_I2C_STAT_NACK;
854 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
855 OMAP_I2C_CON_STP);
856 }
857 if (stat & OMAP_I2C_STAT_AL) {
858 dev_err(dev->dev, "Arbitration lost\n");
859 err |= OMAP_I2C_STAT_AL;
860 }
861 /*
862 * ProDB0017052: Clear ARDY bit twice
863 */
864 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
865 OMAP_I2C_STAT_AL)) {
866 omap_i2c_ack_stat(dev, stat &
867 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
868 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
869 OMAP_I2C_STAT_ARDY));
870 omap_i2c_complete_cmd(dev, err);
871 return IRQ_HANDLED;
872 }
873 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
874 u8 num_bytes = 1;
875
876 if (dev->errata & I2C_OMAP_ERRATA_I207)
877 i2c_omap_errata_i207(dev, stat);
878
879 if (dev->fifo_size) {
880 if (stat & OMAP_I2C_STAT_RRDY)
881 num_bytes = dev->fifo_size;
882 else /* read RXSTAT on RDR interrupt */
883 num_bytes = (omap_i2c_read_reg(dev,
884 OMAP_I2C_BUFSTAT_REG)
885 >> 8) & 0x3F;
886 }
887 while (num_bytes) {
888 num_bytes--;
889 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
890 if (dev->buf_len) {
891 *dev->buf++ = w;
892 dev->buf_len--;
893 /*
894 * Data reg in 2430, omap3 and
895 * omap4 is 8 bit wide
896 */
897 if (pdata->flags &
898 OMAP_I2C_FLAG_16BIT_DATA_REG) {
899 if (dev->buf_len) {
900 *dev->buf++ = w >> 8;
901 dev->buf_len--;
902 }
903 }
904 } else {
905 if (stat & OMAP_I2C_STAT_RRDY)
906 dev_err(dev->dev,
907 "RRDY IRQ while no data"
908 " requested\n");
909 if (stat & OMAP_I2C_STAT_RDR)
910 dev_err(dev->dev,
911 "RDR IRQ while no data"
912 " requested\n");
913 break;
914 }
915 }
916 omap_i2c_ack_stat(dev,
917 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
918 continue;
919 }
920 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
921 u8 num_bytes = 1;
922 if (dev->fifo_size) {
923 if (stat & OMAP_I2C_STAT_XRDY)
924 num_bytes = dev->fifo_size;
925 else /* read TXSTAT on XDR interrupt */
926 num_bytes = omap_i2c_read_reg(dev,
927 OMAP_I2C_BUFSTAT_REG)
928 & 0x3F;
929 }
930 while (num_bytes) {
931 num_bytes--;
932 w = 0;
933 if (dev->buf_len) {
934 w = *dev->buf++;
935 dev->buf_len--;
936 /*
937 * Data reg in 2430, omap3 and
938 * omap4 is 8 bit wide
939 */
940 if (pdata->flags &
941 OMAP_I2C_FLAG_16BIT_DATA_REG) {
942 if (dev->buf_len) {
943 w |= *dev->buf++ << 8;
944 dev->buf_len--;
945 }
946 }
947 } else {
948 if (stat & OMAP_I2C_STAT_XRDY)
949 dev_err(dev->dev,
950 "XRDY IRQ while no "
951 "data to send\n");
952 if (stat & OMAP_I2C_STAT_XDR)
953 dev_err(dev->dev,
954 "XDR IRQ while no "
955 "data to send\n");
956 break;
957 }
958
959 if ((dev->errata & I2C_OMAP3_1P153) &&
960 errata_omap3_1p153(dev, &stat, &err))
961 goto complete;
962
963 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
964 }
965 omap_i2c_ack_stat(dev,
966 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
967 continue;
968 }
969 if (stat & OMAP_I2C_STAT_ROVR) {
970 dev_err(dev->dev, "Receive overrun\n");
971 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
972 }
973 if (stat & OMAP_I2C_STAT_XUDF) {
974 dev_err(dev->dev, "Transmit underflow\n");
975 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
976 }
977 }
978
979 return count ? IRQ_HANDLED : IRQ_NONE;
980 }
981
982 static const struct i2c_algorithm omap_i2c_algo = {
983 .master_xfer = omap_i2c_xfer,
984 .functionality = omap_i2c_func,
985 };
986
987 static int __devinit
988 omap_i2c_probe(struct platform_device *pdev)
989 {
990 struct omap_i2c_dev *dev;
991 struct i2c_adapter *adap;
992 struct resource *mem, *irq, *ioarea;
993 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
994 irq_handler_t isr;
995 int r;
996 u32 speed = 0;
997
998 /* NOTE: driver uses the static register mapping */
999 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1000 if (!mem) {
1001 dev_err(&pdev->dev, "no mem resource?\n");
1002 return -ENODEV;
1003 }
1004 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1005 if (!irq) {
1006 dev_err(&pdev->dev, "no irq resource?\n");
1007 return -ENODEV;
1008 }
1009
1010 ioarea = request_mem_region(mem->start, resource_size(mem),
1011 pdev->name);
1012 if (!ioarea) {
1013 dev_err(&pdev->dev, "I2C region already claimed\n");
1014 return -EBUSY;
1015 }
1016
1017 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1018 if (!dev) {
1019 r = -ENOMEM;
1020 goto err_release_region;
1021 }
1022
1023 if (pdata != NULL) {
1024 speed = pdata->clkrate;
1025 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1026 } else {
1027 speed = 100; /* Default speed */
1028 dev->set_mpu_wkup_lat = NULL;
1029 }
1030
1031 dev->speed = speed;
1032 dev->idle = 1;
1033 dev->dev = &pdev->dev;
1034 dev->irq = irq->start;
1035 dev->base = ioremap(mem->start, resource_size(mem));
1036 if (!dev->base) {
1037 r = -ENOMEM;
1038 goto err_free_mem;
1039 }
1040
1041 platform_set_drvdata(pdev, dev);
1042
1043 dev->reg_shift = (pdata->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1044
1045 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
1046 dev->regs = (u8 *)reg_map_ip_v2;
1047 else
1048 dev->regs = (u8 *)reg_map_ip_v1;
1049
1050 pm_runtime_enable(&pdev->dev);
1051 omap_i2c_unidle(dev);
1052
1053 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1054
1055 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1056 dev->errata |= I2C_OMAP3_1P153;
1057
1058 if (!(pdata->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1059 u16 s;
1060
1061 /* Set up the fifo size - Get total size */
1062 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1063 dev->fifo_size = 0x8 << s;
1064
1065 /*
1066 * Set up notification threshold as half the total available
1067 * size. This is to ensure that we can handle the status on int
1068 * call back latencies.
1069 */
1070 if (dev->rev >= OMAP_I2C_REV_ON_3530_4430) {
1071 dev->fifo_size = 0;
1072 dev->b_hw = 0; /* Disable hardware fixes */
1073 } else {
1074 dev->fifo_size = (dev->fifo_size / 2);
1075 dev->b_hw = 1; /* Enable hardware fixes */
1076 }
1077 /* calculate wakeup latency constraint for MPU */
1078 if (dev->set_mpu_wkup_lat != NULL)
1079 dev->latency = (1000000 * dev->fifo_size) /
1080 (1000 * speed / 8);
1081 }
1082
1083 /* reset ASAP, clearing any IRQs */
1084 omap_i2c_init(dev);
1085
1086 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1087 omap_i2c_isr;
1088 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1089
1090 if (r) {
1091 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1092 goto err_unuse_clocks;
1093 }
1094
1095 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
1096 pdata->rev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1097
1098 omap_i2c_idle(dev);
1099
1100 adap = &dev->adapter;
1101 i2c_set_adapdata(adap, dev);
1102 adap->owner = THIS_MODULE;
1103 adap->class = I2C_CLASS_HWMON;
1104 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1105 adap->algo = &omap_i2c_algo;
1106 adap->dev.parent = &pdev->dev;
1107
1108 /* i2c device drivers may be active on return from add_adapter() */
1109 adap->nr = pdev->id;
1110 r = i2c_add_numbered_adapter(adap);
1111 if (r) {
1112 dev_err(dev->dev, "failure adding adapter\n");
1113 goto err_free_irq;
1114 }
1115
1116 return 0;
1117
1118 err_free_irq:
1119 free_irq(dev->irq, dev);
1120 err_unuse_clocks:
1121 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1122 omap_i2c_idle(dev);
1123 iounmap(dev->base);
1124 err_free_mem:
1125 platform_set_drvdata(pdev, NULL);
1126 kfree(dev);
1127 err_release_region:
1128 release_mem_region(mem->start, resource_size(mem));
1129
1130 return r;
1131 }
1132
1133 static int
1134 omap_i2c_remove(struct platform_device *pdev)
1135 {
1136 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1137 struct resource *mem;
1138
1139 platform_set_drvdata(pdev, NULL);
1140
1141 free_irq(dev->irq, dev);
1142 i2c_del_adapter(&dev->adapter);
1143 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1144 iounmap(dev->base);
1145 kfree(dev);
1146 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1147 release_mem_region(mem->start, resource_size(mem));
1148 return 0;
1149 }
1150
1151 static struct platform_driver omap_i2c_driver = {
1152 .probe = omap_i2c_probe,
1153 .remove = omap_i2c_remove,
1154 .driver = {
1155 .name = "omap_i2c",
1156 .owner = THIS_MODULE,
1157 },
1158 };
1159
1160 /* I2C may be needed to bring up other drivers */
1161 static int __init
1162 omap_i2c_init_driver(void)
1163 {
1164 return platform_driver_register(&omap_i2c_driver);
1165 }
1166 subsys_initcall(omap_i2c_init_driver);
1167
1168 static void __exit omap_i2c_exit_driver(void)
1169 {
1170 platform_driver_unregister(&omap_i2c_driver);
1171 }
1172 module_exit(omap_i2c_exit_driver);
1173
1174 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1175 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1176 MODULE_LICENSE("GPL");
1177 MODULE_ALIAS("platform:omap_i2c");
linux-next