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This client driver allows you to use a GPIO pin as a source for PPS
[linux-2.6/next.git] / drivers / staging / rts5139 / xd.c
blob6cd53c47e04da46590a4a8c60f606e7f9850ae78
1 /* Driver for Realtek RTS51xx USB card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 * Maintainer:
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
24 */
25
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31
32 #include "debug.h"
33 #include "trace.h"
34 #include "rts51x.h"
35 #include "rts51x_transport.h"
36 #include "rts51x_scsi.h"
37 #include "rts51x_card.h"
38 #include "xd.h"
39
40 static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no);
41 static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
42 u8 start_page, u8 end_page);
43
44 static inline void xd_set_err_code(struct rts51x_chip *chip, u8 err_code)
45 {
46 struct xd_info *xd_card = &(chip->xd_card);
47
48 xd_card->err_code = err_code;
49 }
50
51 static inline int xd_check_err_code(struct rts51x_chip *chip, u8 err_code)
52 {
53 struct xd_info *xd_card = &(chip->xd_card);
54
55 return (xd_card->err_code == err_code);
56 }
57
58 static int xd_set_init_para(struct rts51x_chip *chip)
59 {
60 struct xd_info *xd_card = &(chip->xd_card);
61 int retval;
62
63 if (chip->asic_code)
64 xd_card->xd_clock = 47;
65 else
66 xd_card->xd_clock = CLK_50;
67
68 retval = switch_clock(chip, xd_card->xd_clock);
69 if (retval != STATUS_SUCCESS)
70 TRACE_RET(chip, retval);
71
72 return STATUS_SUCCESS;
73 }
74
75 static int xd_switch_clock(struct rts51x_chip *chip)
76 {
77 struct xd_info *xd_card = &(chip->xd_card);
78 int retval;
79
80 retval = rts51x_select_card(chip, XD_CARD);
81 if (retval != STATUS_SUCCESS)
82 TRACE_RET(chip, retval);
83
84 retval = switch_clock(chip, xd_card->xd_clock);
85 if (retval != STATUS_SUCCESS)
86 TRACE_RET(chip, retval);
87
88 return STATUS_SUCCESS;
89 }
90
91 static int xd_read_id(struct rts51x_chip *chip, u8 id_cmd, u8 *id_buf,
92 u8 buf_len)
93 {
94 int retval, i;
95
96 rts51x_init_cmd(chip);
97
98 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
99 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
100 XD_TRANSFER_START | XD_READ_ID);
101 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
102 XD_TRANSFER_END);
103
104 for (i = 0; i < 4; i++) {
105 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_ADDRESS1 + i), 0,
106 0);
107 }
108
109 retval = rts51x_send_cmd(chip, MODE_CR, 20);
110 if (retval != STATUS_SUCCESS)
111 TRACE_RET(chip, retval);
112
113 retval = rts51x_get_rsp(chip, 5, 20);
114
115 if (retval != STATUS_SUCCESS) {
116 rts51x_clear_xd_error(chip);
117 TRACE_RET(chip, retval);
118 }
119
120 if (id_buf && buf_len) {
121 if (buf_len > 4)
122 buf_len = 4;
123 rts51x_read_rsp_buf(chip, 1, id_buf, buf_len);
124 }
125
126 return STATUS_SUCCESS;
127 }
128
129 static void xd_assign_phy_addr(struct rts51x_chip *chip, u32 addr, u8 mode)
130 {
131 struct xd_info *xd_card = &(chip->xd_card);
132
133 switch (mode) {
134 case XD_RW_ADDR:
135 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
136 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
137 (u8) addr);
138 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
139 (u8) (addr >> 8));
140 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF,
141 (u8) (addr >> 16));
142 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
143 xd_card->addr_cycle | XD_CALC_ECC |
144 XD_BA_NO_TRANSFORM);
145 break;
146
147 case XD_ERASE_ADDR:
148 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF,
149 (u8) addr);
150 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
151 (u8) (addr >> 8));
152 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
153 (u8) (addr >> 16));
154 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
155 (xd_card->addr_cycle - 1) |
156 XD_CALC_ECC | XD_BA_NO_TRANSFORM);
157 break;
158
159 default:
160 break;
161 }
162 }
163
164 static int xd_read_redundant(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
165 int buf_len)
166 {
167 int retval, i;
168
169 rts51x_init_cmd(chip);
170
171 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
172
173 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
174 XD_TRANSFER_START | XD_READ_REDUNDANT);
175 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
176 XD_TRANSFER_END);
177
178 for (i = 0; i < 6; i++) {
179 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_PAGE_STATUS + i),
180 0, 0);
181 }
182 for (i = 0; i < 4; i++) {
183 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_RESERVED0 + i), 0,
184 0);
185 }
186 rts51x_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
187
188 retval = rts51x_send_cmd(chip, MODE_CR, 100);
189 if (retval != STATUS_SUCCESS)
190 TRACE_RET(chip, retval);
191
192 retval = rts51x_get_rsp(chip, 11, 500);
193
194 if (retval != STATUS_SUCCESS) {
195 rts51x_clear_xd_error(chip);
196 TRACE_RET(chip, retval);
197 }
198
199 if (buf && buf_len) {
200 if (buf_len > 11)
201 buf_len = 11;
202 rts51x_read_rsp_buf(chip, 1, buf, buf_len);
203 }
204
205 return STATUS_SUCCESS;
206 }
207
208 static int xd_read_data_from_ppb(struct rts51x_chip *chip, int offset, u8 *buf,
209 int buf_len)
210 {
211 int retval, i;
212
213 if (!buf || (buf_len <= 0))
214 TRACE_RET(chip, STATUS_FAIL);
215
216 rts51x_init_cmd(chip);
217
218 for (i = 0; i < buf_len; i++) {
219 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0,
220 0);
221 }
222
223 retval = rts51x_send_cmd(chip, MODE_CR, 100);
224 if (retval != STATUS_SUCCESS)
225 TRACE_RET(chip, retval);
226
227 retval = rts51x_get_rsp(chip, buf_len, 200);
228 if (retval != STATUS_SUCCESS)
229 TRACE_RET(chip, retval);
230
231 rts51x_read_rsp_buf(chip, 0, buf, buf_len);
232
233 return STATUS_SUCCESS;
234 }
235
236 static int xd_read_cis(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
237 int buf_len)
238 {
239 int retval;
240 u8 reg;
241
242 if (!buf || (buf_len < 10))
243 TRACE_RET(chip, STATUS_FAIL);
244
245 rts51x_init_cmd(chip);
246
247 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
248
249 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
250 PINGPONG_BUFFER);
251 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
252 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
253 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
254
255 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
256 XD_TRANSFER_START | XD_READ_PAGES);
257 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
258 XD_TRANSFER_END | XD_PPB_EMPTY,
259 XD_TRANSFER_END | XD_PPB_EMPTY);
260
261 retval = rts51x_send_cmd(chip, MODE_CR, 100);
262 if (retval != STATUS_SUCCESS)
263 TRACE_RET(chip, retval);
264
265 retval = rts51x_get_rsp(chip, 1, 500);
266 if (retval == STATUS_TIMEDOUT) {
267 rts51x_clear_xd_error(chip);
268 TRACE_RET(chip, retval);
269 }
270
271 RTS51X_READ_REG(chip, XD_PAGE_STATUS, &reg);
272 if (reg != XD_GPG) {
273 rts51x_clear_xd_error(chip);
274 TRACE_RET(chip, STATUS_FAIL);
275 }
276
277 RTS51X_READ_REG(chip, XD_CTL, &reg);
278
279 if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
280 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
281 if (retval != STATUS_SUCCESS)
282 TRACE_RET(chip, retval);
283 if (reg & XD_ECC1_ERROR) { /* correctable error */
284 u8 ecc_bit, ecc_byte;
285
286 RTS51X_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
287 RTS51X_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
288
289 RTS51X_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
290 ecc_bit, ecc_byte);
291 if (ecc_byte < buf_len) {
292 RTS51X_DEBUGP("Before correct: 0x%x\n",
293 buf[ecc_byte]);
294 buf[ecc_byte] ^= (1 << ecc_bit);
295 RTS51X_DEBUGP("After correct: 0x%x\n",
296 buf[ecc_byte]);
297 }
298 }
299 } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
300 RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
301 XD_STOP | XD_CLR_ERR);
302
303 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
304 if (retval != STATUS_SUCCESS)
305 TRACE_RET(chip, retval);
306 if (reg & XD_ECC2_ERROR) {
307 u8 ecc_bit, ecc_byte;
308
309 RTS51X_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
310 RTS51X_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
311
312 RTS51X_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
313 ecc_bit, ecc_byte);
314 if (ecc_byte < buf_len) {
315 RTS51X_DEBUGP("Before correct: 0x%x\n",
316 buf[ecc_byte]);
317 buf[ecc_byte] ^= (1 << ecc_bit);
318 RTS51X_DEBUGP("After correct: 0x%x\n",
319 buf[ecc_byte]);
320 }
321 }
322 } else {
323 rts51x_clear_xd_error(chip);
324 TRACE_RET(chip, STATUS_FAIL);
325 }
326
327 return STATUS_SUCCESS;
328 }
329
330 static void xd_pull_ctl_disable(struct rts51x_chip *chip)
331 {
332 if (CHECK_PKG(chip, LQFP48)) {
333 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
334 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
335 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
336 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
337 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
338 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
339 } else {
340 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
341 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
342 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
343 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
344 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
345 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
346 }
347 }
348
349 static void xd_pull_ctl_enable(struct rts51x_chip *chip)
350 {
351 if (CHECK_PKG(chip, LQFP48)) {
352 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
353 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
354 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
355 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
356 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
357 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
358 } else {
359 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA5);
360 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x59);
361 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
362 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
363 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
364 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
365 }
366 }
367
368 static int reset_xd(struct rts51x_chip *chip)
369 {
370 struct xd_info *xd_card = &(chip->xd_card);
371 int retval, i, j;
372 u8 id_buf[4], redunt[11];
373
374 retval = rts51x_select_card(chip, XD_CARD);
375 if (retval != STATUS_SUCCESS)
376 TRACE_RET(chip, STATUS_FAIL);
377
378 rts51x_init_cmd(chip);
379
380 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
381 XD_PGSTS_NOT_FF);
382 if (chip->asic_code)
383 xd_pull_ctl_disable(chip);
384 else
385 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
386 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3));
387
388 if (!chip->option.FT2_fast_mode) {
389 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF,
390 0);
391 if (CHECK_PKG(chip, LQFP48) ||
392 chip->option.rts5129_D3318_off_enable) {
393 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
394 DV3318_AUTO_PWR_OFF,
395 DV3318_AUTO_PWR_OFF);
396 }
397 }
398 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
399 if (!chip->option.FT2_fast_mode) {
400 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
401 POWER_OFF);
402 }
403
404 retval = rts51x_send_cmd(chip, MODE_C, 100);
405 if (retval != STATUS_SUCCESS)
406 TRACE_RET(chip, retval);
407 if (!chip->option.FT2_fast_mode) {
408 #ifdef SD_XD_IO_FOLLOW_PWR
409 if (CHECK_PKG(chip, LQFP48)
410 || chip->option.rts5129_D3318_off_enable) {
411 rts51x_write_register(chip, CARD_PWR_CTL,
412 LDO_OFF, LDO_OFF);
413 }
414 #endif
415
416 wait_timeout(250);
417
418 #ifdef SD_XD_IO_FOLLOW_PWR
419 if (CHECK_PKG(chip, LQFP48)
420 || chip->option.rts5129_D3318_off_enable) {
421 rts51x_init_cmd(chip);
422 if (chip->asic_code) {
423 xd_pull_ctl_enable(chip);
424 } else {
425 rts51x_add_cmd(chip, WRITE_REG_CMD,
426 FPGA_PULL_CTL, 0xFF,
427 (FPGA_XD_PULL_CTL_EN1 &
428 FPGA_XD_PULL_CTL_EN2));
429 }
430 retval = rts51x_send_cmd(chip, MODE_C, 100);
431 if (retval != STATUS_SUCCESS)
432 TRACE_RET(chip, STATUS_FAIL);
433 }
434 #endif
435
436 retval = card_power_on(chip, XD_CARD);
437 if (retval != STATUS_SUCCESS)
438 TRACE_RET(chip, retval);
439 #ifdef SUPPORT_OCP
440 wait_timeout(50);
441 rts51x_get_card_status(chip, &(chip->card_status));
442 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
443
444 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
445 RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
446 chip->ocp_stat);
447 TRACE_RET(chip, STATUS_FAIL);
448 }
449 #endif
450 }
451
452 rts51x_init_cmd(chip);
453
454 if (chip->asic_code)
455 xd_pull_ctl_enable(chip);
456 else
457 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
458 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2));
459 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN,
460 XD_OUTPUT_EN);
461 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
462
463 retval = rts51x_send_cmd(chip, MODE_C, 100);
464 if (retval != STATUS_SUCCESS)
465 TRACE_RET(chip, STATUS_FAIL);
466
467 if (!chip->option.FT2_fast_mode)
468 wait_timeout(200);
469
470 retval = xd_set_init_para(chip);
471 if (retval != STATUS_SUCCESS)
472 TRACE_RET(chip, STATUS_FAIL);
473 /* Read ID to check if the timing setting is right */
474 for (i = 0; i < 4; i++) {
475 u8 xd_dat, xd_ctl;
476
477 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
478 TRACE_RET(chip, STATUS_FAIL);
479
480 rts51x_init_cmd(chip);
481 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
482 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP *
483 (2 + i + chip->option.xd_rw_step)
484 + XD_TIME_RWN_STEP * (i + chip->option.xd_rwn_step));
485 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
486 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 +
487 i) + XD_TIME_RWN_STEP * (3 + i));
488
489 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
490 XD_TRANSFER_START | XD_RESET);
491 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
492 XD_TRANSFER_END, XD_TRANSFER_END);
493
494 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
495 rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
496
497 retval = rts51x_send_cmd(chip, MODE_CR, 100);
498 if (retval != STATUS_SUCCESS) {
499 rts51x_clear_xd_error(chip);
500 TRACE_RET(chip, retval);
501 }
502
503 retval = rts51x_get_rsp(chip, 3, 100);
504 if (retval != STATUS_SUCCESS) {
505 rts51x_clear_xd_error(chip);
506 TRACE_RET(chip, retval);
507 }
508
509 xd_dat = chip->rsp_buf[1];
510 xd_ctl = chip->rsp_buf[2];
511 RTS51X_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", xd_dat, xd_ctl);
512
513 if (((xd_dat & READY_FLAG) != READY_STATE)
514 || !(xd_ctl & XD_RDY))
515 continue;
516
517 retval = xd_read_id(chip, READ_ID, id_buf, 4);
518 if (retval != STATUS_SUCCESS)
519 TRACE_RET(chip, retval);
520
521 RTS51X_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
522 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
523
524 xd_card->device_code = id_buf[1];
525
526 switch (xd_card->device_code) {
527 case XD_4M_X8_512_1:
528 case XD_4M_X8_512_2:
529 xd_card->block_shift = 4; /* 16 pages per block */
530 xd_card->page_off = 0x0F;
531 xd_card->addr_cycle = 3;
532 xd_card->zone_cnt = 1;
533 xd_card->capacity = 8000; /* 500 * 2 ^ 4 */
534 XD_SET_4MB(xd_card);
535 break;
536 case XD_8M_X8_512:
537 xd_card->block_shift = 4;
538 xd_card->page_off = 0x0F;
539 xd_card->addr_cycle = 3;
540 xd_card->zone_cnt = 1;
541 xd_card->capacity = 16000; /* 1000 * 2 ^ 4 */
542 break;
543 case XD_16M_X8_512:
544 XD_PAGE_512(xd_card); /* 32 pages per block */
545 xd_card->addr_cycle = 3;
546 xd_card->zone_cnt = 1;
547 xd_card->capacity = 32000; /* 1000 * 2 ^ 5 */
548 break;
549 case XD_32M_X8_512:
550 XD_PAGE_512(xd_card);
551 xd_card->addr_cycle = 3;
552 xd_card->zone_cnt = 2;
553 xd_card->capacity = 64000; /* 2000 * 2 ^ 5 */
554 break;
555 case XD_64M_X8_512:
556 XD_PAGE_512(xd_card);
557 xd_card->addr_cycle = 4;
558 xd_card->zone_cnt = 4;
559 xd_card->capacity = 128000; /* 4000 * 2 ^ 5 */
560 break;
561 case XD_128M_X8_512:
562 XD_PAGE_512(xd_card);
563 xd_card->addr_cycle = 4;
564 xd_card->zone_cnt = 8;
565 xd_card->capacity = 256000; /* 8000 * 2 ^ 5 */
566 break;
567 case XD_256M_X8_512:
568 XD_PAGE_512(xd_card);
569 xd_card->addr_cycle = 4;
570 xd_card->zone_cnt = 16;
571 xd_card->capacity = 512000; /* 16000 * 2 ^ 5 */
572 break;
573 case XD_512M_X8:
574 XD_PAGE_512(xd_card);
575 xd_card->addr_cycle = 4;
576 xd_card->zone_cnt = 32;
577 xd_card->capacity = 1024000; /* 32000 * 2 ^ 5 */
578 break;
579 case xD_1G_X8_512:
580 XD_PAGE_512(xd_card);
581 xd_card->addr_cycle = 4;
582 xd_card->zone_cnt = 64;
583 xd_card->capacity = 2048000; /* 64000 * 2 ^ 5 */
584 break;
585 case xD_2G_X8_512:
586 XD_PAGE_512(xd_card);
587 xd_card->addr_cycle = 4;
588 xd_card->zone_cnt = 128;
589 xd_card->capacity = 4096000; /* 128000 * 2 ^ 5 */
590 break;
591 default:
592 continue;
593 }
594
595 /* Confirm timing setting */
596 for (j = 0; j < 10; j++) {
597 retval = xd_read_id(chip, READ_ID, id_buf, 4);
598 if (retval != STATUS_SUCCESS)
599 TRACE_RET(chip, retval);
600
601 if (id_buf[1] != xd_card->device_code)
602 break;
603 }
604
605 /* Current timing pass */
606 if (j == 10)
607 break;
608 }
609
610 if (i == 4) {
611 xd_card->block_shift = 0;
612 xd_card->page_off = 0;
613 xd_card->addr_cycle = 0;
614 xd_card->capacity = 0;
615
616 TRACE_RET(chip, STATUS_FAIL);
617 }
618
619 retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
620 if (retval != STATUS_SUCCESS)
621 TRACE_RET(chip, retval);
622 RTS51X_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
623 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
624 if (id_buf[2] != XD_ID_CODE)
625 TRACE_RET(chip, STATUS_FAIL);
626
627 /* Search CIS block */
628 for (i = 0; i < 24; i++) {
629 u32 page_addr;
630
631 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
632 TRACE_RET(chip, STATUS_FAIL);
633
634 page_addr = (u32) i << xd_card->block_shift;
635
636 for (j = 0; j < 3; j++) {
637 retval = xd_read_redundant(chip, page_addr, redunt, 11);
638 if (retval == STATUS_SUCCESS)
639 break;
640 }
641 if (j == 3)
642 continue;
643
644 if (redunt[BLOCK_STATUS] != XD_GBLK)
645 continue;
646
647 j = 0;
648 /* Check page status */
649 if (redunt[PAGE_STATUS] != XD_GPG) {
650 for (j = 1; j <= 8; j++) {
651 retval =
652 xd_read_redundant(chip, page_addr + j,
653 redunt, 11);
654 if (retval == STATUS_SUCCESS) {
655 if (redunt[PAGE_STATUS] == XD_GPG)
656 break;
657 }
658 }
659
660 if (j == 9)
661 break;
662 }
663
664 if ((redunt[BLOCK_STATUS] == XD_GBLK)
665 && (redunt[PARITY] & XD_BA1_ALL0)) {
666 u8 buf[10];
667
668 page_addr += j;
669
670 retval = xd_read_cis(chip, page_addr, buf, 10);
671 if (retval != STATUS_SUCCESS)
672 TRACE_RET(chip, retval);
673
674 if ((buf[0] == 0x01) && (buf[1] == 0x03)
675 && (buf[2] == 0xD9)
676 && (buf[3] == 0x01) && (buf[4] == 0xFF)
677 && (buf[5] == 0x18) && (buf[6] == 0x02)
678 && (buf[7] == 0xDF) && (buf[8] == 0x01)
679 && (buf[9] == 0x20)) {
680 xd_card->cis_block = (u16) i;
681 }
682 }
683
684 break;
685 }
686
687 RTS51X_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block);
688 if (xd_card->cis_block == 0xFFFF)
689 TRACE_RET(chip, STATUS_FAIL);
690
691 chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
692
693 return STATUS_SUCCESS;
694 }
695
696 static int xd_check_data_blank(u8 *redunt)
697 {
698 int i;
699
700 for (i = 0; i < 6; i++) {
701 if (redunt[PAGE_STATUS + i] != 0xFF)
702 return 0;
703 }
704
705 if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) !=
706 (XD_ECC1_ALL1 | XD_ECC2_ALL1))
707 return 0;
708
709 for (i = 0; i < 4; i++) {
710 if (redunt[RESERVED0 + i] != 0xFF)
711 return 0;
712 }
713
714 return 1;
715 }
716
717 static u16 xd_load_log_block_addr(u8 *redunt)
718 {
719 u16 addr = 0xFFFF;
720
721 if (redunt[PARITY] & XD_BA1_BA2_EQL)
722 addr =
723 ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
724 else if (redunt[PARITY] & XD_BA1_VALID)
725 addr =
726 ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
727 else if (redunt[PARITY] & XD_BA2_VALID)
728 addr =
729 ((u16) redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L];
730
731 return addr;
732 }
733
734 static int xd_init_l2p_tbl(struct rts51x_chip *chip)
735 {
736 struct xd_info *xd_card = &(chip->xd_card);
737 int size, i;
738
739 RTS51X_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt);
740
741 if (xd_card->zone_cnt < 1)
742 TRACE_RET(chip, STATUS_FAIL);
743
744 size = xd_card->zone_cnt * sizeof(struct zone_entry);
745 RTS51X_DEBUGP("Buffer size for l2p table is %d\n", size);
746
747 xd_card->zone = vmalloc(size);
748 if (!xd_card->zone)
749 TRACE_RET(chip, STATUS_NOMEM);
750
751 for (i = 0; i < xd_card->zone_cnt; i++) {
752 xd_card->zone[i].build_flag = 0;
753 xd_card->zone[i].l2p_table = NULL;
754 xd_card->zone[i].free_table = NULL;
755 xd_card->zone[i].get_index = 0;
756 xd_card->zone[i].set_index = 0;
757 xd_card->zone[i].unused_blk_cnt = 0;
758 }
759
760 return STATUS_SUCCESS;
761 }
762
763 static inline void free_zone(struct zone_entry *zone)
764 {
765 RTS51X_DEBUGP("free_zone\n");
766 if (!zone)
767 return;
768 zone->build_flag = 0;
769 zone->set_index = 0;
770 zone->get_index = 0;
771 zone->unused_blk_cnt = 0;
772 if (zone->l2p_table) {
773 vfree(zone->l2p_table);
774 zone->l2p_table = NULL;
775 }
776 if (zone->free_table) {
777 vfree(zone->free_table);
778 zone->free_table = NULL;
779 }
780 }
781
782 static void xd_set_unused_block(struct rts51x_chip *chip, u32 phy_blk)
783 {
784 struct xd_info *xd_card = &(chip->xd_card);
785 struct zone_entry *zone;
786 int zone_no;
787
788 zone_no = (int)phy_blk >> 10;
789 if (zone_no >= xd_card->zone_cnt) {
790 RTS51X_DEBUGP("Set unused block to invalid zone"
791 "(zone_no = %d, zone_cnt = %d)\n",
792 zone_no, xd_card->zone_cnt);
793 return;
794 }
795 zone = &(xd_card->zone[zone_no]);
796
797 if (zone->free_table == NULL) {
798 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
799 return;
800 }
801
802 if ((zone->set_index >= XD_FREE_TABLE_CNT)
803 || (zone->set_index < 0)) {
804 free_zone(zone);
805 RTS51X_DEBUGP("Set unused block fail, invalid set_index\n");
806 return;
807 }
808
809 RTS51X_DEBUGP("Set unused block to index %d\n", zone->set_index);
810
811 zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
812 if (zone->set_index >= XD_FREE_TABLE_CNT)
813 zone->set_index = 0;
814 zone->unused_blk_cnt++;
815 }
816
817 static u32 xd_get_unused_block(struct rts51x_chip *chip, int zone_no)
818 {
819 struct xd_info *xd_card = &(chip->xd_card);
820 struct zone_entry *zone;
821 u32 phy_blk;
822
823 if (zone_no >= xd_card->zone_cnt) {
824 RTS51X_DEBUGP("Get unused block from invalid zone"
825 "(zone_no = %d, zone_cnt = %d)\n",
826 zone_no, xd_card->zone_cnt);
827 TRACE_RET(chip, BLK_NOT_FOUND);
828 }
829 zone = &(xd_card->zone[zone_no]);
830
831 if ((zone->unused_blk_cnt == 0) ||
832 (zone->set_index == zone->get_index)) {
833 free_zone(zone);
834 RTS51X_DEBUGP("Get unused block fail,"
835 "no unused block available\n");
836 TRACE_RET(chip, BLK_NOT_FOUND);
837 }
838 if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
839 free_zone(zone);
840 RTS51X_DEBUGP("Get unused block fail, invalid get_index\n");
841 TRACE_RET(chip, BLK_NOT_FOUND);
842 }
843
844 RTS51X_DEBUGP("Get unused block from index %d\n", zone->get_index);
845
846 phy_blk = zone->free_table[zone->get_index];
847 zone->free_table[zone->get_index++] = 0xFFFF;
848 if (zone->get_index >= XD_FREE_TABLE_CNT)
849 zone->get_index = 0;
850 zone->unused_blk_cnt--;
851
852 phy_blk += ((u32) (zone_no) << 10);
853 return phy_blk;
854 }
855
856 static void xd_set_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off,
857 u16 phy_off)
858 {
859 struct xd_info *xd_card = &(chip->xd_card);
860 struct zone_entry *zone;
861
862 zone = &(xd_card->zone[zone_no]);
863 zone->l2p_table[log_off] = phy_off;
864 }
865
866 static u32 xd_get_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off)
867 {
868 struct xd_info *xd_card = &(chip->xd_card);
869 struct zone_entry *zone;
870 int retval;
871
872 zone = &(xd_card->zone[zone_no]);
873 if (zone->l2p_table[log_off] == 0xFFFF) {
874 u32 phy_blk = 0;
875 int i;
876
877 retval = xd_delay_write(chip);
878 if (retval != STATUS_SUCCESS) {
879 RTS51X_DEBUGP("In xd_get_l2p_tbl,"
880 "delay write fail!\n");
881 TRACE_RET(chip, BLK_NOT_FOUND);
882 }
883
884 if (zone->unused_blk_cnt <= 0) {
885 RTS51X_DEBUGP("No unused block!\n");
886 TRACE_RET(chip, BLK_NOT_FOUND);
887 }
888
889 for (i = 0; i < zone->unused_blk_cnt; i++) {
890 phy_blk = xd_get_unused_block(chip, zone_no);
891 if (phy_blk == BLK_NOT_FOUND) {
892 RTS51X_DEBUGP("No unused block available!\n");
893 TRACE_RET(chip, BLK_NOT_FOUND);
894 }
895
896 retval =
897 xd_init_page(chip, phy_blk, log_off, 0,
898 xd_card->page_off + 1);
899 if (retval == STATUS_SUCCESS)
900 break;
901 }
902 if (i >= zone->unused_blk_cnt) {
903 RTS51X_DEBUGP("No good unused block available!\n");
904 TRACE_RET(chip, BLK_NOT_FOUND);
905 }
906
907 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (phy_blk & 0x3FF));
908 return phy_blk;
909 }
910
911 return (u32) zone->l2p_table[log_off] + ((u32) (zone_no) << 10);
912 }
913
914 int reset_xd_card(struct rts51x_chip *chip)
915 {
916 struct xd_info *xd_card = &(chip->xd_card);
917 int retval;
918
919 memset(xd_card, 0, sizeof(struct xd_info));
920
921 xd_card->block_shift = 0;
922 xd_card->page_off = 0;
923 xd_card->addr_cycle = 0;
924 xd_card->capacity = 0;
925 xd_card->zone_cnt = 0;
926 xd_card->cis_block = 0xFFFF;
927 xd_card->delay_write.delay_write_flag = 0;
928
929 enable_card_clock(chip, XD_CARD);
930
931 retval = reset_xd(chip);
932 if (retval != STATUS_SUCCESS) {
933 if (chip->option.reset_or_rw_fail_set_pad_drive) {
934 rts51x_write_register(chip, CARD_DRIVE_SEL,
935 SD20_DRIVE_MASK, DRIVE_8mA);
936 }
937 TRACE_RET(chip, retval);
938 }
939
940 retval = xd_init_l2p_tbl(chip);
941 if (retval != STATUS_SUCCESS)
942 TRACE_RET(chip, retval);
943
944 return STATUS_SUCCESS;
945 }
946
947 static int xd_mark_bad_block(struct rts51x_chip *chip, u32 phy_blk)
948 {
949 struct xd_info *xd_card = &(chip->xd_card);
950 int retval;
951 u32 page_addr;
952 u8 reg = 0;
953
954 RTS51X_DEBUGP("mark block 0x%x as bad block\n", phy_blk);
955
956 if (phy_blk == BLK_NOT_FOUND)
957 TRACE_RET(chip, STATUS_FAIL);
958
959 rts51x_init_cmd(chip);
960
961 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
962 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF,
963 XD_LATER_BBLK);
964 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
965 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
966 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
967 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
968 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
969 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
970 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
971 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
972
973 page_addr = phy_blk << xd_card->block_shift;
974
975 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
976
977 /* Specify page count */
978 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
979 xd_card->page_off + 1);
980
981 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
982 XD_TRANSFER_START | XD_WRITE_REDUNDANT);
983 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
984 XD_TRANSFER_END);
985
986 retval = rts51x_send_cmd(chip, MODE_CR, 100);
987 if (retval != STATUS_SUCCESS)
988 TRACE_RET(chip, STATUS_FAIL);
989
990 retval = rts51x_get_rsp(chip, 1, 100);
991
992 if (retval != STATUS_SUCCESS) {
993 rts51x_clear_xd_error(chip);
994 rts51x_ep0_read_register(chip, XD_DAT, &reg);
995 if (reg & PROGRAM_ERROR)
996 xd_set_err_code(chip, XD_PRG_ERROR);
997 else
998 xd_set_err_code(chip, XD_TO_ERROR);
999 TRACE_RET(chip, STATUS_FAIL);
1000 }
1001
1002 return STATUS_SUCCESS;
1003 }
1004
1005 static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
1006 u8 start_page, u8 end_page)
1007 {
1008 struct xd_info *xd_card = &(chip->xd_card);
1009 int retval;
1010 u32 page_addr;
1011 u8 reg = 0;
1012
1013 RTS51X_DEBUGP("Init block 0x%x\n", phy_blk);
1014
1015 if (start_page > end_page)
1016 TRACE_RET(chip, STATUS_FAIL);
1017 if (phy_blk == BLK_NOT_FOUND)
1018 TRACE_RET(chip, STATUS_FAIL);
1019
1020 rts51x_init_cmd(chip);
1021
1022 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1023 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1024 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1025 (u8) (logoff >> 8));
1026 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1027 (u8) logoff);
1028
1029 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1030
1031 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1032
1033 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1034 XD_BA_TRANSFORM);
1035
1036 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1037 (end_page - start_page));
1038
1039 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1040 XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1041 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1042 XD_TRANSFER_END);
1043
1044 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1045 if (retval != STATUS_SUCCESS)
1046 TRACE_RET(chip, STATUS_FAIL);
1047
1048 retval = rts51x_get_rsp(chip, 1, 500);
1049
1050 if (retval != STATUS_SUCCESS) {
1051 rts51x_clear_xd_error(chip);
1052 rts51x_ep0_read_register(chip, XD_DAT, &reg);
1053 if (reg & PROGRAM_ERROR) {
1054 xd_mark_bad_block(chip, phy_blk);
1055 xd_set_err_code(chip, XD_PRG_ERROR);
1056 } else {
1057 xd_set_err_code(chip, XD_TO_ERROR);
1058 }
1059 TRACE_RET(chip, STATUS_FAIL);
1060 }
1061
1062 return STATUS_SUCCESS;
1063 }
1064
1065 static int xd_copy_page(struct rts51x_chip *chip,
1066 u32 old_blk, u32 new_blk, u8 start_page, u8 end_page)
1067 {
1068 struct xd_info *xd_card = &(chip->xd_card);
1069 u32 old_page, new_page;
1070 u8 i, reg = 0;
1071 int retval;
1072
1073 RTS51X_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk,
1074 new_blk);
1075
1076 if (start_page > end_page)
1077 TRACE_RET(chip, STATUS_FAIL);
1078
1079 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1080 TRACE_RET(chip, STATUS_FAIL);
1081
1082 old_page = (old_blk << xd_card->block_shift) + start_page;
1083 new_page = (new_blk << xd_card->block_shift) + start_page;
1084
1085 XD_CLR_BAD_NEWBLK(xd_card);
1086
1087 RTS51X_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1088
1089 for (i = start_page; i < end_page; i++) {
1090 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1091 RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
1092 XD_STOP | XD_CLR_ERR);
1093 xd_set_err_code(chip, XD_NO_CARD);
1094 TRACE_RET(chip, STATUS_FAIL);
1095 }
1096
1097 rts51x_init_cmd(chip);
1098
1099 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1100
1101 /* Single page read */
1102 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1103 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1104 XD_AUTO_CHK_DATA_STATUS, 0);
1105 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1106 XD_TRANSFER_START | XD_READ_PAGES);
1107 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1108 XD_TRANSFER_END, XD_TRANSFER_END);
1109
1110 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_XD_STATUS, 100);
1111 if (retval != STATUS_SUCCESS)
1112 TRACE_RET(chip, retval);
1113
1114 retval = rts51x_get_rsp(chip, 4, 500);
1115 if ((retval != STATUS_SUCCESS) ||
1116 (chip->rsp_buf[2] & (XD_ECC1_ERROR | XD_ECC2_ERROR))) {
1117 rts51x_clear_xd_error(chip);
1118 reg = 0;
1119 rts51x_ep0_read_register(chip, XD_CTL, &reg);
1120 if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1121 wait_timeout(100);
1122
1123 if (monitor_card_cd(chip, XD_CARD) ==
1124 CD_NOT_EXIST) {
1125 xd_set_err_code(chip, XD_NO_CARD);
1126 TRACE_RET(chip, STATUS_FAIL);
1127 }
1128
1129 if (((reg &
1130 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1131 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1132 || ((reg & (XD_ECC2_ERROR |
1133 XD_ECC2_UNCORRECTABLE)) ==
1134 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1135 RTS51X_WRITE_REG(chip, XD_PAGE_STATUS,
1136 0xFF, XD_BPG);
1137 RTS51X_WRITE_REG(chip, XD_BLOCK_STATUS,
1138 0xFF, XD_GBLK);
1139 XD_SET_BAD_OLDBLK(xd_card);
1140 RTS51X_DEBUGP("old block 0x%x"
1141 "ecc error\n", old_blk);
1142 }
1143 } else {
1144 xd_set_err_code(chip, XD_TO_ERROR);
1145 TRACE_RET(chip, STATUS_FAIL);
1146 }
1147 }
1148 if (XD_CHK_BAD_OLDBLK(xd_card))
1149 rts51x_clear_xd_error(chip);
1150
1151 rts51x_init_cmd(chip);
1152
1153 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1154 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1155 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1156 XD_TRANSFER_START | XD_WRITE_PAGES);
1157 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1158 XD_TRANSFER_END, XD_TRANSFER_END);
1159
1160 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1161 if (retval != STATUS_SUCCESS)
1162 TRACE_RET(chip, retval);
1163
1164 retval = rts51x_get_rsp(chip, 1, 300);
1165 if (retval != STATUS_SUCCESS) {
1166 rts51x_clear_xd_error(chip);
1167 reg = 0;
1168 rts51x_ep0_read_register(chip, XD_DAT, &reg);
1169 if (reg & PROGRAM_ERROR) {
1170 xd_mark_bad_block(chip, new_blk);
1171 xd_set_err_code(chip, XD_PRG_ERROR);
1172 XD_SET_BAD_NEWBLK(xd_card);
1173 } else {
1174 xd_set_err_code(chip, XD_TO_ERROR);
1175 }
1176 TRACE_RET(chip, retval);
1177 }
1178
1179 old_page++;
1180 new_page++;
1181 }
1182
1183 return STATUS_SUCCESS;
1184 }
1185
1186 #ifdef XD_SPEEDUP
1187 static int xd_auto_copy_page(struct rts51x_chip *chip,
1188 u32 old_blk, u32 new_blk,
1189 u8 start_page, u8 end_page)
1190 {
1191 struct xd_info *xd_card = &(chip->xd_card);
1192 u32 old_page, new_page;
1193 int retval;
1194 u8 page_count;
1195
1196 RTS51X_DEBUGP("Auto copy page from block 0x%x to block 0x%x\n",
1197 old_blk, new_blk);
1198
1199 if (start_page > end_page)
1200 TRACE_RET(chip, STATUS_FAIL);
1201
1202 page_count = end_page - start_page;
1203
1204 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1205 TRACE_RET(chip, STATUS_FAIL);
1206
1207 old_page = (old_blk << xd_card->block_shift) + start_page;
1208 new_page = (new_blk << xd_card->block_shift) + start_page;
1209
1210 XD_CLR_BAD_NEWBLK(xd_card);
1211
1212 rts51x_init_cmd(chip);
1213
1214 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WAITTIME, 0x03, WAIT_FF);
1215 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_PAGELEN, 0xFF, page_count);
1216
1217 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR0, 0xFF, 0);
1218 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR1, 0xFF,
1219 (u8) old_page);
1220 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR2, 0xFF,
1221 (u8) (old_page >> 8));
1222 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR3, 0xFF,
1223 (u8) (old_page >> 16));
1224 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR4, 0xFF, 0);
1225
1226 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR0, 0xFF, 0);
1227 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR1, 0xFF,
1228 (u8) new_page);
1229 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR2, 0xFF,
1230 (u8) (new_page >> 8));
1231 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR3, 0xFF,
1232 (u8) (new_page >> 16));
1233 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR4, 0xFF, 0);
1234
1235 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1236 PINGPONG_BUFFER);
1237
1238 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1239 XD_BA_TRANSFORM | XD_ADDR_MASK, 0 | xd_card->addr_cycle);
1240
1241 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1242 XD_AUTO_CHK_DATA_STATUS, 0);
1243 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1244 XD_TRANSFER_START | XD_COPY_PAGES);
1245 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1246 XD_TRANSFER_END);
1247
1248 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1249 if (retval != STATUS_SUCCESS) {
1250 rts51x_clear_xd_error(chip);
1251 TRACE_GOTO(chip, Copy_Fail);
1252 }
1253
1254 retval = rts51x_get_rsp(chip, 1, 800);
1255 if (retval != STATUS_SUCCESS) {
1256 rts51x_clear_xd_error(chip);
1257 TRACE_GOTO(chip, Copy_Fail);
1258 }
1259
1260 return STATUS_SUCCESS;
1261
1262 Copy_Fail:
1263 retval = xd_copy_page(chip, old_blk, new_blk, start_page, end_page);
1264 if (retval != STATUS_SUCCESS)
1265 TRACE_RET(chip, retval);
1266
1267 return STATUS_SUCCESS;
1268 }
1269 #endif
1270
1271 static int xd_reset_cmd(struct rts51x_chip *chip)
1272 {
1273 int retval;
1274 u8 xd_dat, xd_ctl;
1275
1276 rts51x_init_cmd(chip);
1277
1278 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1279 XD_TRANSFER_START | XD_RESET);
1280 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1281 XD_TRANSFER_END);
1282 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1283 rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1284
1285 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1286 if (retval != STATUS_SUCCESS)
1287 TRACE_RET(chip, retval);
1288
1289 retval = rts51x_get_rsp(chip, 3, 100);
1290 if (retval != STATUS_SUCCESS) {
1291 rts51x_clear_xd_error(chip);
1292 TRACE_RET(chip, retval);
1293 }
1294
1295 xd_dat = chip->rsp_buf[1];
1296 xd_ctl = chip->rsp_buf[2];
1297 if (((xd_dat & READY_FLAG) == READY_STATE) && (xd_ctl & XD_RDY))
1298 return STATUS_SUCCESS;
1299
1300 TRACE_RET(chip, STATUS_FAIL);
1301 }
1302
1303 static int xd_erase_block(struct rts51x_chip *chip, u32 phy_blk)
1304 {
1305 struct xd_info *xd_card = &(chip->xd_card);
1306 u32 page_addr;
1307 u8 reg = 0, xd_dat;
1308 int i, retval;
1309
1310 if (phy_blk == BLK_NOT_FOUND)
1311 TRACE_RET(chip, STATUS_FAIL);
1312
1313 page_addr = phy_blk << xd_card->block_shift;
1314
1315 for (i = 0; i < 3; i++) {
1316 rts51x_init_cmd(chip);
1317
1318 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1319
1320 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1321 XD_TRANSFER_START | XD_ERASE);
1322 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1323 XD_TRANSFER_END, XD_TRANSFER_END);
1324 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1325
1326 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1327 if (retval != STATUS_SUCCESS)
1328 TRACE_RET(chip, retval);
1329
1330 retval = rts51x_get_rsp(chip, 2, 300);
1331 if (retval != STATUS_SUCCESS) {
1332 rts51x_clear_xd_error(chip);
1333 rts51x_ep0_read_register(chip, XD_DAT, &reg);
1334 if (reg & PROGRAM_ERROR) {
1335 xd_mark_bad_block(chip, phy_blk);
1336 xd_set_err_code(chip, XD_PRG_ERROR);
1337 TRACE_RET(chip, STATUS_FAIL);
1338 } else {
1339 xd_set_err_code(chip, XD_ERASE_FAIL);
1340 }
1341 retval = xd_reset_cmd(chip);
1342 if (retval != STATUS_SUCCESS)
1343 TRACE_RET(chip, retval);
1344 continue;
1345 }
1346 xd_dat = chip->rsp_buf[1];
1347 if (xd_dat & PROGRAM_ERROR) {
1348 xd_mark_bad_block(chip, phy_blk);
1349 xd_set_err_code(chip, XD_PRG_ERROR);
1350 TRACE_RET(chip, STATUS_FAIL);
1351 }
1352
1353 return STATUS_SUCCESS;
1354 }
1355
1356 xd_mark_bad_block(chip, phy_blk);
1357 xd_set_err_code(chip, XD_ERASE_FAIL);
1358 TRACE_RET(chip, STATUS_FAIL);
1359 }
1360
1361 static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no)
1362 {
1363 struct xd_info *xd_card = &(chip->xd_card);
1364 struct zone_entry *zone;
1365 int retval;
1366 u32 start, end, i;
1367 u16 max_logoff, cur_fst_page_logoff, cur_lst_page_logoff,
1368 ent_lst_page_logoff;
1369 u8 redunt[11];
1370
1371 RTS51X_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no);
1372
1373 if (xd_card->zone == NULL) {
1374 retval = xd_init_l2p_tbl(chip);
1375 if (retval != STATUS_SUCCESS)
1376 TRACE_RET(chip, retval);
1377 }
1378
1379 if (xd_card->zone[zone_no].build_flag) {
1380 RTS51X_DEBUGP("l2p table of zone %d has been built\n",
1381 zone_no);
1382 return STATUS_SUCCESS;
1383 }
1384
1385 zone = &(xd_card->zone[zone_no]);
1386
1387 if (zone->l2p_table == NULL) {
1388 zone->l2p_table = vmalloc(2000);
1389 if (zone->l2p_table == NULL)
1390 TRACE_GOTO(chip, Build_Fail);
1391 }
1392 memset((u8 *) (zone->l2p_table), 0xff, 2000);
1393
1394 if (zone->free_table == NULL) {
1395 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1396 if (zone->free_table == NULL)
1397 TRACE_GOTO(chip, Build_Fail);
1398 }
1399 memset((u8 *) (zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1400
1401 if (zone_no == 0) {
1402 if (xd_card->cis_block == 0xFFFF)
1403 start = 0;
1404 else
1405 start = xd_card->cis_block + 1;
1406 if (XD_CHK_4MB(xd_card)) {
1407 end = 0x200;
1408 max_logoff = 499;
1409 } else {
1410 end = 0x400;
1411 max_logoff = 999;
1412 }
1413 } else {
1414 start = (u32) (zone_no) << 10;
1415 end = (u32) (zone_no + 1) << 10;
1416 max_logoff = 999;
1417 }
1418
1419 RTS51X_DEBUGP("start block 0x%x, end block 0x%x\n", start, end);
1420
1421 zone->set_index = zone->get_index = 0;
1422 zone->unused_blk_cnt = 0;
1423
1424 for (i = start; i < end; i++) {
1425 u32 page_addr = i << xd_card->block_shift;
1426 u32 phy_block;
1427
1428 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1429 if (retval != STATUS_SUCCESS)
1430 continue;
1431
1432 if (redunt[BLOCK_STATUS] != 0xFF) {
1433 RTS51X_DEBUGP("bad block\n");
1434 continue;
1435 }
1436
1437 if (xd_check_data_blank(redunt)) {
1438 RTS51X_DEBUGP("blank block\n");
1439 xd_set_unused_block(chip, i);
1440 continue;
1441 }
1442
1443 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1444 if ((cur_fst_page_logoff == 0xFFFF)
1445 || (cur_fst_page_logoff > max_logoff)) {
1446 retval = xd_erase_block(chip, i);
1447 if (retval == STATUS_SUCCESS)
1448 xd_set_unused_block(chip, i);
1449 continue;
1450 }
1451 if ((zone_no == 0) && (cur_fst_page_logoff == 0)
1452 && (redunt[PAGE_STATUS] != XD_GPG))
1453 XD_SET_MBR_FAIL(xd_card);
1454
1455 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1456 zone->l2p_table[cur_fst_page_logoff] =
1457 (u16) (i & 0x3FF);
1458 continue;
1459 }
1460
1461 phy_block =
1462 zone->l2p_table[cur_fst_page_logoff] +
1463 ((u32) ((zone_no) << 10));
1464
1465 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1466
1467 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1468 if (retval != STATUS_SUCCESS)
1469 continue;
1470
1471 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1472 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1473 int m;
1474
1475 page_addr =
1476 ((phy_block + 1) << xd_card->block_shift) - 1;
1477
1478 for (m = 0; m < 3; m++) {
1479 retval =
1480 xd_read_redundant(chip, page_addr, redunt,
1481 11);
1482 if (retval == STATUS_SUCCESS)
1483 break;
1484 }
1485
1486 if (m == 3) {
1487 zone->l2p_table[cur_fst_page_logoff] =
1488 (u16) (i & 0x3FF);
1489 retval = xd_erase_block(chip, phy_block);
1490 if (retval == STATUS_SUCCESS)
1491 xd_set_unused_block(chip, phy_block);
1492 continue;
1493 }
1494
1495 ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1496 if (ent_lst_page_logoff != cur_fst_page_logoff) {
1497 zone->l2p_table[cur_fst_page_logoff] =
1498 (u16) (i & 0x3FF);
1499 retval = xd_erase_block(chip, phy_block);
1500 if (retval == STATUS_SUCCESS)
1501 xd_set_unused_block(chip, phy_block);
1502 continue;
1503 } else {
1504 retval = xd_erase_block(chip, i);
1505 if (retval == STATUS_SUCCESS)
1506 xd_set_unused_block(chip, i);
1507 }
1508 } else {
1509 retval = xd_erase_block(chip, i);
1510 if (retval == STATUS_SUCCESS)
1511 xd_set_unused_block(chip, i);
1512 }
1513 }
1514
1515 if (XD_CHK_4MB(xd_card))
1516 end = 500;
1517 else
1518 end = 1000;
1519
1520 i = 0;
1521 for (start = 0; start < end; start++) {
1522 if (zone->l2p_table[start] == 0xFFFF)
1523 i++;
1524 }
1525
1526 RTS51X_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i);
1527 RTS51X_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt);
1528
1529 if ((zone->unused_blk_cnt - i) < 1)
1530 chip->card_wp |= XD_CARD;
1531
1532 zone->build_flag = 1;
1533
1534 return STATUS_SUCCESS;
1535
1536 Build_Fail:
1537 if (zone->l2p_table) {
1538 vfree(zone->l2p_table);
1539 zone->l2p_table = NULL;
1540 }
1541 if (zone->free_table) {
1542 vfree(zone->free_table);
1543 zone->free_table = NULL;
1544 }
1545
1546 return STATUS_FAIL;
1547 }
1548
1549 static int xd_send_cmd(struct rts51x_chip *chip, u8 cmd)
1550 {
1551 int retval;
1552
1553 rts51x_init_cmd(chip);
1554
1555 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1556 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1557 XD_TRANSFER_START | XD_SET_CMD);
1558 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1559 XD_TRANSFER_END);
1560
1561 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1562 if (retval != STATUS_SUCCESS)
1563 TRACE_RET(chip, retval);
1564
1565 retval = rts51x_get_rsp(chip, 1, 200);
1566 if (retval != STATUS_SUCCESS) {
1567 rts51x_clear_xd_error(chip);
1568 TRACE_RET(chip, retval);
1569 }
1570
1571 return STATUS_SUCCESS;
1572 }
1573
1574 static int xd_read_multiple_pages(struct rts51x_chip *chip, u32 phy_blk,
1575 u32 log_blk, u8 start_page, u8 end_page,
1576 u8 *buf, void **ptr, unsigned int *offset)
1577 {
1578 struct xd_info *xd_card = &(chip->xd_card);
1579 u32 page_addr, new_blk;
1580 u16 log_off;
1581 u8 reg_val, page_cnt;
1582 int zone_no, retval, i;
1583
1584 if (start_page > end_page)
1585 TRACE_RET(chip, STATUS_FAIL);
1586
1587 page_cnt = end_page - start_page;
1588 zone_no = (int)(log_blk / 1000);
1589 log_off = (u16) (log_blk % 1000);
1590
1591 if ((phy_blk & 0x3FF) == 0x3FF) {
1592 for (i = 0; i < 256; i++) {
1593 page_addr = ((u32) i) << xd_card->block_shift;
1594
1595 retval = xd_read_redundant(chip, page_addr, NULL, 0);
1596 if (retval == STATUS_SUCCESS)
1597 break;
1598
1599 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1600 xd_set_err_code(chip, XD_NO_CARD);
1601 TRACE_RET(chip, STATUS_FAIL);
1602 }
1603 }
1604 }
1605
1606 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1607
1608 rts51x_init_cmd(chip);
1609
1610 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1611
1612 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE,
1613 XD_PPB_TO_SIE);
1614 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1615 RING_BUFFER);
1616 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1617 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1618 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1619
1620 trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512,
1621 DMA_512);
1622
1623 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1624 XD_TRANSFER_START | XD_READ_PAGES);
1625 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1626 XD_TRANSFER_END | XD_PPB_EMPTY,
1627 XD_TRANSFER_END | XD_PPB_EMPTY);
1628
1629 retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
1630 if (retval != STATUS_SUCCESS)
1631 TRACE_RET(chip, retval);
1632
1633 retval =
1634 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip), (void *)buf,
1635 ptr, offset, page_cnt * 512,
1636 scsi_sg_count(chip->srb), NULL, 2000);
1637 if (retval != STATUS_SUCCESS) {
1638 rts51x_clear_xd_error(chip);
1639
1640 if (retval == STATUS_TIMEDOUT) {
1641 xd_set_err_code(chip, XD_TO_ERROR);
1642 TRACE_RET(chip, retval);
1643 } else {
1644 TRACE_GOTO(chip, Fail);
1645 }
1646 }
1647 retval = rts51x_get_rsp(chip, 1, 200);
1648 if (retval != STATUS_SUCCESS) {
1649 rts51x_clear_xd_error(chip);
1650
1651 if (retval == STATUS_TIMEDOUT) {
1652 xd_set_err_code(chip, XD_TO_ERROR);
1653 TRACE_RET(chip, retval);
1654 } else {
1655 TRACE_GOTO(chip, Fail);
1656 }
1657 }
1658
1659 return STATUS_SUCCESS;
1660
1661 Fail:
1662 rts51x_ep0_read_register(chip, XD_PAGE_STATUS, &reg_val);
1663 RTS51X_DEBUGP("XD_PAGE_STATUS: 0x%x\n", reg_val);
1664
1665 if (reg_val != XD_GPG)
1666 xd_set_err_code(chip, XD_PRG_ERROR);
1667
1668 rts51x_ep0_read_register(chip, XD_CTL, &reg_val);
1669 RTS51X_DEBUGP("XD_CTL: 0x%x\n", reg_val);
1670
1671 /* Handle uncorrectable ECC error */
1672 if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1673 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1674 || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1675 == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1676 wait_timeout(100);
1677
1678 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1679 xd_set_err_code(chip, XD_NO_CARD);
1680 TRACE_RET(chip, STATUS_FAIL);
1681 }
1682
1683 xd_set_err_code(chip, XD_ECC_ERROR);
1684
1685 new_blk = xd_get_unused_block(chip, zone_no);
1686 if (new_blk == NO_NEW_BLK) {
1687 XD_CLR_BAD_OLDBLK(xd_card);
1688 TRACE_RET(chip, STATUS_FAIL);
1689 }
1690 #ifdef XD_SPEEDUP
1691 retval =
1692 xd_auto_copy_page(chip, phy_blk, new_blk, 0,
1693 xd_card->page_off + 1);
1694 #else
1695 retval =
1696 xd_copy_page(chip, phy_blk, new_blk, 0,
1697 xd_card->page_off + 1);
1698 #endif
1699 if (retval != STATUS_SUCCESS) {
1700 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1701 retval = xd_erase_block(chip, new_blk);
1702 if (retval == STATUS_SUCCESS)
1703 xd_set_unused_block(chip, new_blk);
1704 } else {
1705 XD_CLR_BAD_NEWBLK(xd_card);
1706 }
1707 XD_CLR_BAD_OLDBLK(xd_card);
1708 TRACE_RET(chip, STATUS_FAIL);
1709 }
1710 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1711 xd_erase_block(chip, phy_blk);
1712 xd_mark_bad_block(chip, phy_blk);
1713 XD_CLR_BAD_OLDBLK(xd_card);
1714 }
1715
1716 TRACE_RET(chip, STATUS_FAIL);
1717 }
1718
1719 static int xd_finish_write(struct rts51x_chip *chip,
1720 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1721 {
1722 struct xd_info *xd_card = &(chip->xd_card);
1723 int retval, zone_no;
1724 u16 log_off;
1725
1726 RTS51X_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x,"
1727 "log_blk = 0x%x\n", old_blk, new_blk, log_blk);
1728
1729 if (page_off > xd_card->page_off)
1730 TRACE_RET(chip, STATUS_FAIL);
1731
1732 zone_no = (int)(log_blk / 1000);
1733 log_off = (u16) (log_blk % 1000);
1734
1735 if (old_blk == BLK_NOT_FOUND) {
1736 retval = xd_init_page(chip, new_blk, log_off,
1737 page_off, xd_card->page_off + 1);
1738 if (retval != STATUS_SUCCESS) {
1739 retval = xd_erase_block(chip, new_blk);
1740 if (retval == STATUS_SUCCESS)
1741 xd_set_unused_block(chip, new_blk);
1742 TRACE_RET(chip, STATUS_FAIL);
1743 }
1744 } else {
1745 #ifdef XD_SPEEDUP
1746 retval = xd_auto_copy_page(chip, old_blk, new_blk,
1747 page_off, xd_card->page_off + 1);
1748 #else
1749 retval = xd_copy_page(chip, old_blk, new_blk,
1750 page_off, xd_card->page_off + 1);
1751 #endif
1752 if (retval != STATUS_SUCCESS) {
1753 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1754 retval = xd_erase_block(chip, new_blk);
1755 if (retval == STATUS_SUCCESS)
1756 xd_set_unused_block(chip, new_blk);
1757 }
1758 XD_CLR_BAD_NEWBLK(xd_card);
1759 TRACE_RET(chip, STATUS_FAIL);
1760 }
1761
1762 retval = xd_erase_block(chip, old_blk);
1763 if (retval == STATUS_SUCCESS) {
1764 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1765 xd_mark_bad_block(chip, old_blk);
1766 XD_CLR_BAD_OLDBLK(xd_card);
1767 } else {
1768 /* Add source block to unused block */
1769 xd_set_unused_block(chip, old_blk);
1770 }
1771 } else {
1772 xd_set_err_code(chip, XD_NO_ERROR);
1773 XD_CLR_BAD_OLDBLK(xd_card);
1774 }
1775 }
1776
1777 /* Add target block to L2P table */
1778 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1779
1780 return STATUS_SUCCESS;
1781 }
1782
1783 static int xd_prepare_write(struct rts51x_chip *chip,
1784 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1785 {
1786 int retval;
1787
1788 RTS51X_DEBUGP("xd_prepare_write, old_blk = 0x%x, new_blk = 0x%x,"
1789 "log_blk = 0x%x, page_off = %d\n",
1790 old_blk, new_blk, log_blk, (int)page_off);
1791
1792 if (page_off) {
1793 #ifdef XD_SPEEDUP
1794 retval = xd_auto_copy_page(chip, old_blk, new_blk, 0, page_off);
1795 #else
1796 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1797 #endif
1798 if (retval != STATUS_SUCCESS)
1799 TRACE_RET(chip, retval);
1800 }
1801
1802 return STATUS_SUCCESS;
1803 }
1804
1805 static int xd_write_multiple_pages(struct rts51x_chip *chip, u32 old_blk,
1806 u32 new_blk, u32 log_blk, u8 start_page,
1807 u8 end_page, u8 *buf, void **ptr,
1808 unsigned int *offset)
1809 {
1810 struct xd_info *xd_card = &(chip->xd_card);
1811 u32 page_addr;
1812 int zone_no, retval;
1813 u16 log_off;
1814 u8 page_cnt, reg_val;
1815
1816 RTS51X_DEBUGP("xd_write_multiple_pages, old_blk = 0x%x,"
1817 "new_blk = 0x%x, log_blk = 0x%x\n",
1818 old_blk, new_blk, log_blk);
1819
1820 if (start_page > end_page)
1821 TRACE_RET(chip, STATUS_FAIL);
1822
1823 page_cnt = end_page - start_page;
1824 zone_no = (int)(log_blk / 1000);
1825 log_off = (u16) (log_blk % 1000);
1826
1827 page_addr = (new_blk << xd_card->block_shift) + start_page;
1828
1829 /* Send index command */
1830 retval = xd_send_cmd(chip, READ1_1);
1831 if (retval != STATUS_SUCCESS)
1832 TRACE_RET(chip, retval);
1833
1834 rts51x_init_cmd(chip);
1835
1836 /* Prepare redundant field */
1837 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1838 (u8) (log_off >> 8));
1839 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1840 (u8) log_off);
1841 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1842 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1843
1844 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1845
1846 /* Transform the block address by hardware */
1847 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1848 XD_BA_TRANSFORM);
1849
1850 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1851 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1852 RING_BUFFER);
1853
1854 trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512,
1855 DMA_512);
1856
1857 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1858 XD_TRANSFER_START | XD_WRITE_PAGES);
1859 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1860 XD_TRANSFER_END);
1861
1862 retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
1863 if (retval != STATUS_SUCCESS)
1864 TRACE_RET(chip, retval);
1865
1866 retval =
1867 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip), (void *)buf,
1868 ptr, offset, page_cnt * 512,
1869 scsi_sg_count(chip->srb), NULL, 2000);
1870 if (retval != STATUS_SUCCESS) {
1871 rts51x_clear_xd_error(chip);
1872
1873 if (retval == STATUS_TIMEDOUT) {
1874 xd_set_err_code(chip, XD_TO_ERROR);
1875 TRACE_RET(chip, retval);
1876 } else {
1877 TRACE_GOTO(chip, Fail);
1878 }
1879 }
1880 retval = rts51x_get_rsp(chip, 1, 200);
1881 if (retval != STATUS_SUCCESS) {
1882 rts51x_clear_xd_error(chip);
1883
1884 if (retval == STATUS_TIMEDOUT) {
1885 xd_set_err_code(chip, XD_TO_ERROR);
1886 TRACE_RET(chip, retval);
1887 } else {
1888 TRACE_GOTO(chip, Fail);
1889 }
1890 }
1891
1892 if (end_page == (xd_card->page_off + 1)) {
1893 xd_card->delay_write.delay_write_flag = 0;
1894
1895 if (old_blk != BLK_NOT_FOUND) {
1896 retval = xd_erase_block(chip, old_blk);
1897 if (retval == STATUS_SUCCESS) {
1898 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1899 xd_mark_bad_block(chip, old_blk);
1900 XD_CLR_BAD_OLDBLK(xd_card);
1901 } else {
1902 xd_set_unused_block(chip, old_blk);
1903 }
1904 } else {
1905 xd_set_err_code(chip, XD_NO_ERROR);
1906 XD_CLR_BAD_OLDBLK(xd_card);
1907 }
1908 }
1909 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1910 }
1911
1912 return STATUS_SUCCESS;
1913
1914 Fail:
1915 rts51x_ep0_read_register(chip, XD_DAT, &reg_val);
1916 RTS51X_DEBUGP("XD_DAT: 0x%x\n", reg_val);
1917
1918 if (reg_val & PROGRAM_ERROR) {
1919 xd_set_err_code(chip, XD_PRG_ERROR);
1920 xd_mark_bad_block(chip, new_blk);
1921 }
1922
1923 TRACE_RET(chip, STATUS_FAIL);
1924 }
1925
1926 int xd_delay_write(struct rts51x_chip *chip)
1927 {
1928 struct xd_info *xd_card = &(chip->xd_card);
1929 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1930 int retval;
1931
1932 if (delay_write->delay_write_flag) {
1933 RTS51X_DEBUGP("xd_delay_write\n");
1934 retval = xd_switch_clock(chip);
1935 if (retval != STATUS_SUCCESS)
1936 TRACE_RET(chip, retval);
1937
1938 delay_write->delay_write_flag = 0;
1939 retval = xd_finish_write(chip,
1940 delay_write->old_phyblock,
1941 delay_write->new_phyblock,
1942 delay_write->logblock,
1943 delay_write->pageoff);
1944 if (retval != STATUS_SUCCESS)
1945 TRACE_RET(chip, retval);
1946 }
1947
1948 return STATUS_SUCCESS;
1949 }
1950
1951 int xd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,
1952 u16 sector_cnt)
1953 {
1954 struct xd_info *xd_card = &(chip->xd_card);
1955 unsigned int lun = SCSI_LUN(srb);
1956 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1957 int retval, zone_no;
1958 u32 log_blk, old_blk = 0, new_blk = 0;
1959 u16 log_off, total_sec_cnt = sector_cnt;
1960 u8 start_page, end_page = 0, page_cnt;
1961 u8 *buf;
1962 void *ptr = NULL;
1963 unsigned int offset = 0;
1964
1965 xd_set_err_code(chip, XD_NO_ERROR);
1966
1967 xd_card->counter = 0;
1968
1969 RTS51X_DEBUGP("xd_rw: scsi_bufflen = %d, scsi_sg_count = %d\n",
1970 scsi_bufflen(srb), scsi_sg_count(srb));
1971 RTS51X_DEBUGP("Data direction: %s\n",
1972 (srb->sc_data_direction ==
1973 DMA_TO_DEVICE) ? "write" : "read");
1974
1975 buf = (u8 *) scsi_sglist(srb);
1976
1977 retval = xd_switch_clock(chip);
1978 if (retval != STATUS_SUCCESS)
1979 TRACE_RET(chip, retval);
1980
1981 log_blk = start_sector >> xd_card->block_shift;
1982 start_page = (u8) start_sector & xd_card->page_off;
1983 zone_no = (int)(log_blk / 1000);
1984 log_off = (u16) (log_blk % 1000);
1985
1986 RTS51X_DEBUGP("log_blk = 0x%x\n", log_blk);
1987
1988 if (xd_card->zone[zone_no].build_flag == 0) {
1989 retval = xd_build_l2p_tbl(chip, zone_no);
1990 if (retval != STATUS_SUCCESS) {
1991 chip->card_fail |= XD_CARD;
1992 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1993 TRACE_RET(chip, retval);
1994 }
1995 }
1996
1997 if (srb->sc_data_direction == DMA_TO_DEVICE) {
1998 if (delay_write->delay_write_flag &&
1999 (delay_write->logblock == log_blk) &&
2000 (start_page > delay_write->pageoff)) {
2001 delay_write->delay_write_flag = 0;
2002 if (delay_write->old_phyblock != BLK_NOT_FOUND) {
2003 #ifdef XD_SPEEDUP
2004 retval = xd_auto_copy_page(chip,
2005 delay_write->old_phyblock,
2006 delay_write->new_phyblock,
2007 delay_write->pageoff, start_page);
2008 #else
2009 retval = xd_copy_page(chip,
2010 delay_write->old_phyblock,
2011 delay_write->new_phyblock,
2012 delay_write->pageoff,
2013 start_page);
2014 #endif
2015 if (retval != STATUS_SUCCESS) {
2016 set_sense_type(chip, lun,
2017 SENSE_TYPE_MEDIA_WRITE_ERR);
2018 TRACE_RET(chip, retval);
2019 }
2020 }
2021 old_blk = delay_write->old_phyblock;
2022 new_blk = delay_write->new_phyblock;
2023 } else if (delay_write->delay_write_flag &&
2024 (delay_write->logblock == log_blk) &&
2025 (start_page == delay_write->pageoff)) {
2026 delay_write->delay_write_flag = 0;
2027 old_blk = delay_write->old_phyblock;
2028 new_blk = delay_write->new_phyblock;
2029 } else {
2030 retval = xd_delay_write(chip);
2031 if (retval != STATUS_SUCCESS) {
2032 set_sense_type(chip, lun,
2033 SENSE_TYPE_MEDIA_WRITE_ERR);
2034 TRACE_RET(chip, retval);
2035 }
2036 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2037 new_blk = xd_get_unused_block(chip, zone_no);
2038 if ((old_blk == BLK_NOT_FOUND)
2039 || (new_blk == BLK_NOT_FOUND)) {
2040 set_sense_type(chip, lun,
2041 SENSE_TYPE_MEDIA_WRITE_ERR);
2042 TRACE_RET(chip, retval);
2043 }
2044
2045 retval =
2046 xd_prepare_write(chip, old_blk, new_blk, log_blk,
2047 start_page);
2048 if (retval != STATUS_SUCCESS) {
2049 if (monitor_card_cd(chip, XD_CARD) ==
2050 CD_NOT_EXIST) {
2051 set_sense_type(chip, lun,
2052 SENSE_TYPE_MEDIA_NOT_PRESENT);
2053 TRACE_RET(chip, STATUS_FAIL);
2054 }
2055 set_sense_type(chip, lun,
2056 SENSE_TYPE_MEDIA_WRITE_ERR);
2057 TRACE_RET(chip, retval);
2058 }
2059 }
2060 } else {
2061 retval = xd_delay_write(chip);
2062 if (retval != STATUS_SUCCESS) {
2063 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
2064 set_sense_type(chip, lun,
2065 SENSE_TYPE_MEDIA_NOT_PRESENT);
2066 TRACE_RET(chip, STATUS_FAIL);
2067 }
2068 set_sense_type(chip, lun,
2069 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2070 TRACE_RET(chip, retval);
2071 }
2072
2073 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2074 if (old_blk == BLK_NOT_FOUND) {
2075 set_sense_type(chip, lun,
2076 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2077 TRACE_RET(chip, STATUS_FAIL);
2078 }
2079 }
2080
2081 RTS51X_DEBUGP("old_blk = 0x%x\n", old_blk);
2082 if (srb->sc_data_direction == DMA_TO_DEVICE)
2083 RTS51X_DEBUGP("new_blk = 0x%x\n", new_blk);
2084
2085 while (total_sec_cnt) {
2086 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
2087 end_page = xd_card->page_off + 1;
2088 else
2089 end_page = start_page + (u8) total_sec_cnt;
2090 page_cnt = end_page - start_page;
2091 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2092 retval = xd_read_multiple_pages(chip, old_blk, log_blk,
2093 start_page, end_page,
2094 buf, &ptr, &offset);
2095 if (retval != STATUS_SUCCESS) {
2096 set_sense_type(chip, lun,
2097 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2098 TRACE_RET(chip, STATUS_FAIL);
2099 }
2100 } else {
2101 retval =
2102 xd_write_multiple_pages(chip, old_blk, new_blk,
2103 log_blk, start_page,
2104 end_page, buf, &ptr,
2105 &offset);
2106 if (retval != STATUS_SUCCESS) {
2107 set_sense_type(chip, lun,
2108 SENSE_TYPE_MEDIA_WRITE_ERR);
2109 TRACE_RET(chip, STATUS_FAIL);
2110 }
2111 }
2112
2113 total_sec_cnt -= page_cnt;
2114
2115 if (total_sec_cnt == 0)
2116 break;
2117
2118 log_blk++;
2119 zone_no = (int)(log_blk / 1000);
2120 log_off = (u16) (log_blk % 1000);
2121
2122 if (xd_card->zone[zone_no].build_flag == 0) {
2123 retval = xd_build_l2p_tbl(chip, zone_no);
2124 if (retval != STATUS_SUCCESS) {
2125 chip->card_fail |= XD_CARD;
2126 set_sense_type(chip, lun,
2127 SENSE_TYPE_MEDIA_NOT_PRESENT);
2128 TRACE_RET(chip, retval);
2129 }
2130 }
2131
2132 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2133 if (old_blk == BLK_NOT_FOUND) {
2134 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2135 set_sense_type(chip, lun,
2136 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2137 } else {
2138 set_sense_type(chip, lun,
2139 SENSE_TYPE_MEDIA_WRITE_ERR);
2140 }
2141 TRACE_RET(chip, STATUS_FAIL);
2142 }
2143
2144 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2145 new_blk = xd_get_unused_block(chip, zone_no);
2146 if (new_blk == BLK_NOT_FOUND) {
2147 set_sense_type(chip, lun,
2148 SENSE_TYPE_MEDIA_WRITE_ERR);
2149 TRACE_RET(chip, STATUS_FAIL);
2150 }
2151 }
2152
2153 start_page = 0;
2154 }
2155
2156 if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2157 (end_page != (xd_card->page_off + 1))) {
2158 delay_write->delay_write_flag = 1;
2159 delay_write->old_phyblock = old_blk;
2160 delay_write->new_phyblock = new_blk;
2161 delay_write->logblock = log_blk;
2162 delay_write->pageoff = end_page;
2163 }
2164
2165 scsi_set_resid(srb, 0);
2166
2167 return STATUS_SUCCESS;
2168 }
2169
2170 void xd_free_l2p_tbl(struct rts51x_chip *chip)
2171 {
2172 struct xd_info *xd_card = &(chip->xd_card);
2173 int i = 0;
2174
2175 if (xd_card->zone != NULL) {
2176 for (i = 0; i < xd_card->zone_cnt; i++) {
2177 if (xd_card->zone[i].l2p_table != NULL) {
2178 vfree(xd_card->zone[i].l2p_table);
2179 xd_card->zone[i].l2p_table = NULL;
2180 }
2181 if (xd_card->zone[i].free_table != NULL) {
2182 vfree(xd_card->zone[i].free_table);
2183 xd_card->zone[i].free_table = NULL;
2184 }
2185 }
2186 vfree(xd_card->zone);
2187 xd_card->zone = NULL;
2188 }
2189 }
2190
2191 void xd_cleanup_work(struct rts51x_chip *chip)
2192 {
2193 struct xd_info *xd_card = &(chip->xd_card);
2194
2195 if (xd_card->delay_write.delay_write_flag) {
2196 RTS51X_DEBUGP("xD: delay write\n");
2197 xd_delay_write(chip);
2198 xd_card->counter = 0;
2199 }
2200 }
2201
2202 int xd_power_off_card3v3(struct rts51x_chip *chip)
2203 {
2204 int retval;
2205
2206 rts51x_init_cmd(chip);
2207
2208 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
2209
2210 if (chip->asic_code)
2211 xd_pull_ctl_disable(chip);
2212 else
2213 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 0xDF);
2214 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
2215 if (!chip->option.FT2_fast_mode) {
2216 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
2217 POWER_OFF);
2218 if (CHECK_PKG(chip, LQFP48)
2219 || chip->option.rts5129_D3318_off_enable)
2220 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
2221 DV3318_AUTO_PWR_OFF, 0);
2222 }
2223
2224 retval = rts51x_send_cmd(chip, MODE_C, 100);
2225 if (retval != STATUS_SUCCESS)
2226 TRACE_RET(chip, retval);
2227
2228 return STATUS_SUCCESS;
2229 }
2230
2231 int release_xd_card(struct rts51x_chip *chip)
2232 {
2233 struct xd_info *xd_card = &(chip->xd_card);
2234 int retval;
2235
2236 RTS51X_DEBUGP("elease_xd_card\n");
2237
2238 chip->card_ready &= ~XD_CARD;
2239 chip->card_fail &= ~XD_CARD;
2240 chip->card_wp &= ~XD_CARD;
2241
2242 xd_card->delay_write.delay_write_flag = 0;
2243
2244 xd_free_l2p_tbl(chip);
2245
2246 rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
2247
2248 retval = xd_power_off_card3v3(chip);
2249 if (retval != STATUS_SUCCESS)
2250 TRACE_RET(chip, retval);
2251
2252 if (chip->asic_code && CHECK_PKG(chip, QFN24))
2253 wait_timeout(20);
2254
2255 return STATUS_SUCCESS;
2256 }
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