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Linux 2.6.35-rc4
[linux-2.6/next.git] / drivers / ata / pata_rdc.c
blob5fbe9b166c69ff75ae002f10d434aef8ac6eca40
1 /*
2 * pata_rdc - Driver for later RDC PATA controllers
3 *
4 * This is actually a driver for hardware meeting
5 * INCITS 370-2004 (1510D): ATA Host Adapter Standards
6 *
7 * Based on ata_piix.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; see the file COPYING. If not, write to
21 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/device.h>
31 #include <linux/gfp.h>
32 #include <scsi/scsi_host.h>
33 #include <linux/libata.h>
34 #include <linux/dmi.h>
35
36 #define DRV_NAME "pata_rdc"
37 #define DRV_VERSION "0.01"
38
39 struct rdc_host_priv {
40 u32 saved_iocfg;
41 };
42
43 /**
44 * rdc_pata_cable_detect - Probe host controller cable detect info
45 * @ap: Port for which cable detect info is desired
46 *
47 * Read 80c cable indicator from ATA PCI device's PCI config
48 * register. This register is normally set by firmware (BIOS).
49 *
50 * LOCKING:
51 * None (inherited from caller).
52 */
53
54 static int rdc_pata_cable_detect(struct ata_port *ap)
55 {
56 struct rdc_host_priv *hpriv = ap->host->private_data;
57 u8 mask;
58
59 /* check BIOS cable detect results */
60 mask = 0x30 << (2 * ap->port_no);
61 if ((hpriv->saved_iocfg & mask) == 0)
62 return ATA_CBL_PATA40;
63 return ATA_CBL_PATA80;
64 }
65
66 /**
67 * rdc_pata_prereset - prereset for PATA host controller
68 * @link: Target link
69 * @deadline: deadline jiffies for the operation
70 *
71 * LOCKING:
72 * None (inherited from caller).
73 */
74 static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
75 {
76 struct ata_port *ap = link->ap;
77 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
78
79 static const struct pci_bits rdc_enable_bits[] = {
80 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
81 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
82 };
83
84 if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no]))
85 return -ENOENT;
86 return ata_sff_prereset(link, deadline);
87 }
88
89 /**
90 * rdc_set_piomode - Initialize host controller PATA PIO timings
91 * @ap: Port whose timings we are configuring
92 * @adev: um
93 *
94 * Set PIO mode for device, in host controller PCI config space.
95 *
96 * LOCKING:
97 * None (inherited from caller).
98 */
99
100 static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
101 {
102 unsigned int pio = adev->pio_mode - XFER_PIO_0;
103 struct pci_dev *dev = to_pci_dev(ap->host->dev);
104 unsigned int is_slave = (adev->devno != 0);
105 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
106 unsigned int slave_port = 0x44;
107 u16 master_data;
108 u8 slave_data;
109 u8 udma_enable;
110 int control = 0;
111
112 static const /* ISP RTC */
113 u8 timings[][2] = { { 0, 0 },
114 { 0, 0 },
115 { 1, 0 },
116 { 2, 1 },
117 { 2, 3 }, };
118
119 if (pio >= 2)
120 control |= 1; /* TIME1 enable */
121 if (ata_pio_need_iordy(adev))
122 control |= 2; /* IE enable */
123
124 if (adev->class == ATA_DEV_ATA)
125 control |= 4; /* PPE enable */
126
127 /* PIO configuration clears DTE unconditionally. It will be
128 * programmed in set_dmamode which is guaranteed to be called
129 * after set_piomode if any DMA mode is available.
130 */
131 pci_read_config_word(dev, master_port, &master_data);
132 if (is_slave) {
133 /* clear TIME1|IE1|PPE1|DTE1 */
134 master_data &= 0xff0f;
135 /* Enable SITRE (separate slave timing register) */
136 master_data |= 0x4000;
137 /* enable PPE1, IE1 and TIME1 as needed */
138 master_data |= (control << 4);
139 pci_read_config_byte(dev, slave_port, &slave_data);
140 slave_data &= (ap->port_no ? 0x0f : 0xf0);
141 /* Load the timing nibble for this slave */
142 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
143 << (ap->port_no ? 4 : 0);
144 } else {
145 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
146 master_data &= 0xccf0;
147 /* Enable PPE, IE and TIME as appropriate */
148 master_data |= control;
149 /* load ISP and RCT */
150 master_data |=
151 (timings[pio][0] << 12) |
152 (timings[pio][1] << 8);
153 }
154 pci_write_config_word(dev, master_port, master_data);
155 if (is_slave)
156 pci_write_config_byte(dev, slave_port, slave_data);
157
158 /* Ensure the UDMA bit is off - it will be turned back on if
159 UDMA is selected */
160
161 pci_read_config_byte(dev, 0x48, &udma_enable);
162 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
163 pci_write_config_byte(dev, 0x48, udma_enable);
164 }
165
166 /**
167 * rdc_set_dmamode - Initialize host controller PATA PIO timings
168 * @ap: Port whose timings we are configuring
169 * @adev: Drive in question
170 *
171 * Set UDMA mode for device, in host controller PCI config space.
172 *
173 * LOCKING:
174 * None (inherited from caller).
175 */
176
177 static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
178 {
179 struct pci_dev *dev = to_pci_dev(ap->host->dev);
180 u8 master_port = ap->port_no ? 0x42 : 0x40;
181 u16 master_data;
182 u8 speed = adev->dma_mode;
183 int devid = adev->devno + 2 * ap->port_no;
184 u8 udma_enable = 0;
185
186 static const /* ISP RTC */
187 u8 timings[][2] = { { 0, 0 },
188 { 0, 0 },
189 { 1, 0 },
190 { 2, 1 },
191 { 2, 3 }, };
192
193 pci_read_config_word(dev, master_port, &master_data);
194 pci_read_config_byte(dev, 0x48, &udma_enable);
195
196 if (speed >= XFER_UDMA_0) {
197 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
198 u16 udma_timing;
199 u16 ideconf;
200 int u_clock, u_speed;
201
202 /*
203 * UDMA is handled by a combination of clock switching and
204 * selection of dividers
205 *
206 * Handy rule: Odd modes are UDMATIMx 01, even are 02
207 * except UDMA0 which is 00
208 */
209 u_speed = min(2 - (udma & 1), udma);
210 if (udma == 5)
211 u_clock = 0x1000; /* 100Mhz */
212 else if (udma > 2)
213 u_clock = 1; /* 66Mhz */
214 else
215 u_clock = 0; /* 33Mhz */
216
217 udma_enable |= (1 << devid);
218
219 /* Load the CT/RP selection */
220 pci_read_config_word(dev, 0x4A, &udma_timing);
221 udma_timing &= ~(3 << (4 * devid));
222 udma_timing |= u_speed << (4 * devid);
223 pci_write_config_word(dev, 0x4A, udma_timing);
224
225 /* Select a 33/66/100Mhz clock */
226 pci_read_config_word(dev, 0x54, &ideconf);
227 ideconf &= ~(0x1001 << devid);
228 ideconf |= u_clock << devid;
229 pci_write_config_word(dev, 0x54, ideconf);
230 } else {
231 /*
232 * MWDMA is driven by the PIO timings. We must also enable
233 * IORDY unconditionally along with TIME1. PPE has already
234 * been set when the PIO timing was set.
235 */
236 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
237 unsigned int control;
238 u8 slave_data;
239 const unsigned int needed_pio[3] = {
240 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
241 };
242 int pio = needed_pio[mwdma] - XFER_PIO_0;
243
244 control = 3; /* IORDY|TIME1 */
245
246 /* If the drive MWDMA is faster than it can do PIO then
247 we must force PIO into PIO0 */
248
249 if (adev->pio_mode < needed_pio[mwdma])
250 /* Enable DMA timing only */
251 control |= 8; /* PIO cycles in PIO0 */
252
253 if (adev->devno) { /* Slave */
254 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
255 master_data |= control << 4;
256 pci_read_config_byte(dev, 0x44, &slave_data);
257 slave_data &= (ap->port_no ? 0x0f : 0xf0);
258 /* Load the matching timing */
259 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
260 pci_write_config_byte(dev, 0x44, slave_data);
261 } else { /* Master */
262 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
263 and master timing bits */
264 master_data |= control;
265 master_data |=
266 (timings[pio][0] << 12) |
267 (timings[pio][1] << 8);
268 }
269
270 udma_enable &= ~(1 << devid);
271 pci_write_config_word(dev, master_port, master_data);
272 }
273 pci_write_config_byte(dev, 0x48, udma_enable);
274 }
275
276 static struct ata_port_operations rdc_pata_ops = {
277 .inherits = &ata_bmdma32_port_ops,
278 .cable_detect = rdc_pata_cable_detect,
279 .set_piomode = rdc_set_piomode,
280 .set_dmamode = rdc_set_dmamode,
281 .prereset = rdc_pata_prereset,
282 };
283
284 static struct ata_port_info rdc_port_info = {
285
286 .flags = ATA_FLAG_SLAVE_POSS,
287 .pio_mask = ATA_PIO4,
288 .mwdma_mask = ATA_MWDMA12_ONLY,
289 .udma_mask = ATA_UDMA5,
290 .port_ops = &rdc_pata_ops,
291 };
292
293 static struct scsi_host_template rdc_sht = {
294 ATA_BMDMA_SHT(DRV_NAME),
295 };
296
297 /**
298 * rdc_init_one - Register PIIX ATA PCI device with kernel services
299 * @pdev: PCI device to register
300 * @ent: Entry in rdc_pci_tbl matching with @pdev
301 *
302 * Called from kernel PCI layer. We probe for combined mode (sigh),
303 * and then hand over control to libata, for it to do the rest.
304 *
305 * LOCKING:
306 * Inherited from PCI layer (may sleep).
307 *
308 * RETURNS:
309 * Zero on success, or -ERRNO value.
310 */
311
312 static int __devinit rdc_init_one(struct pci_dev *pdev,
313 const struct pci_device_id *ent)
314 {
315 static int printed_version;
316 struct device *dev = &pdev->dev;
317 struct ata_port_info port_info[2];
318 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
319 unsigned long port_flags;
320 struct ata_host *host;
321 struct rdc_host_priv *hpriv;
322 int rc;
323
324 if (!printed_version++)
325 dev_printk(KERN_DEBUG, &pdev->dev,
326 "version " DRV_VERSION "\n");
327
328 port_info[0] = rdc_port_info;
329 port_info[1] = rdc_port_info;
330
331 port_flags = port_info[0].flags;
332
333 /* enable device and prepare host */
334 rc = pcim_enable_device(pdev);
335 if (rc)
336 return rc;
337
338 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
339 if (!hpriv)
340 return -ENOMEM;
341
342 /* Save IOCFG, this will be used for cable detection, quirk
343 * detection and restoration on detach.
344 */
345 pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg);
346
347 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
348 if (rc)
349 return rc;
350 host->private_data = hpriv;
351
352 pci_intx(pdev, 1);
353
354 host->flags |= ATA_HOST_PARALLEL_SCAN;
355
356 pci_set_master(pdev);
357 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht);
358 }
359
360 static void rdc_remove_one(struct pci_dev *pdev)
361 {
362 struct ata_host *host = dev_get_drvdata(&pdev->dev);
363 struct rdc_host_priv *hpriv = host->private_data;
364
365 pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg);
366
367 ata_pci_remove_one(pdev);
368 }
369
370 static const struct pci_device_id rdc_pci_tbl[] = {
371 { PCI_DEVICE(0x17F3, 0x1011), },
372 { PCI_DEVICE(0x17F3, 0x1012), },
373 { } /* terminate list */
374 };
375
376 static struct pci_driver rdc_pci_driver = {
377 .name = DRV_NAME,
378 .id_table = rdc_pci_tbl,
379 .probe = rdc_init_one,
380 .remove = rdc_remove_one,
381 };
382
383
384 static int __init rdc_init(void)
385 {
386 return pci_register_driver(&rdc_pci_driver);
387 }
388
389 static void __exit rdc_exit(void)
390 {
391 pci_unregister_driver(&rdc_pci_driver);
392 }
393
394 module_init(rdc_init);
395 module_exit(rdc_exit);
396
397 MODULE_AUTHOR("Alan Cox (based on ata_piix)");
398 MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers");
399 MODULE_LICENSE("GPL");
400 MODULE_DEVICE_TABLE(pci, rdc_pci_tbl);
401 MODULE_VERSION(DRV_VERSION);
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