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staging:iio:triggers reorder module put and device put to ensure that the ops are...
[linux-2.6/next.git] / drivers / i2c / busses / i2c-tegra.c
blob2440b741197851247ea267cd8464467c925a4c72
1 /*
2 * drivers/i2c/busses/i2c-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
24 #include <linux/io.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/i2c-tegra.h>
29 #include <linux/of_i2c.h>
30
31 #include <asm/unaligned.h>
32
33 #include <mach/clk.h>
34
35 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
36 #define BYTES_PER_FIFO_WORD 4
37
38 #define I2C_CNFG 0x000
39 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
40 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
41 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
42 #define I2C_STATUS 0x01C
43 #define I2C_SL_CNFG 0x020
44 #define I2C_SL_CNFG_NACK (1<<1)
45 #define I2C_SL_CNFG_NEWSL (1<<2)
46 #define I2C_SL_ADDR1 0x02c
47 #define I2C_SL_ADDR2 0x030
48 #define I2C_TX_FIFO 0x050
49 #define I2C_RX_FIFO 0x054
50 #define I2C_PACKET_TRANSFER_STATUS 0x058
51 #define I2C_FIFO_CONTROL 0x05c
52 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
53 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
54 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
55 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
56 #define I2C_FIFO_STATUS 0x060
57 #define I2C_FIFO_STATUS_TX_MASK 0xF0
58 #define I2C_FIFO_STATUS_TX_SHIFT 4
59 #define I2C_FIFO_STATUS_RX_MASK 0x0F
60 #define I2C_FIFO_STATUS_RX_SHIFT 0
61 #define I2C_INT_MASK 0x064
62 #define I2C_INT_STATUS 0x068
63 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
64 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
65 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
66 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
67 #define I2C_INT_NO_ACK (1<<3)
68 #define I2C_INT_ARBITRATION_LOST (1<<2)
69 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
70 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
71 #define I2C_CLK_DIVISOR 0x06c
72
73 #define DVC_CTRL_REG1 0x000
74 #define DVC_CTRL_REG1_INTR_EN (1<<10)
75 #define DVC_CTRL_REG2 0x004
76 #define DVC_CTRL_REG3 0x008
77 #define DVC_CTRL_REG3_SW_PROG (1<<26)
78 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
79 #define DVC_STATUS 0x00c
80 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
81
82 #define I2C_ERR_NONE 0x00
83 #define I2C_ERR_NO_ACK 0x01
84 #define I2C_ERR_ARBITRATION_LOST 0x02
85 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
86
87 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
88 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
89 #define PACKET_HEADER0_CONT_ID_SHIFT 12
90 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
91
92 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
93 #define I2C_HEADER_CONT_ON_NAK (1<<21)
94 #define I2C_HEADER_SEND_START_BYTE (1<<20)
95 #define I2C_HEADER_READ (1<<19)
96 #define I2C_HEADER_10BIT_ADDR (1<<18)
97 #define I2C_HEADER_IE_ENABLE (1<<17)
98 #define I2C_HEADER_REPEAT_START (1<<16)
99 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
100 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
101
102 /**
103 * struct tegra_i2c_dev - per device i2c context
104 * @dev: device reference for power management
105 * @adapter: core i2c layer adapter information
106 * @clk: clock reference for i2c controller
107 * @i2c_clk: clock reference for i2c bus
108 * @iomem: memory resource for registers
109 * @base: ioremapped registers cookie
110 * @cont_id: i2c controller id, used for for packet header
111 * @irq: irq number of transfer complete interrupt
112 * @is_dvc: identifies the DVC i2c controller, has a different register layout
113 * @msg_complete: transfer completion notifier
114 * @msg_err: error code for completed message
115 * @msg_buf: pointer to current message data
116 * @msg_buf_remaining: size of unsent data in the message buffer
117 * @msg_read: identifies read transfers
118 * @bus_clk_rate: current i2c bus clock rate
119 * @is_suspended: prevents i2c controller accesses after suspend is called
120 */
121 struct tegra_i2c_dev {
122 struct device *dev;
123 struct i2c_adapter adapter;
124 struct clk *clk;
125 struct clk *i2c_clk;
126 struct resource *iomem;
127 void __iomem *base;
128 int cont_id;
129 int irq;
130 bool irq_disabled;
131 int is_dvc;
132 struct completion msg_complete;
133 int msg_err;
134 u8 *msg_buf;
135 size_t msg_buf_remaining;
136 int msg_read;
137 unsigned long bus_clk_rate;
138 bool is_suspended;
139 };
140
141 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
142 {
143 writel(val, i2c_dev->base + reg);
144 }
145
146 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
147 {
148 return readl(i2c_dev->base + reg);
149 }
150
151 /*
152 * i2c_writel and i2c_readl will offset the register if necessary to talk
153 * to the I2C block inside the DVC block
154 */
155 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
156 unsigned long reg)
157 {
158 if (i2c_dev->is_dvc)
159 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
160 return reg;
161 }
162
163 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
164 unsigned long reg)
165 {
166 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
167 }
168
169 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
170 {
171 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
172 }
173
174 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
175 unsigned long reg, int len)
176 {
177 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
178 }
179
180 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
181 unsigned long reg, int len)
182 {
183 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
184 }
185
186 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
187 {
188 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
189 int_mask &= ~mask;
190 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
191 }
192
193 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
194 {
195 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
196 int_mask |= mask;
197 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
198 }
199
200 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
201 {
202 unsigned long timeout = jiffies + HZ;
203 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
204 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
205 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
206
207 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
208 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
209 if (time_after(jiffies, timeout)) {
210 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
211 return -ETIMEDOUT;
212 }
213 msleep(1);
214 }
215 return 0;
216 }
217
218 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
219 {
220 u32 val;
221 int rx_fifo_avail;
222 u8 *buf = i2c_dev->msg_buf;
223 size_t buf_remaining = i2c_dev->msg_buf_remaining;
224 int words_to_transfer;
225
226 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
227 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
228 I2C_FIFO_STATUS_RX_SHIFT;
229
230 /* Rounds down to not include partial word at the end of buf */
231 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
232 if (words_to_transfer > rx_fifo_avail)
233 words_to_transfer = rx_fifo_avail;
234
235 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
236
237 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
238 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
239 rx_fifo_avail -= words_to_transfer;
240
241 /*
242 * If there is a partial word at the end of buf, handle it manually to
243 * prevent overwriting past the end of buf
244 */
245 if (rx_fifo_avail > 0 && buf_remaining > 0) {
246 BUG_ON(buf_remaining > 3);
247 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
248 memcpy(buf, &val, buf_remaining);
249 buf_remaining = 0;
250 rx_fifo_avail--;
251 }
252
253 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
254 i2c_dev->msg_buf_remaining = buf_remaining;
255 i2c_dev->msg_buf = buf;
256 return 0;
257 }
258
259 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
260 {
261 u32 val;
262 int tx_fifo_avail;
263 u8 *buf = i2c_dev->msg_buf;
264 size_t buf_remaining = i2c_dev->msg_buf_remaining;
265 int words_to_transfer;
266
267 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
268 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
269 I2C_FIFO_STATUS_TX_SHIFT;
270
271 /* Rounds down to not include partial word at the end of buf */
272 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
273 if (words_to_transfer > tx_fifo_avail)
274 words_to_transfer = tx_fifo_avail;
275
276 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
277
278 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
279 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
280 tx_fifo_avail -= words_to_transfer;
281
282 /*
283 * If there is a partial word at the end of buf, handle it manually to
284 * prevent reading past the end of buf, which could cross a page
285 * boundary and fault.
286 */
287 if (tx_fifo_avail > 0 && buf_remaining > 0) {
288 BUG_ON(buf_remaining > 3);
289 memcpy(&val, buf, buf_remaining);
290 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
291 buf_remaining = 0;
292 tx_fifo_avail--;
293 }
294
295 BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
296 i2c_dev->msg_buf_remaining = buf_remaining;
297 i2c_dev->msg_buf = buf;
298 return 0;
299 }
300
301 /*
302 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
303 * block. This block is identical to the rest of the I2C blocks, except that
304 * it only supports master mode, it has registers moved around, and it needs
305 * some extra init to get it into I2C mode. The register moves are handled
306 * by i2c_readl and i2c_writel
307 */
308 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
309 {
310 u32 val = 0;
311 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
312 val |= DVC_CTRL_REG3_SW_PROG;
313 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
314 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
315
316 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
317 val |= DVC_CTRL_REG1_INTR_EN;
318 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
319 }
320
321 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
322 {
323 u32 val;
324 int err = 0;
325
326 clk_enable(i2c_dev->clk);
327
328 tegra_periph_reset_assert(i2c_dev->clk);
329 udelay(2);
330 tegra_periph_reset_deassert(i2c_dev->clk);
331
332 if (i2c_dev->is_dvc)
333 tegra_dvc_init(i2c_dev);
334
335 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
336 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
337 i2c_writel(i2c_dev, val, I2C_CNFG);
338 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
339 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
340
341 if (!i2c_dev->is_dvc) {
342 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
343 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
344 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
345 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
346 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
347
348 }
349
350 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
351 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
352 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
353
354 if (tegra_i2c_flush_fifos(i2c_dev))
355 err = -ETIMEDOUT;
356
357 clk_disable(i2c_dev->clk);
358
359 if (i2c_dev->irq_disabled) {
360 i2c_dev->irq_disabled = 0;
361 enable_irq(i2c_dev->irq);
362 }
363
364 return err;
365 }
366
367 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
368 {
369 u32 status;
370 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
371 struct tegra_i2c_dev *i2c_dev = dev_id;
372
373 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
374
375 if (status == 0) {
376 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
377 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
378 i2c_readl(i2c_dev, I2C_STATUS),
379 i2c_readl(i2c_dev, I2C_CNFG));
380 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
381
382 if (!i2c_dev->irq_disabled) {
383 disable_irq_nosync(i2c_dev->irq);
384 i2c_dev->irq_disabled = 1;
385 }
386
387 complete(&i2c_dev->msg_complete);
388 goto err;
389 }
390
391 if (unlikely(status & status_err)) {
392 if (status & I2C_INT_NO_ACK)
393 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
394 if (status & I2C_INT_ARBITRATION_LOST)
395 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
396 complete(&i2c_dev->msg_complete);
397 goto err;
398 }
399
400 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
401 if (i2c_dev->msg_buf_remaining)
402 tegra_i2c_empty_rx_fifo(i2c_dev);
403 else
404 BUG();
405 }
406
407 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
408 if (i2c_dev->msg_buf_remaining)
409 tegra_i2c_fill_tx_fifo(i2c_dev);
410 else
411 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
412 }
413
414 if ((status & I2C_INT_PACKET_XFER_COMPLETE) &&
415 !i2c_dev->msg_buf_remaining)
416 complete(&i2c_dev->msg_complete);
417
418 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
419 if (i2c_dev->is_dvc)
420 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
421 return IRQ_HANDLED;
422 err:
423 /* An error occurred, mask all interrupts */
424 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
425 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
426 I2C_INT_RX_FIFO_DATA_REQ);
427 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
428 if (i2c_dev->is_dvc)
429 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
430 return IRQ_HANDLED;
431 }
432
433 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
434 struct i2c_msg *msg, int stop)
435 {
436 u32 packet_header;
437 u32 int_mask;
438 int ret;
439
440 tegra_i2c_flush_fifos(i2c_dev);
441 i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
442
443 if (msg->len == 0)
444 return -EINVAL;
445
446 i2c_dev->msg_buf = msg->buf;
447 i2c_dev->msg_buf_remaining = msg->len;
448 i2c_dev->msg_err = I2C_ERR_NONE;
449 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
450 INIT_COMPLETION(i2c_dev->msg_complete);
451
452 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
453 PACKET_HEADER0_PROTOCOL_I2C |
454 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
455 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
456 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
457
458 packet_header = msg->len - 1;
459 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
460
461 packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
462 packet_header |= I2C_HEADER_IE_ENABLE;
463 if (!stop)
464 packet_header |= I2C_HEADER_REPEAT_START;
465 if (msg->flags & I2C_M_TEN)
466 packet_header |= I2C_HEADER_10BIT_ADDR;
467 if (msg->flags & I2C_M_IGNORE_NAK)
468 packet_header |= I2C_HEADER_CONT_ON_NAK;
469 if (msg->flags & I2C_M_RD)
470 packet_header |= I2C_HEADER_READ;
471 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
472
473 if (!(msg->flags & I2C_M_RD))
474 tegra_i2c_fill_tx_fifo(i2c_dev);
475
476 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
477 if (msg->flags & I2C_M_RD)
478 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
479 else if (i2c_dev->msg_buf_remaining)
480 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
481 tegra_i2c_unmask_irq(i2c_dev, int_mask);
482 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
483 i2c_readl(i2c_dev, I2C_INT_MASK));
484
485 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
486 tegra_i2c_mask_irq(i2c_dev, int_mask);
487
488 if (WARN_ON(ret == 0)) {
489 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
490
491 tegra_i2c_init(i2c_dev);
492 return -ETIMEDOUT;
493 }
494
495 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
496 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
497
498 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
499 return 0;
500
501 tegra_i2c_init(i2c_dev);
502 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
503 if (msg->flags & I2C_M_IGNORE_NAK)
504 return 0;
505 return -EREMOTEIO;
506 }
507
508 return -EIO;
509 }
510
511 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
512 int num)
513 {
514 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
515 int i;
516 int ret = 0;
517
518 if (i2c_dev->is_suspended)
519 return -EBUSY;
520
521 clk_enable(i2c_dev->clk);
522 for (i = 0; i < num; i++) {
523 int stop = (i == (num - 1)) ? 1 : 0;
524 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
525 if (ret)
526 break;
527 }
528 clk_disable(i2c_dev->clk);
529 return ret ?: i;
530 }
531
532 static u32 tegra_i2c_func(struct i2c_adapter *adap)
533 {
534 return I2C_FUNC_I2C;
535 }
536
537 static const struct i2c_algorithm tegra_i2c_algo = {
538 .master_xfer = tegra_i2c_xfer,
539 .functionality = tegra_i2c_func,
540 };
541
542 static int tegra_i2c_probe(struct platform_device *pdev)
543 {
544 struct tegra_i2c_dev *i2c_dev;
545 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
546 struct resource *res;
547 struct resource *iomem;
548 struct clk *clk;
549 struct clk *i2c_clk;
550 const unsigned int *prop;
551 void *base;
552 int irq;
553 int ret = 0;
554
555 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
556 if (!res) {
557 dev_err(&pdev->dev, "no mem resource\n");
558 return -EINVAL;
559 }
560 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
561 if (!iomem) {
562 dev_err(&pdev->dev, "I2C region already claimed\n");
563 return -EBUSY;
564 }
565
566 base = ioremap(iomem->start, resource_size(iomem));
567 if (!base) {
568 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
569 return -ENOMEM;
570 }
571
572 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
573 if (!res) {
574 dev_err(&pdev->dev, "no irq resource\n");
575 ret = -EINVAL;
576 goto err_iounmap;
577 }
578 irq = res->start;
579
580 clk = clk_get(&pdev->dev, NULL);
581 if (IS_ERR(clk)) {
582 dev_err(&pdev->dev, "missing controller clock");
583 ret = PTR_ERR(clk);
584 goto err_release_region;
585 }
586
587 i2c_clk = clk_get(&pdev->dev, "i2c");
588 if (IS_ERR(i2c_clk)) {
589 dev_err(&pdev->dev, "missing bus clock");
590 ret = PTR_ERR(i2c_clk);
591 goto err_clk_put;
592 }
593
594 i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
595 if (!i2c_dev) {
596 ret = -ENOMEM;
597 goto err_i2c_clk_put;
598 }
599
600 i2c_dev->base = base;
601 i2c_dev->clk = clk;
602 i2c_dev->i2c_clk = i2c_clk;
603 i2c_dev->iomem = iomem;
604 i2c_dev->adapter.algo = &tegra_i2c_algo;
605 i2c_dev->irq = irq;
606 i2c_dev->cont_id = pdev->id;
607 i2c_dev->dev = &pdev->dev;
608
609 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
610 if (pdata) {
611 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
612
613 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
614 prop = of_get_property(i2c_dev->dev->of_node,
615 "clock-frequency", NULL);
616 if (prop)
617 i2c_dev->bus_clk_rate = be32_to_cpup(prop);
618 }
619
620 if (pdev->id == 3)
621 i2c_dev->is_dvc = 1;
622 init_completion(&i2c_dev->msg_complete);
623
624 platform_set_drvdata(pdev, i2c_dev);
625
626 ret = tegra_i2c_init(i2c_dev);
627 if (ret) {
628 dev_err(&pdev->dev, "Failed to initialize i2c controller");
629 goto err_free;
630 }
631
632 ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
633 if (ret) {
634 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
635 goto err_free;
636 }
637
638 clk_enable(i2c_dev->i2c_clk);
639
640 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
641 i2c_dev->adapter.owner = THIS_MODULE;
642 i2c_dev->adapter.class = I2C_CLASS_HWMON;
643 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
644 sizeof(i2c_dev->adapter.name));
645 i2c_dev->adapter.algo = &tegra_i2c_algo;
646 i2c_dev->adapter.dev.parent = &pdev->dev;
647 i2c_dev->adapter.nr = pdev->id;
648 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
649
650 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
651 if (ret) {
652 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
653 goto err_free_irq;
654 }
655
656 of_i2c_register_devices(&i2c_dev->adapter);
657
658 return 0;
659 err_free_irq:
660 free_irq(i2c_dev->irq, i2c_dev);
661 err_free:
662 kfree(i2c_dev);
663 err_i2c_clk_put:
664 clk_put(i2c_clk);
665 err_clk_put:
666 clk_put(clk);
667 err_release_region:
668 release_mem_region(iomem->start, resource_size(iomem));
669 err_iounmap:
670 iounmap(base);
671 return ret;
672 }
673
674 static int tegra_i2c_remove(struct platform_device *pdev)
675 {
676 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
677 i2c_del_adapter(&i2c_dev->adapter);
678 free_irq(i2c_dev->irq, i2c_dev);
679 clk_put(i2c_dev->i2c_clk);
680 clk_put(i2c_dev->clk);
681 release_mem_region(i2c_dev->iomem->start,
682 resource_size(i2c_dev->iomem));
683 iounmap(i2c_dev->base);
684 kfree(i2c_dev);
685 return 0;
686 }
687
688 #ifdef CONFIG_PM
689 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
690 {
691 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
692
693 i2c_lock_adapter(&i2c_dev->adapter);
694 i2c_dev->is_suspended = true;
695 i2c_unlock_adapter(&i2c_dev->adapter);
696
697 return 0;
698 }
699
700 static int tegra_i2c_resume(struct platform_device *pdev)
701 {
702 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
703 int ret;
704
705 i2c_lock_adapter(&i2c_dev->adapter);
706
707 ret = tegra_i2c_init(i2c_dev);
708
709 if (ret) {
710 i2c_unlock_adapter(&i2c_dev->adapter);
711 return ret;
712 }
713
714 i2c_dev->is_suspended = false;
715
716 i2c_unlock_adapter(&i2c_dev->adapter);
717
718 return 0;
719 }
720 #endif
721
722 static struct platform_driver tegra_i2c_driver = {
723 .probe = tegra_i2c_probe,
724 .remove = tegra_i2c_remove,
725 #ifdef CONFIG_PM
726 .suspend = tegra_i2c_suspend,
727 .resume = tegra_i2c_resume,
728 #endif
729 .driver = {
730 .name = "tegra-i2c",
731 .owner = THIS_MODULE,
732 },
733 };
734
735 static int __init tegra_i2c_init_driver(void)
736 {
737 return platform_driver_register(&tegra_i2c_driver);
738 }
739
740 static void __exit tegra_i2c_exit_driver(void)
741 {
742 platform_driver_unregister(&tegra_i2c_driver);
743 }
744
745 subsys_initcall(tegra_i2c_init_driver);
746 module_exit(tegra_i2c_exit_driver);
747
748 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
749 MODULE_AUTHOR("Colin Cross");
750 MODULE_LICENSE("GPL v2");
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