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powerpc/pmac: Add missing unlocks in error path
[linux-2.6/next.git] / sound / soc / codecs / wm8350.c
blob2e0772f9c456fe63d6cb8c5ae0f17bffbb6a1cf4
1 /*
2 * wm8350.c -- WM8350 ALSA SoC audio driver
3 *
4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/platform_device.h>
20 #include <linux/mfd/wm8350/audio.h>
21 #include <linux/mfd/wm8350/core.h>
22 #include <linux/regulator/consumer.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include "wm8350.h"
32
33 #define WM8350_OUTn_0dB 0x39
34
35 #define WM8350_RAMP_NONE 0
36 #define WM8350_RAMP_UP 1
37 #define WM8350_RAMP_DOWN 2
38
39 /* We only include the analogue supplies here; the digital supplies
40 * need to be available well before this driver can be probed.
41 */
42 static const char *supply_names[] = {
43 "AVDD",
44 "HPVDD",
45 };
46
47 struct wm8350_output {
48 u16 active;
49 u16 left_vol;
50 u16 right_vol;
51 u16 ramp;
52 u16 mute;
53 };
54
55 struct wm8350_jack_data {
56 struct snd_soc_jack *jack;
57 int report;
58 };
59
60 struct wm8350_data {
61 struct snd_soc_codec codec;
62 struct wm8350_output out1;
63 struct wm8350_output out2;
64 struct wm8350_jack_data hpl;
65 struct wm8350_jack_data hpr;
66 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
67 int fll_freq_out;
68 int fll_freq_in;
69 };
70
71 static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec,
72 unsigned int reg)
73 {
74 struct wm8350 *wm8350 = codec->control_data;
75 return wm8350->reg_cache[reg];
76 }
77
78 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
79 unsigned int reg)
80 {
81 struct wm8350 *wm8350 = codec->control_data;
82 return wm8350_reg_read(wm8350, reg);
83 }
84
85 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg,
86 unsigned int value)
87 {
88 struct wm8350 *wm8350 = codec->control_data;
89 return wm8350_reg_write(wm8350, reg, value);
90 }
91
92 /*
93 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
94 */
95 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
96 {
97 struct wm8350_data *wm8350_data = codec->private_data;
98 struct wm8350_output *out1 = &wm8350_data->out1;
99 struct wm8350 *wm8350 = codec->control_data;
100 int left_complete = 0, right_complete = 0;
101 u16 reg, val;
102
103 /* left channel */
104 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
105 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
106
107 if (out1->ramp == WM8350_RAMP_UP) {
108 /* ramp step up */
109 if (val < out1->left_vol) {
110 val++;
111 reg &= ~WM8350_OUT1L_VOL_MASK;
112 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
113 reg | (val << WM8350_OUT1L_VOL_SHIFT));
114 } else
115 left_complete = 1;
116 } else if (out1->ramp == WM8350_RAMP_DOWN) {
117 /* ramp step down */
118 if (val > 0) {
119 val--;
120 reg &= ~WM8350_OUT1L_VOL_MASK;
121 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
122 reg | (val << WM8350_OUT1L_VOL_SHIFT));
123 } else
124 left_complete = 1;
125 } else
126 return 1;
127
128 /* right channel */
129 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
130 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
131 if (out1->ramp == WM8350_RAMP_UP) {
132 /* ramp step up */
133 if (val < out1->right_vol) {
134 val++;
135 reg &= ~WM8350_OUT1R_VOL_MASK;
136 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
137 reg | (val << WM8350_OUT1R_VOL_SHIFT));
138 } else
139 right_complete = 1;
140 } else if (out1->ramp == WM8350_RAMP_DOWN) {
141 /* ramp step down */
142 if (val > 0) {
143 val--;
144 reg &= ~WM8350_OUT1R_VOL_MASK;
145 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
146 reg | (val << WM8350_OUT1R_VOL_SHIFT));
147 } else
148 right_complete = 1;
149 }
150
151 /* only hit the update bit if either volume has changed this step */
152 if (!left_complete || !right_complete)
153 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
154
155 return left_complete & right_complete;
156 }
157
158 /*
159 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
160 */
161 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
162 {
163 struct wm8350_data *wm8350_data = codec->private_data;
164 struct wm8350_output *out2 = &wm8350_data->out2;
165 struct wm8350 *wm8350 = codec->control_data;
166 int left_complete = 0, right_complete = 0;
167 u16 reg, val;
168
169 /* left channel */
170 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
171 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
172 if (out2->ramp == WM8350_RAMP_UP) {
173 /* ramp step up */
174 if (val < out2->left_vol) {
175 val++;
176 reg &= ~WM8350_OUT2L_VOL_MASK;
177 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
178 reg | (val << WM8350_OUT1L_VOL_SHIFT));
179 } else
180 left_complete = 1;
181 } else if (out2->ramp == WM8350_RAMP_DOWN) {
182 /* ramp step down */
183 if (val > 0) {
184 val--;
185 reg &= ~WM8350_OUT2L_VOL_MASK;
186 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
187 reg | (val << WM8350_OUT1L_VOL_SHIFT));
188 } else
189 left_complete = 1;
190 } else
191 return 1;
192
193 /* right channel */
194 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
195 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
196 if (out2->ramp == WM8350_RAMP_UP) {
197 /* ramp step up */
198 if (val < out2->right_vol) {
199 val++;
200 reg &= ~WM8350_OUT2R_VOL_MASK;
201 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
202 reg | (val << WM8350_OUT1R_VOL_SHIFT));
203 } else
204 right_complete = 1;
205 } else if (out2->ramp == WM8350_RAMP_DOWN) {
206 /* ramp step down */
207 if (val > 0) {
208 val--;
209 reg &= ~WM8350_OUT2R_VOL_MASK;
210 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
211 reg | (val << WM8350_OUT1R_VOL_SHIFT));
212 } else
213 right_complete = 1;
214 }
215
216 /* only hit the update bit if either volume has changed this step */
217 if (!left_complete || !right_complete)
218 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
219
220 return left_complete & right_complete;
221 }
222
223 /*
224 * This work ramps both output PGAs at stream start/stop time to
225 * minimise pop associated with DAPM power switching.
226 * It's best to enable Zero Cross when ramping occurs to minimise any
227 * zipper noises.
228 */
229 static void wm8350_pga_work(struct work_struct *work)
230 {
231 struct snd_soc_codec *codec =
232 container_of(work, struct snd_soc_codec, delayed_work.work);
233 struct wm8350_data *wm8350_data = codec->private_data;
234 struct wm8350_output *out1 = &wm8350_data->out1,
235 *out2 = &wm8350_data->out2;
236 int i, out1_complete, out2_complete;
237
238 /* do we need to ramp at all ? */
239 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
240 return;
241
242 /* PGA volumes have 6 bits of resolution to ramp */
243 for (i = 0; i <= 63; i++) {
244 out1_complete = 1, out2_complete = 1;
245 if (out1->ramp != WM8350_RAMP_NONE)
246 out1_complete = wm8350_out1_ramp_step(codec);
247 if (out2->ramp != WM8350_RAMP_NONE)
248 out2_complete = wm8350_out2_ramp_step(codec);
249
250 /* ramp finished ? */
251 if (out1_complete && out2_complete)
252 break;
253
254 /* we need to delay longer on the up ramp */
255 if (out1->ramp == WM8350_RAMP_UP ||
256 out2->ramp == WM8350_RAMP_UP) {
257 /* delay is longer over 0dB as increases are larger */
258 if (i >= WM8350_OUTn_0dB)
259 schedule_timeout_interruptible(msecs_to_jiffies
260 (2));
261 else
262 schedule_timeout_interruptible(msecs_to_jiffies
263 (1));
264 } else
265 udelay(50); /* doesn't matter if we delay longer */
266 }
267
268 out1->ramp = WM8350_RAMP_NONE;
269 out2->ramp = WM8350_RAMP_NONE;
270 }
271
272 /*
273 * WM8350 Controls
274 */
275
276 static int pga_event(struct snd_soc_dapm_widget *w,
277 struct snd_kcontrol *kcontrol, int event)
278 {
279 struct snd_soc_codec *codec = w->codec;
280 struct wm8350_data *wm8350_data = codec->private_data;
281 struct wm8350_output *out;
282
283 switch (w->shift) {
284 case 0:
285 case 1:
286 out = &wm8350_data->out1;
287 break;
288 case 2:
289 case 3:
290 out = &wm8350_data->out2;
291 break;
292
293 default:
294 BUG();
295 return -1;
296 }
297
298 switch (event) {
299 case SND_SOC_DAPM_POST_PMU:
300 out->ramp = WM8350_RAMP_UP;
301 out->active = 1;
302
303 if (!delayed_work_pending(&codec->delayed_work))
304 schedule_delayed_work(&codec->delayed_work,
305 msecs_to_jiffies(1));
306 break;
307
308 case SND_SOC_DAPM_PRE_PMD:
309 out->ramp = WM8350_RAMP_DOWN;
310 out->active = 0;
311
312 if (!delayed_work_pending(&codec->delayed_work))
313 schedule_delayed_work(&codec->delayed_work,
314 msecs_to_jiffies(1));
315 break;
316 }
317
318 return 0;
319 }
320
321 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
322 struct snd_ctl_elem_value *ucontrol)
323 {
324 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
325 struct wm8350_data *wm8350_priv = codec->private_data;
326 struct wm8350_output *out = NULL;
327 struct soc_mixer_control *mc =
328 (struct soc_mixer_control *)kcontrol->private_value;
329 int ret;
330 unsigned int reg = mc->reg;
331 u16 val;
332
333 /* For OUT1 and OUT2 we shadow the values and only actually write
334 * them out when active in order to ensure the amplifier comes on
335 * as quietly as possible. */
336 switch (reg) {
337 case WM8350_LOUT1_VOLUME:
338 out = &wm8350_priv->out1;
339 break;
340 case WM8350_LOUT2_VOLUME:
341 out = &wm8350_priv->out2;
342 break;
343 default:
344 break;
345 }
346
347 if (out) {
348 out->left_vol = ucontrol->value.integer.value[0];
349 out->right_vol = ucontrol->value.integer.value[1];
350 if (!out->active)
351 return 1;
352 }
353
354 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
355 if (ret < 0)
356 return ret;
357
358 /* now hit the volume update bits (always bit 8) */
359 val = wm8350_codec_read(codec, reg);
360 wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU);
361 return 1;
362 }
363
364 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
365 struct snd_ctl_elem_value *ucontrol)
366 {
367 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
368 struct wm8350_data *wm8350_priv = codec->private_data;
369 struct wm8350_output *out1 = &wm8350_priv->out1;
370 struct wm8350_output *out2 = &wm8350_priv->out2;
371 struct soc_mixer_control *mc =
372 (struct soc_mixer_control *)kcontrol->private_value;
373 unsigned int reg = mc->reg;
374
375 /* If these are cached registers use the cache */
376 switch (reg) {
377 case WM8350_LOUT1_VOLUME:
378 ucontrol->value.integer.value[0] = out1->left_vol;
379 ucontrol->value.integer.value[1] = out1->right_vol;
380 return 0;
381
382 case WM8350_LOUT2_VOLUME:
383 ucontrol->value.integer.value[0] = out2->left_vol;
384 ucontrol->value.integer.value[1] = out2->right_vol;
385 return 0;
386
387 default:
388 break;
389 }
390
391 return snd_soc_get_volsw_2r(kcontrol, ucontrol);
392 }
393
394 /* double control with volume update */
395 #define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
396 xinvert, tlv_array) \
397 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
398 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
399 SNDRV_CTL_ELEM_ACCESS_READWRITE | \
400 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
401 .tlv.p = (tlv_array), \
402 .info = snd_soc_info_volsw_2r, \
403 .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \
404 .private_value = (unsigned long)&(struct soc_mixer_control) \
405 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
406 .rshift = xshift, .max = xmax, .invert = xinvert}, }
407
408 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
409 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
410 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
411 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
412 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
413 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
414 static const char *wm8350_lr[] = { "Left", "Right" };
415
416 static const struct soc_enum wm8350_enum[] = {
417 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
418 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
419 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
420 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
421 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
422 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
423 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
424 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
425 };
426
427 static DECLARE_TLV_DB_LINEAR(pre_amp_tlv, -1200, 3525);
428 static DECLARE_TLV_DB_LINEAR(out_pga_tlv, -5700, 600);
429 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
430 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
431 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
432
433 static const unsigned int capture_sd_tlv[] = {
434 TLV_DB_RANGE_HEAD(2),
435 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
436 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
437 };
438
439 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
440 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
441 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
442 SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume",
443 WM8350_DAC_DIGITAL_VOLUME_L,
444 WM8350_DAC_DIGITAL_VOLUME_R,
445 0, 255, 0, dac_pcm_tlv),
446 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
447 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
448 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
449 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
450 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
451 SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume",
452 WM8350_ADC_DIGITAL_VOLUME_L,
453 WM8350_ADC_DIGITAL_VOLUME_R,
454 0, 255, 0, adc_pcm_tlv),
455 SOC_DOUBLE_TLV("Capture Sidetone Volume",
456 WM8350_ADC_DIVIDER,
457 8, 4, 15, 1, capture_sd_tlv),
458 SOC_WM8350_DOUBLE_R_TLV("Capture Volume",
459 WM8350_LEFT_INPUT_VOLUME,
460 WM8350_RIGHT_INPUT_VOLUME,
461 2, 63, 0, pre_amp_tlv),
462 SOC_DOUBLE_R("Capture ZC Switch",
463 WM8350_LEFT_INPUT_VOLUME,
464 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
465 SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
466 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
467 SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
468 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
469 5, 7, 0, out_mix_tlv),
470 SOC_SINGLE_TLV("Left Input Bypass Volume",
471 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
472 9, 7, 0, out_mix_tlv),
473 SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
474 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
475 1, 7, 0, out_mix_tlv),
476 SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
477 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
478 5, 7, 0, out_mix_tlv),
479 SOC_SINGLE_TLV("Right Input Bypass Volume",
480 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
481 13, 7, 0, out_mix_tlv),
482 SOC_SINGLE("Left Input Mixer +20dB Switch",
483 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
484 SOC_SINGLE("Right Input Mixer +20dB Switch",
485 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
486 SOC_SINGLE_TLV("Out4 Capture Volume",
487 WM8350_INPUT_MIXER_VOLUME,
488 1, 7, 0, out_mix_tlv),
489 SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume",
490 WM8350_LOUT1_VOLUME,
491 WM8350_ROUT1_VOLUME,
492 2, 63, 0, out_pga_tlv),
493 SOC_DOUBLE_R("Out1 Playback ZC Switch",
494 WM8350_LOUT1_VOLUME,
495 WM8350_ROUT1_VOLUME, 13, 1, 0),
496 SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume",
497 WM8350_LOUT2_VOLUME,
498 WM8350_ROUT2_VOLUME,
499 2, 63, 0, out_pga_tlv),
500 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
501 WM8350_ROUT2_VOLUME, 13, 1, 0),
502 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
503 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
504 5, 7, 0, out_mix_tlv),
505
506 SOC_DOUBLE_R("Out1 Playback Switch",
507 WM8350_LOUT1_VOLUME,
508 WM8350_ROUT1_VOLUME,
509 14, 1, 1),
510 SOC_DOUBLE_R("Out2 Playback Switch",
511 WM8350_LOUT2_VOLUME,
512 WM8350_ROUT2_VOLUME,
513 14, 1, 1),
514 };
515
516 /*
517 * DAPM Controls
518 */
519
520 /* Left Playback Mixer */
521 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
522 SOC_DAPM_SINGLE("Playback Switch",
523 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
524 SOC_DAPM_SINGLE("Left Bypass Switch",
525 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
526 SOC_DAPM_SINGLE("Right Playback Switch",
527 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
528 SOC_DAPM_SINGLE("Left Sidetone Switch",
529 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
530 SOC_DAPM_SINGLE("Right Sidetone Switch",
531 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
532 };
533
534 /* Right Playback Mixer */
535 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
536 SOC_DAPM_SINGLE("Playback Switch",
537 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
538 SOC_DAPM_SINGLE("Right Bypass Switch",
539 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
540 SOC_DAPM_SINGLE("Left Playback Switch",
541 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
542 SOC_DAPM_SINGLE("Left Sidetone Switch",
543 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
544 SOC_DAPM_SINGLE("Right Sidetone Switch",
545 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
546 };
547
548 /* Out4 Mixer */
549 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
550 SOC_DAPM_SINGLE("Right Playback Switch",
551 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
552 SOC_DAPM_SINGLE("Left Playback Switch",
553 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
554 SOC_DAPM_SINGLE("Right Capture Switch",
555 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
556 SOC_DAPM_SINGLE("Out3 Playback Switch",
557 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
558 SOC_DAPM_SINGLE("Right Mixer Switch",
559 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
560 SOC_DAPM_SINGLE("Left Mixer Switch",
561 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
562 };
563
564 /* Out3 Mixer */
565 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
566 SOC_DAPM_SINGLE("Left Playback Switch",
567 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
568 SOC_DAPM_SINGLE("Left Capture Switch",
569 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
570 SOC_DAPM_SINGLE("Out4 Playback Switch",
571 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
572 SOC_DAPM_SINGLE("Left Mixer Switch",
573 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
574 };
575
576 /* Left Input Mixer */
577 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
578 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
579 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
580 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
581 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
582 SOC_DAPM_SINGLE("PGA Capture Switch",
583 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
584 };
585
586 /* Right Input Mixer */
587 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
588 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
589 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
590 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
591 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
592 SOC_DAPM_SINGLE("PGA Capture Switch",
593 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
594 };
595
596 /* Left Mic Mixer */
597 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
598 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
599 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
600 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
601 };
602
603 /* Right Mic Mixer */
604 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
605 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
606 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
607 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
608 };
609
610 /* Beep Switch */
611 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
612 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
613
614 /* Out4 Capture Mux */
615 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
616 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
617
618 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
619
620 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
621 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
622 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
623 0, pga_event,
624 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
625 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
626 pga_event,
627 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
628 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
629 0, pga_event,
630 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
631 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
632 pga_event,
633 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
634
635 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
636 7, 0, &wm8350_right_capt_mixer_controls[0],
637 ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
638
639 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
640 6, 0, &wm8350_left_capt_mixer_controls[0],
641 ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
642
643 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
644 &wm8350_out4_mixer_controls[0],
645 ARRAY_SIZE(wm8350_out4_mixer_controls)),
646
647 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
648 &wm8350_out3_mixer_controls[0],
649 ARRAY_SIZE(wm8350_out3_mixer_controls)),
650
651 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
652 &wm8350_right_play_mixer_controls[0],
653 ARRAY_SIZE(wm8350_right_play_mixer_controls)),
654
655 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
656 &wm8350_left_play_mixer_controls[0],
657 ARRAY_SIZE(wm8350_left_play_mixer_controls)),
658
659 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
660 &wm8350_left_mic_mixer_controls[0],
661 ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
662
663 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
664 &wm8350_right_mic_mixer_controls[0],
665 ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
666
667 /* virtual mixer for Beep and Out2R */
668 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
669
670 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
671 &wm8350_beep_switch_controls),
672
673 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
674 WM8350_POWER_MGMT_4, 3, 0),
675 SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
676 WM8350_POWER_MGMT_4, 2, 0),
677 SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
678 WM8350_POWER_MGMT_4, 5, 0),
679 SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
680 WM8350_POWER_MGMT_4, 4, 0),
681
682 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
683
684 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
685 &wm8350_out4_capture_controls),
686
687 SND_SOC_DAPM_OUTPUT("OUT1R"),
688 SND_SOC_DAPM_OUTPUT("OUT1L"),
689 SND_SOC_DAPM_OUTPUT("OUT2R"),
690 SND_SOC_DAPM_OUTPUT("OUT2L"),
691 SND_SOC_DAPM_OUTPUT("OUT3"),
692 SND_SOC_DAPM_OUTPUT("OUT4"),
693
694 SND_SOC_DAPM_INPUT("IN1RN"),
695 SND_SOC_DAPM_INPUT("IN1RP"),
696 SND_SOC_DAPM_INPUT("IN2R"),
697 SND_SOC_DAPM_INPUT("IN1LP"),
698 SND_SOC_DAPM_INPUT("IN1LN"),
699 SND_SOC_DAPM_INPUT("IN2L"),
700 SND_SOC_DAPM_INPUT("IN3R"),
701 SND_SOC_DAPM_INPUT("IN3L"),
702 };
703
704 static const struct snd_soc_dapm_route audio_map[] = {
705
706 /* left playback mixer */
707 {"Left Playback Mixer", "Playback Switch", "Left DAC"},
708 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
709 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
710 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
711 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
712
713 /* right playback mixer */
714 {"Right Playback Mixer", "Playback Switch", "Right DAC"},
715 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
716 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
717 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
718 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
719
720 /* out4 playback mixer */
721 {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
722 {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
723 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
724 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
725 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
726 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
727 {"OUT4", NULL, "Out4 Mixer"},
728
729 /* out3 playback mixer */
730 {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
731 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
732 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
733 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
734 {"OUT3", NULL, "Out3 Mixer"},
735
736 /* out2 */
737 {"Right Out2 PGA", NULL, "Right Playback Mixer"},
738 {"Left Out2 PGA", NULL, "Left Playback Mixer"},
739 {"OUT2L", NULL, "Left Out2 PGA"},
740 {"OUT2R", NULL, "Right Out2 PGA"},
741
742 /* out1 */
743 {"Right Out1 PGA", NULL, "Right Playback Mixer"},
744 {"Left Out1 PGA", NULL, "Left Playback Mixer"},
745 {"OUT1L", NULL, "Left Out1 PGA"},
746 {"OUT1R", NULL, "Right Out1 PGA"},
747
748 /* ADCs */
749 {"Left ADC", NULL, "Left Capture Mixer"},
750 {"Right ADC", NULL, "Right Capture Mixer"},
751
752 /* Left capture mixer */
753 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
754 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
755 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
756 {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
757
758 /* Right capture mixer */
759 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
760 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
761 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
762 {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
763
764 /* L3 Inputs */
765 {"IN3L PGA", NULL, "IN3L"},
766 {"IN3R PGA", NULL, "IN3R"},
767
768 /* Left Mic mixer */
769 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
770 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
771 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
772
773 /* Right Mic mixer */
774 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
775 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
776 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
777
778 /* out 4 capture */
779 {"Out4 Capture Channel", NULL, "Out4 Mixer"},
780
781 /* Beep */
782 {"Beep", NULL, "IN3R PGA"},
783 };
784
785 static int wm8350_add_widgets(struct snd_soc_codec *codec)
786 {
787 int ret;
788
789 ret = snd_soc_dapm_new_controls(codec,
790 wm8350_dapm_widgets,
791 ARRAY_SIZE(wm8350_dapm_widgets));
792 if (ret != 0) {
793 dev_err(codec->dev, "dapm control register failed\n");
794 return ret;
795 }
796
797 /* set up audio paths */
798 ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
799 if (ret != 0) {
800 dev_err(codec->dev, "DAPM route register failed\n");
801 return ret;
802 }
803
804 return 0;
805 }
806
807 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
808 int clk_id, unsigned int freq, int dir)
809 {
810 struct snd_soc_codec *codec = codec_dai->codec;
811 struct wm8350 *wm8350 = codec->control_data;
812 u16 fll_4;
813
814 switch (clk_id) {
815 case WM8350_MCLK_SEL_MCLK:
816 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
817 WM8350_MCLK_SEL);
818 break;
819 case WM8350_MCLK_SEL_PLL_MCLK:
820 case WM8350_MCLK_SEL_PLL_DAC:
821 case WM8350_MCLK_SEL_PLL_ADC:
822 case WM8350_MCLK_SEL_PLL_32K:
823 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
824 WM8350_MCLK_SEL);
825 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
826 ~WM8350_FLL_CLK_SRC_MASK;
827 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
828 break;
829 }
830
831 /* MCLK direction */
832 if (dir == WM8350_MCLK_DIR_OUT)
833 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
834 WM8350_MCLK_DIR);
835 else
836 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
837 WM8350_MCLK_DIR);
838
839 return 0;
840 }
841
842 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
843 {
844 struct snd_soc_codec *codec = codec_dai->codec;
845 u16 val;
846
847 switch (div_id) {
848 case WM8350_ADC_CLKDIV:
849 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) &
850 ~WM8350_ADC_CLKDIV_MASK;
851 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div);
852 break;
853 case WM8350_DAC_CLKDIV:
854 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) &
855 ~WM8350_DAC_CLKDIV_MASK;
856 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
857 break;
858 case WM8350_BCLK_CLKDIV:
859 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
860 ~WM8350_BCLK_DIV_MASK;
861 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
862 break;
863 case WM8350_OPCLK_CLKDIV:
864 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
865 ~WM8350_OPCLK_DIV_MASK;
866 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
867 break;
868 case WM8350_SYS_CLKDIV:
869 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
870 ~WM8350_MCLK_DIV_MASK;
871 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
872 break;
873 case WM8350_DACLR_CLKDIV:
874 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
875 ~WM8350_DACLRC_RATE_MASK;
876 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div);
877 break;
878 case WM8350_ADCLR_CLKDIV:
879 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
880 ~WM8350_ADCLRC_RATE_MASK;
881 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div);
882 break;
883 default:
884 return -EINVAL;
885 }
886
887 return 0;
888 }
889
890 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
891 {
892 struct snd_soc_codec *codec = codec_dai->codec;
893 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
894 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
895 u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) &
896 ~WM8350_BCLK_MSTR;
897 u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
898 ~WM8350_DACLRC_ENA;
899 u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
900 ~WM8350_ADCLRC_ENA;
901
902 /* set master/slave audio interface */
903 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
904 case SND_SOC_DAIFMT_CBM_CFM:
905 master |= WM8350_BCLK_MSTR;
906 dac_lrc |= WM8350_DACLRC_ENA;
907 adc_lrc |= WM8350_ADCLRC_ENA;
908 break;
909 case SND_SOC_DAIFMT_CBS_CFS:
910 break;
911 default:
912 return -EINVAL;
913 }
914
915 /* interface format */
916 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
917 case SND_SOC_DAIFMT_I2S:
918 iface |= 0x2 << 8;
919 break;
920 case SND_SOC_DAIFMT_RIGHT_J:
921 break;
922 case SND_SOC_DAIFMT_LEFT_J:
923 iface |= 0x1 << 8;
924 break;
925 case SND_SOC_DAIFMT_DSP_A:
926 iface |= 0x3 << 8;
927 break;
928 case SND_SOC_DAIFMT_DSP_B:
929 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
930 break;
931 default:
932 return -EINVAL;
933 }
934
935 /* clock inversion */
936 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
937 case SND_SOC_DAIFMT_NB_NF:
938 break;
939 case SND_SOC_DAIFMT_IB_IF:
940 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
941 break;
942 case SND_SOC_DAIFMT_IB_NF:
943 iface |= WM8350_AIF_BCLK_INV;
944 break;
945 case SND_SOC_DAIFMT_NB_IF:
946 iface |= WM8350_AIF_LRCLK_INV;
947 break;
948 default:
949 return -EINVAL;
950 }
951
952 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
953 wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master);
954 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
955 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
956 return 0;
957 }
958
959 static int wm8350_pcm_trigger(struct snd_pcm_substream *substream,
960 int cmd, struct snd_soc_dai *codec_dai)
961 {
962 struct snd_soc_codec *codec = codec_dai->codec;
963 int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) &
964 WM8350_BCLK_MSTR;
965 int enabled = 0;
966
967 /* Check that the DACs or ADCs are enabled since they are
968 * required for LRC in master mode. The DACs or ADCs need a
969 * valid audio path i.e. pin -> ADC or DAC -> pin before
970 * the LRC will be enabled in master mode. */
971 if (!master || cmd != SNDRV_PCM_TRIGGER_START)
972 return 0;
973
974 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
975 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
976 (WM8350_ADCR_ENA | WM8350_ADCL_ENA);
977 } else {
978 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
979 (WM8350_DACR_ENA | WM8350_DACL_ENA);
980 }
981
982 if (!enabled) {
983 dev_err(codec->dev,
984 "%s: invalid audio path - no clocks available\n",
985 __func__);
986 return -EINVAL;
987 }
988 return 0;
989 }
990
991 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
992 struct snd_pcm_hw_params *params,
993 struct snd_soc_dai *codec_dai)
994 {
995 struct snd_soc_codec *codec = codec_dai->codec;
996 struct wm8350 *wm8350 = codec->control_data;
997 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
998 ~WM8350_AIF_WL_MASK;
999
1000 /* bit size */
1001 switch (params_format(params)) {
1002 case SNDRV_PCM_FORMAT_S16_LE:
1003 break;
1004 case SNDRV_PCM_FORMAT_S20_3LE:
1005 iface |= 0x1 << 10;
1006 break;
1007 case SNDRV_PCM_FORMAT_S24_LE:
1008 iface |= 0x2 << 10;
1009 break;
1010 case SNDRV_PCM_FORMAT_S32_LE:
1011 iface |= 0x3 << 10;
1012 break;
1013 }
1014
1015 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
1016
1017 /* The sloping stopband filter is recommended for use with
1018 * lower sample rates to improve performance.
1019 */
1020 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1021 if (params_rate(params) < 24000)
1022 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1023 WM8350_DAC_SB_FILT);
1024 else
1025 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1026 WM8350_DAC_SB_FILT);
1027 }
1028
1029 return 0;
1030 }
1031
1032 static int wm8350_mute(struct snd_soc_dai *dai, int mute)
1033 {
1034 struct snd_soc_codec *codec = dai->codec;
1035 struct wm8350 *wm8350 = codec->control_data;
1036
1037 if (mute)
1038 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1039 else
1040 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1041 return 0;
1042 }
1043
1044 /* FLL divisors */
1045 struct _fll_div {
1046 int div; /* FLL_OUTDIV */
1047 int n;
1048 int k;
1049 int ratio; /* FLL_FRATIO */
1050 };
1051
1052 /* The size in bits of the fll divide multiplied by 10
1053 * to allow rounding later */
1054 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1055
1056 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
1057 unsigned int output)
1058 {
1059 u64 Kpart;
1060 unsigned int t1, t2, K, Nmod;
1061
1062 if (output >= 2815250 && output <= 3125000)
1063 fll_div->div = 0x4;
1064 else if (output >= 5625000 && output <= 6250000)
1065 fll_div->div = 0x3;
1066 else if (output >= 11250000 && output <= 12500000)
1067 fll_div->div = 0x2;
1068 else if (output >= 22500000 && output <= 25000000)
1069 fll_div->div = 0x1;
1070 else {
1071 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
1072 return -EINVAL;
1073 }
1074
1075 if (input > 48000)
1076 fll_div->ratio = 1;
1077 else
1078 fll_div->ratio = 8;
1079
1080 t1 = output * (1 << (fll_div->div + 1));
1081 t2 = input * fll_div->ratio;
1082
1083 fll_div->n = t1 / t2;
1084 Nmod = t1 % t2;
1085
1086 if (Nmod) {
1087 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1088 do_div(Kpart, t2);
1089 K = Kpart & 0xFFFFFFFF;
1090
1091 /* Check if we need to round */
1092 if ((K % 10) >= 5)
1093 K += 5;
1094
1095 /* Move down to proper range now rounding is done */
1096 K /= 10;
1097 fll_div->k = K;
1098 } else
1099 fll_div->k = 0;
1100
1101 return 0;
1102 }
1103
1104 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1105 int pll_id, int source, unsigned int freq_in,
1106 unsigned int freq_out)
1107 {
1108 struct snd_soc_codec *codec = codec_dai->codec;
1109 struct wm8350 *wm8350 = codec->control_data;
1110 struct wm8350_data *priv = codec->private_data;
1111 struct _fll_div fll_div;
1112 int ret = 0;
1113 u16 fll_1, fll_4;
1114
1115 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1116 return 0;
1117
1118 /* power down FLL - we need to do this for reconfiguration */
1119 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1120 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1121
1122 if (freq_out == 0 || freq_in == 0)
1123 return ret;
1124
1125 ret = fll_factors(&fll_div, freq_in, freq_out);
1126 if (ret < 0)
1127 return ret;
1128 dev_dbg(wm8350->dev,
1129 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1130 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1131 fll_div.ratio);
1132
1133 /* set up N.K & dividers */
1134 fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) &
1135 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1136 wm8350_codec_write(codec, WM8350_FLL_CONTROL_1,
1137 fll_1 | (fll_div.div << 8) | 0x50);
1138 wm8350_codec_write(codec, WM8350_FLL_CONTROL_2,
1139 (fll_div.ratio << 11) | (fll_div.
1140 n & WM8350_FLL_N_MASK));
1141 wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1142 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
1143 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1144 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4,
1145 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1146 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1147
1148 /* power FLL on */
1149 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1150 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1151
1152 priv->fll_freq_out = freq_out;
1153 priv->fll_freq_in = freq_in;
1154
1155 return 0;
1156 }
1157
1158 static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1159 enum snd_soc_bias_level level)
1160 {
1161 struct wm8350 *wm8350 = codec->control_data;
1162 struct wm8350_data *priv = codec->private_data;
1163 struct wm8350_audio_platform_data *platform =
1164 wm8350->codec.platform_data;
1165 u16 pm1;
1166 int ret;
1167
1168 switch (level) {
1169 case SND_SOC_BIAS_ON:
1170 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1171 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1172 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1173 pm1 | WM8350_VMID_50K |
1174 platform->codec_current_on << 14);
1175 break;
1176
1177 case SND_SOC_BIAS_PREPARE:
1178 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1179 pm1 &= ~WM8350_VMID_MASK;
1180 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1181 pm1 | WM8350_VMID_50K);
1182 break;
1183
1184 case SND_SOC_BIAS_STANDBY:
1185 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1186 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1187 priv->supplies);
1188 if (ret != 0)
1189 return ret;
1190
1191 /* Enable the system clock */
1192 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1193 WM8350_SYSCLK_ENA);
1194
1195 /* mute DAC & outputs */
1196 wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1197 WM8350_DAC_MUTE_ENA);
1198
1199 /* discharge cap memory */
1200 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1201 platform->dis_out1 |
1202 (platform->dis_out2 << 2) |
1203 (platform->dis_out3 << 4) |
1204 (platform->dis_out4 << 6));
1205
1206 /* wait for discharge */
1207 schedule_timeout_interruptible(msecs_to_jiffies
1208 (platform->
1209 cap_discharge_msecs));
1210
1211 /* enable antipop */
1212 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1213 (platform->vmid_s_curve << 8));
1214
1215 /* ramp up vmid */
1216 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1217 (platform->
1218 codec_current_charge << 14) |
1219 WM8350_VMID_5K | WM8350_VMIDEN |
1220 WM8350_VBUFEN);
1221
1222 /* wait for vmid */
1223 schedule_timeout_interruptible(msecs_to_jiffies
1224 (platform->
1225 vmid_charge_msecs));
1226
1227 /* turn on vmid 300k */
1228 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1229 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1230 pm1 |= WM8350_VMID_300K |
1231 (platform->codec_current_standby << 14);
1232 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1233 pm1);
1234
1235
1236 /* enable analogue bias */
1237 pm1 |= WM8350_BIASEN;
1238 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1239
1240 /* disable antipop */
1241 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1242
1243 } else {
1244 /* turn on vmid 300k and reduce current */
1245 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1246 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1247 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1248 pm1 | WM8350_VMID_300K |
1249 (platform->
1250 codec_current_standby << 14));
1251
1252 }
1253 break;
1254
1255 case SND_SOC_BIAS_OFF:
1256
1257 /* mute DAC & enable outputs */
1258 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1259
1260 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1261 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1262 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1263
1264 /* enable anti pop S curve */
1265 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1266 (platform->vmid_s_curve << 8));
1267
1268 /* turn off vmid */
1269 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1270 ~WM8350_VMIDEN;
1271 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1272
1273 /* wait */
1274 schedule_timeout_interruptible(msecs_to_jiffies
1275 (platform->
1276 vmid_discharge_msecs));
1277
1278 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1279 (platform->vmid_s_curve << 8) |
1280 platform->dis_out1 |
1281 (platform->dis_out2 << 2) |
1282 (platform->dis_out3 << 4) |
1283 (platform->dis_out4 << 6));
1284
1285 /* turn off VBuf and drain */
1286 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1287 ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1288 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1289 pm1 | WM8350_OUTPUT_DRAIN_EN);
1290
1291 /* wait */
1292 schedule_timeout_interruptible(msecs_to_jiffies
1293 (platform->drain_msecs));
1294
1295 pm1 &= ~WM8350_BIASEN;
1296 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1297
1298 /* disable anti-pop */
1299 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1300
1301 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1302 WM8350_OUT1L_ENA);
1303 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1304 WM8350_OUT1R_ENA);
1305 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1306 WM8350_OUT2L_ENA);
1307 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1308 WM8350_OUT2R_ENA);
1309
1310 /* disable clock gen */
1311 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1312 WM8350_SYSCLK_ENA);
1313
1314 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1315 priv->supplies);
1316 break;
1317 }
1318 codec->bias_level = level;
1319 return 0;
1320 }
1321
1322 static int wm8350_suspend(struct platform_device *pdev, pm_message_t state)
1323 {
1324 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1325 struct snd_soc_codec *codec = socdev->card->codec;
1326
1327 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1328 return 0;
1329 }
1330
1331 static int wm8350_resume(struct platform_device *pdev)
1332 {
1333 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1334 struct snd_soc_codec *codec = socdev->card->codec;
1335
1336 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1337
1338 if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
1339 wm8350_set_bias_level(codec, SND_SOC_BIAS_ON);
1340
1341 return 0;
1342 }
1343
1344 static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1345 {
1346 struct wm8350_data *priv = data;
1347 struct wm8350 *wm8350 = priv->codec.control_data;
1348 u16 reg;
1349 int report;
1350 int mask;
1351 struct wm8350_jack_data *jack = NULL;
1352
1353 switch (irq - wm8350->irq_base) {
1354 case WM8350_IRQ_CODEC_JCK_DET_L:
1355 jack = &priv->hpl;
1356 mask = WM8350_JACK_L_LVL;
1357 break;
1358
1359 case WM8350_IRQ_CODEC_JCK_DET_R:
1360 jack = &priv->hpr;
1361 mask = WM8350_JACK_R_LVL;
1362 break;
1363
1364 default:
1365 BUG();
1366 }
1367
1368 if (!jack->jack) {
1369 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n");
1370 return IRQ_NONE;
1371 }
1372
1373 /* Debounce */
1374 msleep(200);
1375
1376 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1377 if (reg & mask)
1378 report = jack->report;
1379 else
1380 report = 0;
1381
1382 snd_soc_jack_report(jack->jack, report, jack->report);
1383
1384 return IRQ_HANDLED;
1385 }
1386
1387 /**
1388 * wm8350_hp_jack_detect - Enable headphone jack detection.
1389 *
1390 * @codec: WM8350 codec
1391 * @which: left or right jack detect signal
1392 * @jack: jack to report detection events on
1393 * @report: value to report
1394 *
1395 * Enables the headphone jack detection of the WM8350.
1396 */
1397 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1398 struct snd_soc_jack *jack, int report)
1399 {
1400 struct wm8350_data *priv = codec->private_data;
1401 struct wm8350 *wm8350 = codec->control_data;
1402 int irq;
1403 int ena;
1404
1405 switch (which) {
1406 case WM8350_JDL:
1407 priv->hpl.jack = jack;
1408 priv->hpl.report = report;
1409 irq = WM8350_IRQ_CODEC_JCK_DET_L;
1410 ena = WM8350_JDL_ENA;
1411 break;
1412
1413 case WM8350_JDR:
1414 priv->hpr.jack = jack;
1415 priv->hpr.report = report;
1416 irq = WM8350_IRQ_CODEC_JCK_DET_R;
1417 ena = WM8350_JDR_ENA;
1418 break;
1419
1420 default:
1421 return -EINVAL;
1422 }
1423
1424 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1425 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1426
1427 /* Sync status */
1428 wm8350_hp_jack_handler(irq + wm8350->irq_base, priv);
1429
1430 return 0;
1431 }
1432 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1433
1434 static struct snd_soc_codec *wm8350_codec;
1435
1436 static int wm8350_probe(struct platform_device *pdev)
1437 {
1438 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1439 struct snd_soc_codec *codec;
1440 struct wm8350 *wm8350;
1441 struct wm8350_data *priv;
1442 int ret;
1443 struct wm8350_output *out1;
1444 struct wm8350_output *out2;
1445
1446 BUG_ON(!wm8350_codec);
1447
1448 socdev->card->codec = wm8350_codec;
1449 codec = socdev->card->codec;
1450 wm8350 = codec->control_data;
1451 priv = codec->private_data;
1452
1453 /* Enable the codec */
1454 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1455
1456 /* Enable robust clocking mode in ADC */
1457 wm8350_codec_write(codec, WM8350_SECURITY, 0xa7);
1458 wm8350_codec_write(codec, 0xde, 0x13);
1459 wm8350_codec_write(codec, WM8350_SECURITY, 0);
1460
1461 /* read OUT1 & OUT2 volumes */
1462 out1 = &priv->out1;
1463 out2 = &priv->out2;
1464 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1465 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1466 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1467 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1468 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1469 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1470 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1471 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1472 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1473 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1474 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1475 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1476
1477 /* Latch VU bits & mute */
1478 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1479 WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1480 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1481 WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1482 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1483 WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1484 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1485 WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1486
1487 /* Make sure jack detect is disabled to start off with */
1488 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1489 WM8350_JDL_ENA | WM8350_JDR_ENA);
1490
1491 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1492 wm8350_hp_jack_handler, 0, "Left jack detect",
1493 priv);
1494 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1495 wm8350_hp_jack_handler, 0, "Right jack detect",
1496 priv);
1497
1498 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1499 if (ret < 0) {
1500 dev_err(&pdev->dev, "failed to create pcms\n");
1501 return ret;
1502 }
1503
1504 snd_soc_add_controls(codec, wm8350_snd_controls,
1505 ARRAY_SIZE(wm8350_snd_controls));
1506 wm8350_add_widgets(codec);
1507
1508 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1509
1510 return 0;
1511 }
1512
1513 static int wm8350_remove(struct platform_device *pdev)
1514 {
1515 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1516 struct snd_soc_codec *codec = socdev->card->codec;
1517 struct wm8350 *wm8350 = codec->control_data;
1518 struct wm8350_data *priv = codec->private_data;
1519 int ret;
1520
1521 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1522 WM8350_JDL_ENA | WM8350_JDR_ENA);
1523 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1524
1525 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1526 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1527
1528 priv->hpl.jack = NULL;
1529 priv->hpr.jack = NULL;
1530
1531 /* cancel any work waiting to be queued. */
1532 ret = cancel_delayed_work(&codec->delayed_work);
1533
1534 /* if there was any work waiting then we run it now and
1535 * wait for its completion */
1536 if (ret) {
1537 schedule_delayed_work(&codec->delayed_work, 0);
1538 flush_scheduled_work();
1539 }
1540
1541 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1542
1543 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1544
1545 return 0;
1546 }
1547
1548 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1549
1550 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1551 SNDRV_PCM_FMTBIT_S20_3LE |\
1552 SNDRV_PCM_FMTBIT_S24_LE)
1553
1554 static struct snd_soc_dai_ops wm8350_dai_ops = {
1555 .hw_params = wm8350_pcm_hw_params,
1556 .digital_mute = wm8350_mute,
1557 .trigger = wm8350_pcm_trigger,
1558 .set_fmt = wm8350_set_dai_fmt,
1559 .set_sysclk = wm8350_set_dai_sysclk,
1560 .set_pll = wm8350_set_fll,
1561 .set_clkdiv = wm8350_set_clkdiv,
1562 };
1563
1564 struct snd_soc_dai wm8350_dai = {
1565 .name = "WM8350",
1566 .playback = {
1567 .stream_name = "Playback",
1568 .channels_min = 1,
1569 .channels_max = 2,
1570 .rates = WM8350_RATES,
1571 .formats = WM8350_FORMATS,
1572 },
1573 .capture = {
1574 .stream_name = "Capture",
1575 .channels_min = 1,
1576 .channels_max = 2,
1577 .rates = WM8350_RATES,
1578 .formats = WM8350_FORMATS,
1579 },
1580 .ops = &wm8350_dai_ops,
1581 };
1582 EXPORT_SYMBOL_GPL(wm8350_dai);
1583
1584 struct snd_soc_codec_device soc_codec_dev_wm8350 = {
1585 .probe = wm8350_probe,
1586 .remove = wm8350_remove,
1587 .suspend = wm8350_suspend,
1588 .resume = wm8350_resume,
1589 };
1590 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8350);
1591
1592 static __devinit int wm8350_codec_probe(struct platform_device *pdev)
1593 {
1594 struct wm8350 *wm8350 = platform_get_drvdata(pdev);
1595 struct wm8350_data *priv;
1596 struct snd_soc_codec *codec;
1597 int ret, i;
1598
1599 if (wm8350->codec.platform_data == NULL) {
1600 dev_err(&pdev->dev, "No audio platform data supplied\n");
1601 return -EINVAL;
1602 }
1603
1604 priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
1605 if (priv == NULL)
1606 return -ENOMEM;
1607
1608 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1609 priv->supplies[i].supply = supply_names[i];
1610
1611 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1612 priv->supplies);
1613 if (ret != 0)
1614 goto err_priv;
1615
1616 codec = &priv->codec;
1617 wm8350->codec.codec = codec;
1618
1619 wm8350_dai.dev = &pdev->dev;
1620
1621 mutex_init(&codec->mutex);
1622 INIT_LIST_HEAD(&codec->dapm_widgets);
1623 INIT_LIST_HEAD(&codec->dapm_paths);
1624 codec->dev = &pdev->dev;
1625 codec->name = "WM8350";
1626 codec->owner = THIS_MODULE;
1627 codec->read = wm8350_codec_read;
1628 codec->write = wm8350_codec_write;
1629 codec->bias_level = SND_SOC_BIAS_OFF;
1630 codec->set_bias_level = wm8350_set_bias_level;
1631 codec->dai = &wm8350_dai;
1632 codec->num_dai = 1;
1633 codec->reg_cache_size = WM8350_MAX_REGISTER;
1634 codec->private_data = priv;
1635 codec->control_data = wm8350;
1636
1637 /* Put the codec into reset if it wasn't already */
1638 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1639
1640 INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work);
1641 ret = snd_soc_register_codec(codec);
1642 if (ret != 0)
1643 goto err_supply;
1644
1645 wm8350_codec = codec;
1646
1647 ret = snd_soc_register_dai(&wm8350_dai);
1648 if (ret != 0)
1649 goto err_codec;
1650 return 0;
1651
1652 err_codec:
1653 snd_soc_unregister_codec(codec);
1654 err_supply:
1655 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1656 err_priv:
1657 kfree(priv);
1658 wm8350_codec = NULL;
1659 return ret;
1660 }
1661
1662 static int __devexit wm8350_codec_remove(struct platform_device *pdev)
1663 {
1664 struct wm8350 *wm8350 = platform_get_drvdata(pdev);
1665 struct snd_soc_codec *codec = wm8350->codec.codec;
1666 struct wm8350_data *priv = codec->private_data;
1667
1668 snd_soc_unregister_dai(&wm8350_dai);
1669 snd_soc_unregister_codec(codec);
1670 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1671 kfree(priv);
1672 wm8350_codec = NULL;
1673 return 0;
1674 }
1675
1676 static struct platform_driver wm8350_codec_driver = {
1677 .driver = {
1678 .name = "wm8350-codec",
1679 .owner = THIS_MODULE,
1680 },
1681 .probe = wm8350_codec_probe,
1682 .remove = __devexit_p(wm8350_codec_remove),
1683 };
1684
1685 static __init int wm8350_init(void)
1686 {
1687 return platform_driver_register(&wm8350_codec_driver);
1688 }
1689 module_init(wm8350_init);
1690
1691 static __exit void wm8350_exit(void)
1692 {
1693 platform_driver_unregister(&wm8350_codec_driver);
1694 }
1695 module_exit(wm8350_exit);
1696
1697 MODULE_DESCRIPTION("ASoC WM8350 driver");
1698 MODULE_AUTHOR("Liam Girdwood");
1699 MODULE_LICENSE("GPL");
1700 MODULE_ALIAS("platform:wm8350-codec");
linux-next