?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
powerpc/pmac: Add missing unlocks in error path
[linux-2.6/next.git] / sound / soc / imx / imx-ssi.c
blob6546b06cbd2a5984709eca74450fee6b7dfba083
1 /*
2 * imx-ssi.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 *
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developped with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
25 * rate.
26 * Reading and writing AC97 registers is another challange. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
31 *
32 */
33
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/device.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/init.h>
39 #include <linux/interrupt.h>
40 #include <linux/module.h>
41 #include <linux/platform_device.h>
42 #include <linux/slab.h>
43
44 #include <sound/core.h>
45 #include <sound/initval.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49
50 #include <mach/ssi.h>
51 #include <mach/hardware.h>
52
53 #include "imx-ssi.h"
54
55 #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
56
57 /*
58 * SSI Network Mode or TDM slots configuration.
59 * Should only be called when port is inactive (i.e. SSIEN = 0).
60 */
61 static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
62 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
63 {
64 struct imx_ssi *ssi = cpu_dai->private_data;
65 u32 sccr;
66
67 sccr = readl(ssi->base + SSI_STCCR);
68 sccr &= ~SSI_STCCR_DC_MASK;
69 sccr |= SSI_STCCR_DC(slots - 1);
70 writel(sccr, ssi->base + SSI_STCCR);
71
72 sccr = readl(ssi->base + SSI_SRCCR);
73 sccr &= ~SSI_STCCR_DC_MASK;
74 sccr |= SSI_STCCR_DC(slots - 1);
75 writel(sccr, ssi->base + SSI_SRCCR);
76
77 writel(tx_mask, ssi->base + SSI_STMSK);
78 writel(rx_mask, ssi->base + SSI_SRMSK);
79
80 return 0;
81 }
82
83 /*
84 * SSI DAI format configuration.
85 * Should only be called when port is inactive (i.e. SSIEN = 0).
86 * Note: We don't use the I2S modes but instead manually configure the
87 * SSI for I2S because the I2S mode is only a register preset.
88 */
89 static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
90 {
91 struct imx_ssi *ssi = cpu_dai->private_data;
92 u32 strcr = 0, scr;
93
94 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
95
96 /* DAI mode */
97 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
98 case SND_SOC_DAIFMT_I2S:
99 /* data on rising edge of bclk, frame low 1clk before data */
100 strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
101 scr |= SSI_SCR_NET;
102 break;
103 case SND_SOC_DAIFMT_LEFT_J:
104 /* data on rising edge of bclk, frame high with data */
105 strcr |= SSI_STCR_TXBIT0;
106 break;
107 case SND_SOC_DAIFMT_DSP_B:
108 /* data on rising edge of bclk, frame high with data */
109 strcr |= SSI_STCR_TFSL;
110 break;
111 case SND_SOC_DAIFMT_DSP_A:
112 /* data on rising edge of bclk, frame high 1clk before data */
113 strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
114 break;
115 }
116
117 /* DAI clock inversion */
118 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
119 case SND_SOC_DAIFMT_IB_IF:
120 strcr |= SSI_STCR_TFSI;
121 strcr &= ~SSI_STCR_TSCKP;
122 break;
123 case SND_SOC_DAIFMT_IB_NF:
124 strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
125 break;
126 case SND_SOC_DAIFMT_NB_IF:
127 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
128 break;
129 case SND_SOC_DAIFMT_NB_NF:
130 strcr &= ~SSI_STCR_TFSI;
131 strcr |= SSI_STCR_TSCKP;
132 break;
133 }
134
135 /* DAI clock master masks */
136 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
137 case SND_SOC_DAIFMT_CBM_CFM:
138 break;
139 default:
140 /* Master mode not implemented, needs handling of clocks. */
141 return -EINVAL;
142 }
143
144 strcr |= SSI_STCR_TFEN0;
145
146 writel(strcr, ssi->base + SSI_STCR);
147 writel(strcr, ssi->base + SSI_SRCR);
148 writel(scr, ssi->base + SSI_SCR);
149
150 return 0;
151 }
152
153 /*
154 * SSI system clock configuration.
155 * Should only be called when port is inactive (i.e. SSIEN = 0).
156 */
157 static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
158 int clk_id, unsigned int freq, int dir)
159 {
160 struct imx_ssi *ssi = cpu_dai->private_data;
161 u32 scr;
162
163 scr = readl(ssi->base + SSI_SCR);
164
165 switch (clk_id) {
166 case IMX_SSP_SYS_CLK:
167 if (dir == SND_SOC_CLOCK_OUT)
168 scr |= SSI_SCR_SYS_CLK_EN;
169 else
170 scr &= ~SSI_SCR_SYS_CLK_EN;
171 break;
172 default:
173 return -EINVAL;
174 }
175
176 writel(scr, ssi->base + SSI_SCR);
177
178 return 0;
179 }
180
181 /*
182 * SSI Clock dividers
183 * Should only be called when port is inactive (i.e. SSIEN = 0).
184 */
185 static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
186 int div_id, int div)
187 {
188 struct imx_ssi *ssi = cpu_dai->private_data;
189 u32 stccr, srccr;
190
191 stccr = readl(ssi->base + SSI_STCCR);
192 srccr = readl(ssi->base + SSI_SRCCR);
193
194 switch (div_id) {
195 case IMX_SSI_TX_DIV_2:
196 stccr &= ~SSI_STCCR_DIV2;
197 stccr |= div;
198 break;
199 case IMX_SSI_TX_DIV_PSR:
200 stccr &= ~SSI_STCCR_PSR;
201 stccr |= div;
202 break;
203 case IMX_SSI_TX_DIV_PM:
204 stccr &= ~0xff;
205 stccr |= SSI_STCCR_PM(div);
206 break;
207 case IMX_SSI_RX_DIV_2:
208 stccr &= ~SSI_STCCR_DIV2;
209 stccr |= div;
210 break;
211 case IMX_SSI_RX_DIV_PSR:
212 stccr &= ~SSI_STCCR_PSR;
213 stccr |= div;
214 break;
215 case IMX_SSI_RX_DIV_PM:
216 stccr &= ~0xff;
217 stccr |= SSI_STCCR_PM(div);
218 break;
219 default:
220 return -EINVAL;
221 }
222
223 writel(stccr, ssi->base + SSI_STCCR);
224 writel(srccr, ssi->base + SSI_SRCCR);
225
226 return 0;
227 }
228
229 /*
230 * Should only be called when port is inactive (i.e. SSIEN = 0),
231 * although can be called multiple times by upper layers.
232 */
233 static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
234 struct snd_pcm_hw_params *params,
235 struct snd_soc_dai *cpu_dai)
236 {
237 struct imx_ssi *ssi = cpu_dai->private_data;
238 u32 reg, sccr;
239
240 /* Tx/Rx config */
241 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
242 reg = SSI_STCCR;
243 cpu_dai->dma_data = &ssi->dma_params_tx;
244 } else {
245 reg = SSI_SRCCR;
246 cpu_dai->dma_data = &ssi->dma_params_rx;
247 }
248
249 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
250
251 /* DAI data (word) size */
252 switch (params_format(params)) {
253 case SNDRV_PCM_FORMAT_S16_LE:
254 sccr |= SSI_SRCCR_WL(16);
255 break;
256 case SNDRV_PCM_FORMAT_S20_3LE:
257 sccr |= SSI_SRCCR_WL(20);
258 break;
259 case SNDRV_PCM_FORMAT_S24_LE:
260 sccr |= SSI_SRCCR_WL(24);
261 break;
262 }
263
264 writel(sccr, ssi->base + reg);
265
266 return 0;
267 }
268
269 static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
270 struct snd_soc_dai *dai)
271 {
272 struct snd_soc_pcm_runtime *rtd = substream->private_data;
273 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
274 struct imx_ssi *ssi = cpu_dai->private_data;
275 unsigned int sier_bits, sier;
276 unsigned int scr;
277
278 scr = readl(ssi->base + SSI_SCR);
279 sier = readl(ssi->base + SSI_SIER);
280
281 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
282 if (ssi->flags & IMX_SSI_DMA)
283 sier_bits = SSI_SIER_TDMAE;
284 else
285 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
286 } else {
287 if (ssi->flags & IMX_SSI_DMA)
288 sier_bits = SSI_SIER_RDMAE;
289 else
290 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
291 }
292
293 switch (cmd) {
294 case SNDRV_PCM_TRIGGER_START:
295 case SNDRV_PCM_TRIGGER_RESUME:
296 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
297 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
298 scr |= SSI_SCR_TE;
299 else
300 scr |= SSI_SCR_RE;
301 sier |= sier_bits;
302
303 if (++ssi->enabled == 1)
304 scr |= SSI_SCR_SSIEN;
305
306 break;
307
308 case SNDRV_PCM_TRIGGER_STOP:
309 case SNDRV_PCM_TRIGGER_SUSPEND:
310 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
311 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
312 scr &= ~SSI_SCR_TE;
313 else
314 scr &= ~SSI_SCR_RE;
315 sier &= ~sier_bits;
316
317 if (--ssi->enabled == 0)
318 scr &= ~SSI_SCR_SSIEN;
319
320 break;
321 default:
322 return -EINVAL;
323 }
324
325 if (!(ssi->flags & IMX_SSI_USE_AC97))
326 /* rx/tx are always enabled to access ac97 registers */
327 writel(scr, ssi->base + SSI_SCR);
328
329 writel(sier, ssi->base + SSI_SIER);
330
331 return 0;
332 }
333
334 static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
335 .hw_params = imx_ssi_hw_params,
336 .set_fmt = imx_ssi_set_dai_fmt,
337 .set_clkdiv = imx_ssi_set_dai_clkdiv,
338 .set_sysclk = imx_ssi_set_dai_sysclk,
339 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
340 .trigger = imx_ssi_trigger,
341 };
342
343 static struct snd_soc_dai imx_ssi_dai = {
344 .playback = {
345 .channels_min = 2,
346 .channels_max = 2,
347 .rates = SNDRV_PCM_RATE_8000_96000,
348 .formats = SNDRV_PCM_FMTBIT_S16_LE,
349 },
350 .capture = {
351 .channels_min = 2,
352 .channels_max = 2,
353 .rates = SNDRV_PCM_RATE_8000_96000,
354 .formats = SNDRV_PCM_FMTBIT_S16_LE,
355 },
356 .ops = &imx_ssi_pcm_dai_ops,
357 };
358
359 int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
360 struct vm_area_struct *vma)
361 {
362 struct snd_pcm_runtime *runtime = substream->runtime;
363 int ret;
364
365 ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
366 runtime->dma_addr, runtime->dma_bytes);
367
368 pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
369 runtime->dma_area,
370 runtime->dma_addr,
371 runtime->dma_bytes);
372 return ret;
373 }
374
375 static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
376 {
377 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
378 struct snd_dma_buffer *buf = &substream->dma_buffer;
379 size_t size = IMX_SSI_DMABUF_SIZE;
380
381 buf->dev.type = SNDRV_DMA_TYPE_DEV;
382 buf->dev.dev = pcm->card->dev;
383 buf->private_data = NULL;
384 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
385 &buf->addr, GFP_KERNEL);
386 if (!buf->area)
387 return -ENOMEM;
388 buf->bytes = size;
389
390 return 0;
391 }
392
393 static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
394
395 int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
396 struct snd_pcm *pcm)
397 {
398
399 int ret = 0;
400
401 if (!card->dev->dma_mask)
402 card->dev->dma_mask = &imx_pcm_dmamask;
403 if (!card->dev->coherent_dma_mask)
404 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
405 if (dai->playback.channels_min) {
406 ret = imx_pcm_preallocate_dma_buffer(pcm,
407 SNDRV_PCM_STREAM_PLAYBACK);
408 if (ret)
409 goto out;
410 }
411
412 if (dai->capture.channels_min) {
413 ret = imx_pcm_preallocate_dma_buffer(pcm,
414 SNDRV_PCM_STREAM_CAPTURE);
415 if (ret)
416 goto out;
417 }
418
419 out:
420 return ret;
421 }
422
423 void imx_pcm_free(struct snd_pcm *pcm)
424 {
425 struct snd_pcm_substream *substream;
426 struct snd_dma_buffer *buf;
427 int stream;
428
429 for (stream = 0; stream < 2; stream++) {
430 substream = pcm->streams[stream].substream;
431 if (!substream)
432 continue;
433
434 buf = &substream->dma_buffer;
435 if (!buf->area)
436 continue;
437
438 dma_free_writecombine(pcm->card->dev, buf->bytes,
439 buf->area, buf->addr);
440 buf->area = NULL;
441 }
442 }
443
444 struct snd_soc_platform imx_soc_platform = {
445 .name = "imx-audio",
446 };
447 EXPORT_SYMBOL_GPL(imx_soc_platform);
448
449 static struct snd_soc_dai imx_ac97_dai = {
450 .name = "AC97",
451 .ac97_control = 1,
452 .playback = {
453 .stream_name = "AC97 Playback",
454 .channels_min = 2,
455 .channels_max = 2,
456 .rates = SNDRV_PCM_RATE_48000,
457 .formats = SNDRV_PCM_FMTBIT_S16_LE,
458 },
459 .capture = {
460 .stream_name = "AC97 Capture",
461 .channels_min = 2,
462 .channels_max = 2,
463 .rates = SNDRV_PCM_RATE_48000,
464 .formats = SNDRV_PCM_FMTBIT_S16_LE,
465 },
466 .ops = &imx_ssi_pcm_dai_ops,
467 };
468
469 static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
470 {
471 void __iomem *base = imx_ssi->base;
472
473 writel(0x0, base + SSI_SCR);
474 writel(0x0, base + SSI_STCR);
475 writel(0x0, base + SSI_SRCR);
476
477 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
478
479 writel(SSI_SFCSR_RFWM0(8) |
480 SSI_SFCSR_TFWM0(8) |
481 SSI_SFCSR_RFWM1(8) |
482 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
483
484 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
485 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
486
487 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
488 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
489
490 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
491 SSI_SCR_TE | SSI_SCR_RE,
492 base + SSI_SCR);
493
494 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
495 writel(0xff, base + SSI_SACCDIS);
496 writel(0x300, base + SSI_SACCEN);
497 }
498
499 static struct imx_ssi *ac97_ssi;
500
501 static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
502 unsigned short val)
503 {
504 struct imx_ssi *imx_ssi = ac97_ssi;
505 void __iomem *base = imx_ssi->base;
506 unsigned int lreg;
507 unsigned int lval;
508
509 if (reg > 0x7f)
510 return;
511
512 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
513
514 lreg = reg << 12;
515 writel(lreg, base + SSI_SACADD);
516
517 lval = val << 4;
518 writel(lval , base + SSI_SACDAT);
519
520 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
521 udelay(100);
522 }
523
524 static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
525 unsigned short reg)
526 {
527 struct imx_ssi *imx_ssi = ac97_ssi;
528 void __iomem *base = imx_ssi->base;
529
530 unsigned short val = -1;
531 unsigned int lreg;
532
533 lreg = (reg & 0x7f) << 12 ;
534 writel(lreg, base + SSI_SACADD);
535 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
536
537 udelay(100);
538
539 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
540
541 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
542
543 return val;
544 }
545
546 static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
547 {
548 struct imx_ssi *imx_ssi = ac97_ssi;
549
550 if (imx_ssi->ac97_reset)
551 imx_ssi->ac97_reset(ac97);
552 }
553
554 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
555 {
556 struct imx_ssi *imx_ssi = ac97_ssi;
557
558 if (imx_ssi->ac97_warm_reset)
559 imx_ssi->ac97_warm_reset(ac97);
560 }
561
562 struct snd_ac97_bus_ops soc_ac97_ops = {
563 .read = imx_ssi_ac97_read,
564 .write = imx_ssi_ac97_write,
565 .reset = imx_ssi_ac97_reset,
566 .warm_reset = imx_ssi_ac97_warm_reset
567 };
568 EXPORT_SYMBOL_GPL(soc_ac97_ops);
569
570 struct snd_soc_dai imx_ssi_pcm_dai[2];
571 EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
572
573 static int imx_ssi_probe(struct platform_device *pdev)
574 {
575 struct resource *res;
576 struct imx_ssi *ssi;
577 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
578 struct snd_soc_platform *platform;
579 int ret = 0;
580 unsigned int val;
581 struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
582
583 if (dai->id >= ARRAY_SIZE(imx_ssi_pcm_dai))
584 return -EINVAL;
585
586 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
587 if (!ssi)
588 return -ENOMEM;
589
590 if (pdata) {
591 ssi->ac97_reset = pdata->ac97_reset;
592 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
593 ssi->flags = pdata->flags;
594 }
595
596 ssi->irq = platform_get_irq(pdev, 0);
597
598 ssi->clk = clk_get(&pdev->dev, NULL);
599 if (IS_ERR(ssi->clk)) {
600 ret = PTR_ERR(ssi->clk);
601 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
602 ret);
603 goto failed_clk;
604 }
605 clk_enable(ssi->clk);
606
607 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
608 if (!res) {
609 ret = -ENODEV;
610 goto failed_get_resource;
611 }
612
613 if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
614 dev_err(&pdev->dev, "request_mem_region failed\n");
615 ret = -EBUSY;
616 goto failed_get_resource;
617 }
618
619 ssi->base = ioremap(res->start, resource_size(res));
620 if (!ssi->base) {
621 dev_err(&pdev->dev, "ioremap failed\n");
622 ret = -ENODEV;
623 goto failed_ioremap;
624 }
625
626 if (ssi->flags & IMX_SSI_USE_AC97) {
627 if (ac97_ssi) {
628 ret = -EBUSY;
629 goto failed_ac97;
630 }
631 ac97_ssi = ssi;
632 setup_channel_to_ac97(ssi);
633 memcpy(dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
634 } else
635 memcpy(dai, &imx_ssi_dai, sizeof(imx_ssi_dai));
636
637 writel(0x0, ssi->base + SSI_SIER);
638
639 ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
640 ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
641
642 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
643 if (res)
644 ssi->dma_params_tx.dma = res->start;
645
646 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
647 if (res)
648 ssi->dma_params_rx.dma = res->start;
649
650 dai->id = pdev->id;
651 dai->dev = &pdev->dev;
652 dai->name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
653 dai->private_data = ssi;
654
655 if ((cpu_is_mx27() || cpu_is_mx21()) &&
656 !(ssi->flags & IMX_SSI_USE_AC97)) {
657 ssi->flags |= IMX_SSI_DMA;
658 platform = imx_ssi_dma_mx2_init(pdev, ssi);
659 } else
660 platform = imx_ssi_fiq_init(pdev, ssi);
661
662 imx_soc_platform.pcm_ops = platform->pcm_ops;
663 imx_soc_platform.pcm_new = platform->pcm_new;
664 imx_soc_platform.pcm_free = platform->pcm_free;
665
666 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
667 SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
668 writel(val, ssi->base + SSI_SFCSR);
669
670 ret = snd_soc_register_dai(dai);
671 if (ret) {
672 dev_err(&pdev->dev, "register DAI failed\n");
673 goto failed_register;
674 }
675
676 platform_set_drvdata(pdev, ssi);
677
678 return 0;
679
680 failed_register:
681 failed_ac97:
682 iounmap(ssi->base);
683 failed_ioremap:
684 release_mem_region(res->start, resource_size(res));
685 failed_get_resource:
686 clk_disable(ssi->clk);
687 clk_put(ssi->clk);
688 failed_clk:
689 kfree(ssi);
690
691 return ret;
692 }
693
694 static int __devexit imx_ssi_remove(struct platform_device *pdev)
695 {
696 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
697 struct imx_ssi *ssi = platform_get_drvdata(pdev);
698 struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
699
700 snd_soc_unregister_dai(dai);
701
702 if (ssi->flags & IMX_SSI_USE_AC97)
703 ac97_ssi = NULL;
704
705 if (!(ssi->flags & IMX_SSI_DMA))
706 imx_ssi_fiq_exit(pdev, ssi);
707
708 iounmap(ssi->base);
709 release_mem_region(res->start, resource_size(res));
710 clk_disable(ssi->clk);
711 clk_put(ssi->clk);
712 kfree(ssi);
713
714 return 0;
715 }
716
717 static struct platform_driver imx_ssi_driver = {
718 .probe = imx_ssi_probe,
719 .remove = __devexit_p(imx_ssi_remove),
720
721 .driver = {
722 .name = DRV_NAME,
723 .owner = THIS_MODULE,
724 },
725 };
726
727 static int __init imx_ssi_init(void)
728 {
729 int ret;
730
731 ret = snd_soc_register_platform(&imx_soc_platform);
732 if (ret) {
733 pr_err("failed to register soc platform: %d\n", ret);
734 return ret;
735 }
736
737 ret = platform_driver_register(&imx_ssi_driver);
738 if (ret) {
739 snd_soc_unregister_platform(&imx_soc_platform);
740 return ret;
741 }
742
743 return 0;
744 }
745
746 static void __exit imx_ssi_exit(void)
747 {
748 platform_driver_unregister(&imx_ssi_driver);
749 snd_soc_unregister_platform(&imx_soc_platform);
750 }
751
752 module_init(imx_ssi_init);
753 module_exit(imx_ssi_exit);
754
755 /* Module information */
756 MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
757 MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
758 MODULE_LICENSE("GPL");
759
linux-next