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staging:iio:ad9834: allocate chip state with iio_dev and use iio_priv to access.
[linux-2.6/next.git] / sound / soc / codecs / sgtl5000.c
blobff29380c9ed30ee5eb2eda225e505b1415de0269
1 /*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/driver.h>
21 #include <linux/regulator/machine.h>
22 #include <linux/regulator/consumer.h>
23 #include <sound/core.h>
24 #include <sound/tlv.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30
31 #include "sgtl5000.h"
32
33 #define SGTL5000_DAP_REG_OFFSET 0x0100
34 #define SGTL5000_MAX_REG_OFFSET 0x013A
35
36 /* default value of sgtl5000 registers except DAP */
37 static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = {
38 0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */
39 0x0000, /* 0x0002, CHIP_DIG_POWER. */
40 0x0008, /* 0x0004, CHIP_CKL_CTRL */
41 0x0010, /* 0x0006, CHIP_I2S_CTRL */
42 0x0000, /* 0x0008, reserved */
43 0x0008, /* 0x000A, CHIP_SSS_CTRL */
44 0x0000, /* 0x000C, reserved */
45 0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */
46 0x3c3c, /* 0x0010, CHIP_DAC_VOL */
47 0x0000, /* 0x0012, reserved */
48 0x015f, /* 0x0014, CHIP_PAD_STRENGTH */
49 0x0000, /* 0x0016, reserved */
50 0x0000, /* 0x0018, reserved */
51 0x0000, /* 0x001A, reserved */
52 0x0000, /* 0x001E, reserved */
53 0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */
54 0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */
55 0x0111, /* 0x0024, CHIP_ANN_CTRL */
56 0x0000, /* 0x0026, CHIP_LINREG_CTRL */
57 0x0000, /* 0x0028, CHIP_REF_CTRL */
58 0x0000, /* 0x002A, CHIP_MIC_CTRL */
59 0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */
60 0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */
61 0x7060, /* 0x0030, CHIP_ANA_POWER */
62 0x5000, /* 0x0032, CHIP_PLL_CTRL */
63 0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */
64 0x0000, /* 0x0036, CHIP_ANA_STATUS */
65 0x0000, /* 0x0038, reserved */
66 0x0000, /* 0x003A, CHIP_ANA_TEST2 */
67 0x0000, /* 0x003C, CHIP_SHORT_CTRL */
68 0x0000, /* reserved */
69 };
70
71 /* default value of dap registers */
72 static const u16 sgtl5000_dap_regs[] = {
73 0x0000, /* 0x0100, DAP_CONTROL */
74 0x0000, /* 0x0102, DAP_PEQ */
75 0x0040, /* 0x0104, DAP_BASS_ENHANCE */
76 0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */
77 0x0000, /* 0x0108, DAP_AUDIO_EQ */
78 0x0040, /* 0x010A, DAP_SGTL_SURROUND */
79 0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */
80 0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */
81 0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */
82 0x0000, /* 0x0112, reserved */
83 0x0000, /* 0x0114, reserved */
84 0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */
85 0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */
86 0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */
87 0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */
88 0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */
89 0x8000, /* 0x0120, DAP_MAIN_CHAN */
90 0x0000, /* 0x0122, DAP_MIX_CHAN */
91 0x0510, /* 0x0124, DAP_AVC_CTRL */
92 0x1473, /* 0x0126, DAP_AVC_THRESHOLD */
93 0x0028, /* 0x0128, DAP_AVC_ATTACK */
94 0x0050, /* 0x012A, DAP_AVC_DECAY */
95 0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */
96 0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */
97 0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */
98 0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */
99 0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */
100 0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */
101 0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */
102 0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */
103 };
104
105 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
106 enum sgtl5000_regulator_supplies {
107 VDDA,
108 VDDIO,
109 VDDD,
110 SGTL5000_SUPPLY_NUM
111 };
112
113 /* vddd is optional supply */
114 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
115 "VDDA",
116 "VDDIO",
117 "VDDD"
118 };
119
120 #define LDO_CONSUMER_NAME "VDDD_LDO"
121 #define LDO_VOLTAGE 1200000
122
123 static struct regulator_consumer_supply ldo_consumer[] = {
124 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
125 };
126
127 static struct regulator_init_data ldo_init_data = {
128 .constraints = {
129 .min_uV = 850000,
130 .max_uV = 1600000,
131 .valid_modes_mask = REGULATOR_MODE_NORMAL,
132 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
133 },
134 .num_consumer_supplies = 1,
135 .consumer_supplies = &ldo_consumer[0],
136 };
137
138 /*
139 * sgtl5000 internal ldo regulator,
140 * enabled when VDDD not provided
141 */
142 struct ldo_regulator {
143 struct regulator_desc desc;
144 struct regulator_dev *dev;
145 int voltage;
146 void *codec_data;
147 bool enabled;
148 };
149
150 /* sgtl5000 private structure in codec */
151 struct sgtl5000_priv {
152 int sysclk; /* sysclk rate */
153 int master; /* i2s master or not */
154 int fmt; /* i2s data format */
155 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
156 struct ldo_regulator *ldo;
157 };
158
159 /*
160 * mic_bias power on/off share the same register bits with
161 * output impedance of mic bias, when power on mic bias, we
162 * need reclaim it to impedance value.
163 * 0x0 = Powered off
164 * 0x1 = 2Kohm
165 * 0x2 = 4Kohm
166 * 0x3 = 8Kohm
167 */
168 static int mic_bias_event(struct snd_soc_dapm_widget *w,
169 struct snd_kcontrol *kcontrol, int event)
170 {
171 switch (event) {
172 case SND_SOC_DAPM_POST_PMU:
173 /* change mic bias resistor to 4Kohm */
174 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
175 SGTL5000_BIAS_R_4k, SGTL5000_BIAS_R_4k);
176 break;
177
178 case SND_SOC_DAPM_PRE_PMD:
179 /*
180 * SGTL5000_BIAS_R_8k as mask to clean the two bits
181 * of mic bias and output impedance
182 */
183 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
184 SGTL5000_BIAS_R_8k, 0);
185 break;
186 }
187 return 0;
188 }
189
190 /*
191 * using codec assist to small pop, hp_powerup or lineout_powerup
192 * should stay setting until vag_powerup is fully ramped down,
193 * vag fully ramped down require 400ms.
194 */
195 static int small_pop_event(struct snd_soc_dapm_widget *w,
196 struct snd_kcontrol *kcontrol, int event)
197 {
198 switch (event) {
199 case SND_SOC_DAPM_PRE_PMU:
200 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
201 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
202 break;
203
204 case SND_SOC_DAPM_PRE_PMD:
205 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
206 SGTL5000_VAG_POWERUP, 0);
207 msleep(400);
208 break;
209 default:
210 break;
211 }
212
213 return 0;
214 }
215
216 /* input sources for ADC */
217 static const char *adc_mux_text[] = {
218 "MIC_IN", "LINE_IN"
219 };
220
221 static const struct soc_enum adc_enum =
222 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
223
224 static const struct snd_kcontrol_new adc_mux =
225 SOC_DAPM_ENUM("Capture Mux", adc_enum);
226
227 /* input sources for DAC */
228 static const char *dac_mux_text[] = {
229 "DAC", "LINE_IN"
230 };
231
232 static const struct soc_enum dac_enum =
233 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
234
235 static const struct snd_kcontrol_new dac_mux =
236 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
237
238 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
239 SND_SOC_DAPM_INPUT("LINE_IN"),
240 SND_SOC_DAPM_INPUT("MIC_IN"),
241
242 SND_SOC_DAPM_OUTPUT("HP_OUT"),
243 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
244
245 SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
246 mic_bias_event,
247 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
248
249 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
250 small_pop_event,
251 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
252 SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0,
253 small_pop_event,
254 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
255
256 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
257 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
258
259 /* aif for i2s input */
260 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
261 0, SGTL5000_CHIP_DIG_POWER,
262 0, 0),
263
264 /* aif for i2s output */
265 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
266 0, SGTL5000_CHIP_DIG_POWER,
267 1, 0),
268
269 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
270
271 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
272 };
273
274 /* routes for sgtl5000 */
275 static const struct snd_soc_dapm_route audio_map[] = {
276 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
277 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
278
279 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
280 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
281
282 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
283 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
284 {"LO", NULL, "DAC"}, /* dac --> line_out */
285
286 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
287 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
288
289 {"LINE_OUT", NULL, "LO"},
290 {"HP_OUT", NULL, "HP"},
291 };
292
293 /* custom function to fetch info of PCM playback volume */
294 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
295 struct snd_ctl_elem_info *uinfo)
296 {
297 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
298 uinfo->count = 2;
299 uinfo->value.integer.min = 0;
300 uinfo->value.integer.max = 0xfc - 0x3c;
301 return 0;
302 }
303
304 /*
305 * custom function to get of PCM playback volume
306 *
307 * dac volume register
308 * 15-------------8-7--------------0
309 * | R channel vol | L channel vol |
310 * -------------------------------
311 *
312 * PCM volume with 0.5017 dB steps from 0 to -90 dB
313 *
314 * register values map to dB
315 * 0x3B and less = Reserved
316 * 0x3C = 0 dB
317 * 0x3D = -0.5 dB
318 * 0xF0 = -90 dB
319 * 0xFC and greater = Muted
320 *
321 * register value map to userspace value
322 *
323 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
324 * ------------------------------
325 * userspace value 0xc0 0
326 */
327 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
328 struct snd_ctl_elem_value *ucontrol)
329 {
330 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
331 int reg;
332 int l;
333 int r;
334
335 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
336
337 /* get left channel volume */
338 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
339
340 /* get right channel volume */
341 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
342
343 /* make sure value fall in (0x3c,0xfc) */
344 l = clamp(l, 0x3c, 0xfc);
345 r = clamp(r, 0x3c, 0xfc);
346
347 /* invert it and map to userspace value */
348 l = 0xfc - l;
349 r = 0xfc - r;
350
351 ucontrol->value.integer.value[0] = l;
352 ucontrol->value.integer.value[1] = r;
353
354 return 0;
355 }
356
357 /*
358 * custom function to put of PCM playback volume
359 *
360 * dac volume register
361 * 15-------------8-7--------------0
362 * | R channel vol | L channel vol |
363 * -------------------------------
364 *
365 * PCM volume with 0.5017 dB steps from 0 to -90 dB
366 *
367 * register values map to dB
368 * 0x3B and less = Reserved
369 * 0x3C = 0 dB
370 * 0x3D = -0.5 dB
371 * 0xF0 = -90 dB
372 * 0xFC and greater = Muted
373 *
374 * userspace value map to register value
375 *
376 * userspace value 0xc0 0
377 * ------------------------------
378 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
379 */
380 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
382 {
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
384 int reg;
385 int l;
386 int r;
387
388 l = ucontrol->value.integer.value[0];
389 r = ucontrol->value.integer.value[1];
390
391 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
392 l = clamp(l, 0, 0xfc - 0x3c);
393 r = clamp(r, 0, 0xfc - 0x3c);
394
395 /* invert it, get the value can be set to register */
396 l = 0xfc - l;
397 r = 0xfc - r;
398
399 /* shift to get the register value */
400 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
401 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
402
403 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
404
405 return 0;
406 }
407
408 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
409
410 /* tlv for mic gain, 0db 20db 30db 40db */
411 static const unsigned int mic_gain_tlv[] = {
412 TLV_DB_RANGE_HEAD(4),
413 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
414 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
415 };
416
417 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
418 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
419
420 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
421 /* SOC_DOUBLE_S8_TLV with invert */
422 {
423 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
424 .name = "PCM Playback Volume",
425 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
426 SNDRV_CTL_ELEM_ACCESS_READWRITE,
427 .info = dac_info_volsw,
428 .get = dac_get_volsw,
429 .put = dac_put_volsw,
430 },
431
432 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
433 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
434 SGTL5000_CHIP_ANA_ADC_CTRL,
435 8, 2, 0, capture_6db_attenuate),
436 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
437
438 SOC_DOUBLE_TLV("Headphone Playback Volume",
439 SGTL5000_CHIP_ANA_HP_CTRL,
440 0, 8,
441 0x7f, 1,
442 headphone_volume),
443 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
444 5, 1, 0),
445
446 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
447 0, 4, 0, mic_gain_tlv),
448 };
449
450 /* mute the codec used by alsa core */
451 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
452 {
453 struct snd_soc_codec *codec = codec_dai->codec;
454 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
455
456 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
457 adcdac_ctrl, mute ? adcdac_ctrl : 0);
458
459 return 0;
460 }
461
462 /* set codec format */
463 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
464 {
465 struct snd_soc_codec *codec = codec_dai->codec;
466 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
467 u16 i2sctl = 0;
468
469 sgtl5000->master = 0;
470 /*
471 * i2s clock and frame master setting.
472 * ONLY support:
473 * - clock and frame slave,
474 * - clock and frame master
475 */
476 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
477 case SND_SOC_DAIFMT_CBS_CFS:
478 break;
479 case SND_SOC_DAIFMT_CBM_CFM:
480 i2sctl |= SGTL5000_I2S_MASTER;
481 sgtl5000->master = 1;
482 break;
483 default:
484 return -EINVAL;
485 }
486
487 /* setting i2s data format */
488 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
489 case SND_SOC_DAIFMT_DSP_A:
490 i2sctl |= SGTL5000_I2S_MODE_PCM;
491 break;
492 case SND_SOC_DAIFMT_DSP_B:
493 i2sctl |= SGTL5000_I2S_MODE_PCM;
494 i2sctl |= SGTL5000_I2S_LRALIGN;
495 break;
496 case SND_SOC_DAIFMT_I2S:
497 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
498 break;
499 case SND_SOC_DAIFMT_RIGHT_J:
500 i2sctl |= SGTL5000_I2S_MODE_RJ;
501 i2sctl |= SGTL5000_I2S_LRPOL;
502 break;
503 case SND_SOC_DAIFMT_LEFT_J:
504 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
505 i2sctl |= SGTL5000_I2S_LRALIGN;
506 break;
507 default:
508 return -EINVAL;
509 }
510
511 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
512
513 /* Clock inversion */
514 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
515 case SND_SOC_DAIFMT_NB_NF:
516 break;
517 case SND_SOC_DAIFMT_IB_NF:
518 i2sctl |= SGTL5000_I2S_SCLK_INV;
519 break;
520 default:
521 return -EINVAL;
522 }
523
524 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
525
526 return 0;
527 }
528
529 /* set codec sysclk */
530 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
531 int clk_id, unsigned int freq, int dir)
532 {
533 struct snd_soc_codec *codec = codec_dai->codec;
534 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
535
536 switch (clk_id) {
537 case SGTL5000_SYSCLK:
538 sgtl5000->sysclk = freq;
539 break;
540 default:
541 return -EINVAL;
542 }
543
544 return 0;
545 }
546
547 /*
548 * set clock according to i2s frame clock,
549 * sgtl5000 provide 2 clock sources.
550 * 1. sys_mclk. sample freq can only configure to
551 * 1/256, 1/384, 1/512 of sys_mclk.
552 * 2. pll. can derive any audio clocks.
553 *
554 * clock setting rules:
555 * 1. in slave mode, only sys_mclk can use.
556 * 2. as constraint by sys_mclk, sample freq should
557 * set to 32k, 44.1k and above.
558 * 3. using sys_mclk prefer to pll to save power.
559 */
560 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
561 {
562 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
563 int clk_ctl = 0;
564 int sys_fs; /* sample freq */
565
566 /*
567 * sample freq should be divided by frame clock,
568 * if frame clock lower than 44.1khz, sample feq should set to
569 * 32khz or 44.1khz.
570 */
571 switch (frame_rate) {
572 case 8000:
573 case 16000:
574 sys_fs = 32000;
575 break;
576 case 11025:
577 case 22050:
578 sys_fs = 44100;
579 break;
580 default:
581 sys_fs = frame_rate;
582 break;
583 }
584
585 /* set divided factor of frame clock */
586 switch (sys_fs / frame_rate) {
587 case 4:
588 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
589 break;
590 case 2:
591 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
592 break;
593 case 1:
594 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
595 break;
596 default:
597 return -EINVAL;
598 }
599
600 /* set the sys_fs according to frame rate */
601 switch (sys_fs) {
602 case 32000:
603 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
604 break;
605 case 44100:
606 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
607 break;
608 case 48000:
609 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
610 break;
611 case 96000:
612 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
613 break;
614 default:
615 dev_err(codec->dev, "frame rate %d not supported\n",
616 frame_rate);
617 return -EINVAL;
618 }
619
620 /*
621 * calculate the divider of mclk/sample_freq,
622 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
623 */
624 switch (sgtl5000->sysclk / sys_fs) {
625 case 256:
626 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
627 SGTL5000_MCLK_FREQ_SHIFT;
628 break;
629 case 384:
630 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
631 SGTL5000_MCLK_FREQ_SHIFT;
632 break;
633 case 512:
634 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
635 SGTL5000_MCLK_FREQ_SHIFT;
636 break;
637 default:
638 /* if mclk not satisify the divider, use pll */
639 if (sgtl5000->master) {
640 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
641 SGTL5000_MCLK_FREQ_SHIFT;
642 } else {
643 dev_err(codec->dev,
644 "PLL not supported in slave mode\n");
645 return -EINVAL;
646 }
647 }
648
649 /* if using pll, please check manual 6.4.2 for detail */
650 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
651 u64 out, t;
652 int div2;
653 int pll_ctl;
654 unsigned int in, int_div, frac_div;
655
656 if (sgtl5000->sysclk > 17000000) {
657 div2 = 1;
658 in = sgtl5000->sysclk / 2;
659 } else {
660 div2 = 0;
661 in = sgtl5000->sysclk;
662 }
663 if (sys_fs == 44100)
664 out = 180633600;
665 else
666 out = 196608000;
667 t = do_div(out, in);
668 int_div = out;
669 t *= 2048;
670 do_div(t, in);
671 frac_div = t;
672 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
673 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
674
675 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
676 if (div2)
677 snd_soc_update_bits(codec,
678 SGTL5000_CHIP_CLK_TOP_CTRL,
679 SGTL5000_INPUT_FREQ_DIV2,
680 SGTL5000_INPUT_FREQ_DIV2);
681 else
682 snd_soc_update_bits(codec,
683 SGTL5000_CHIP_CLK_TOP_CTRL,
684 SGTL5000_INPUT_FREQ_DIV2,
685 0);
686
687 /* power up pll */
688 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
689 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
690 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
691 } else {
692 /* power down pll */
693 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
694 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
695 0);
696 }
697
698 /* if using pll, clk_ctrl must be set after pll power up */
699 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
700
701 return 0;
702 }
703
704 /*
705 * Set PCM DAI bit size and sample rate.
706 * input: params_rate, params_fmt
707 */
708 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
709 struct snd_pcm_hw_params *params,
710 struct snd_soc_dai *dai)
711 {
712 struct snd_soc_pcm_runtime *rtd = substream->private_data;
713 struct snd_soc_codec *codec = rtd->codec;
714 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
715 int channels = params_channels(params);
716 int i2s_ctl = 0;
717 int stereo;
718 int ret;
719
720 /* sysclk should already set */
721 if (!sgtl5000->sysclk) {
722 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
723 return -EFAULT;
724 }
725
726 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
727 stereo = SGTL5000_DAC_STEREO;
728 else
729 stereo = SGTL5000_ADC_STEREO;
730
731 /* set mono to save power */
732 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
733 channels == 1 ? 0 : stereo);
734
735 /* set codec clock base on lrclk */
736 ret = sgtl5000_set_clock(codec, params_rate(params));
737 if (ret)
738 return ret;
739
740 /* set i2s data format */
741 switch (params_format(params)) {
742 case SNDRV_PCM_FORMAT_S16_LE:
743 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
744 return -EINVAL;
745 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
746 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
747 SGTL5000_I2S_SCLKFREQ_SHIFT;
748 break;
749 case SNDRV_PCM_FORMAT_S20_3LE:
750 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
751 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
752 SGTL5000_I2S_SCLKFREQ_SHIFT;
753 break;
754 case SNDRV_PCM_FORMAT_S24_LE:
755 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
756 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
757 SGTL5000_I2S_SCLKFREQ_SHIFT;
758 break;
759 case SNDRV_PCM_FORMAT_S32_LE:
760 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
761 return -EINVAL;
762 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
763 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
764 SGTL5000_I2S_SCLKFREQ_SHIFT;
765 break;
766 default:
767 return -EINVAL;
768 }
769
770 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, i2s_ctl, i2s_ctl);
771
772 return 0;
773 }
774
775 #ifdef CONFIG_REGULATOR
776 static int ldo_regulator_is_enabled(struct regulator_dev *dev)
777 {
778 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
779
780 return ldo->enabled;
781 }
782
783 static int ldo_regulator_enable(struct regulator_dev *dev)
784 {
785 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
786 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
787 int reg;
788
789 if (ldo_regulator_is_enabled(dev))
790 return 0;
791
792 /* set regulator value firstly */
793 reg = (1600 - ldo->voltage / 1000) / 50;
794 reg = clamp(reg, 0x0, 0xf);
795
796 /* amend the voltage value, unit: uV */
797 ldo->voltage = (1600 - reg * 50) * 1000;
798
799 /* set voltage to register */
800 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
801 (0x1 << 4) - 1, reg);
802
803 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
804 SGTL5000_LINEREG_D_POWERUP,
805 SGTL5000_LINEREG_D_POWERUP);
806
807 /* when internal ldo enabled, simple digital power can be disabled */
808 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
809 SGTL5000_LINREG_SIMPLE_POWERUP,
810 0);
811
812 ldo->enabled = 1;
813 return 0;
814 }
815
816 static int ldo_regulator_disable(struct regulator_dev *dev)
817 {
818 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
819 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
820
821 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
822 SGTL5000_LINEREG_D_POWERUP,
823 0);
824
825 /* clear voltage info */
826 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
827 (0x1 << 4) - 1, 0);
828
829 ldo->enabled = 0;
830
831 return 0;
832 }
833
834 static int ldo_regulator_get_voltage(struct regulator_dev *dev)
835 {
836 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
837
838 return ldo->voltage;
839 }
840
841 static struct regulator_ops ldo_regulator_ops = {
842 .is_enabled = ldo_regulator_is_enabled,
843 .enable = ldo_regulator_enable,
844 .disable = ldo_regulator_disable,
845 .get_voltage = ldo_regulator_get_voltage,
846 };
847
848 static int ldo_regulator_register(struct snd_soc_codec *codec,
849 struct regulator_init_data *init_data,
850 int voltage)
851 {
852 struct ldo_regulator *ldo;
853
854 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
855
856 if (!ldo) {
857 dev_err(codec->dev, "failed to allocate ldo_regulator\n");
858 return -ENOMEM;
859 }
860
861 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
862 if (!ldo->desc.name) {
863 kfree(ldo);
864 dev_err(codec->dev, "failed to allocate decs name memory\n");
865 return -ENOMEM;
866 }
867
868 ldo->desc.type = REGULATOR_VOLTAGE;
869 ldo->desc.owner = THIS_MODULE;
870 ldo->desc.ops = &ldo_regulator_ops;
871 ldo->desc.n_voltages = 1;
872
873 ldo->codec_data = codec;
874 ldo->voltage = voltage;
875
876 ldo->dev = regulator_register(&ldo->desc, codec->dev,
877 init_data, ldo);
878 if (IS_ERR(ldo->dev)) {
879 int ret = PTR_ERR(ldo->dev);
880
881 dev_err(codec->dev, "failed to register regulator\n");
882 kfree(ldo->desc.name);
883 kfree(ldo);
884
885 return ret;
886 }
887
888 return 0;
889 }
890
891 static int ldo_regulator_remove(struct snd_soc_codec *codec)
892 {
893 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
894 struct ldo_regulator *ldo = sgtl5000->ldo;
895
896 if (!ldo)
897 return 0;
898
899 regulator_unregister(ldo->dev);
900 kfree(ldo->desc.name);
901 kfree(ldo);
902
903 return 0;
904 }
905 #else
906 static int ldo_regulator_register(struct snd_soc_codec *codec,
907 struct regulator_init_data *init_data,
908 int voltage)
909 {
910 return -EINVAL;
911 }
912
913 static int ldo_regulator_remove(struct snd_soc_codec *codec)
914 {
915 return 0;
916 }
917 #endif
918
919 /*
920 * set dac bias
921 * common state changes:
922 * startup:
923 * off --> standby --> prepare --> on
924 * standby --> prepare --> on
925 *
926 * stop:
927 * on --> prepare --> standby
928 */
929 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
930 enum snd_soc_bias_level level)
931 {
932 int ret;
933 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
934
935 switch (level) {
936 case SND_SOC_BIAS_ON:
937 case SND_SOC_BIAS_PREPARE:
938 break;
939 case SND_SOC_BIAS_STANDBY:
940 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
941 ret = regulator_bulk_enable(
942 ARRAY_SIZE(sgtl5000->supplies),
943 sgtl5000->supplies);
944 if (ret)
945 return ret;
946 udelay(10);
947 }
948
949 break;
950 case SND_SOC_BIAS_OFF:
951 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
952 sgtl5000->supplies);
953 break;
954 }
955
956 codec->dapm.bias_level = level;
957 return 0;
958 }
959
960 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
961 SNDRV_PCM_FMTBIT_S20_3LE |\
962 SNDRV_PCM_FMTBIT_S24_LE |\
963 SNDRV_PCM_FMTBIT_S32_LE)
964
965 static struct snd_soc_dai_ops sgtl5000_ops = {
966 .hw_params = sgtl5000_pcm_hw_params,
967 .digital_mute = sgtl5000_digital_mute,
968 .set_fmt = sgtl5000_set_dai_fmt,
969 .set_sysclk = sgtl5000_set_dai_sysclk,
970 };
971
972 static struct snd_soc_dai_driver sgtl5000_dai = {
973 .name = "sgtl5000",
974 .playback = {
975 .stream_name = "Playback",
976 .channels_min = 1,
977 .channels_max = 2,
978 /*
979 * only support 8~48K + 96K,
980 * TODO modify hw_param to support more
981 */
982 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
983 .formats = SGTL5000_FORMATS,
984 },
985 .capture = {
986 .stream_name = "Capture",
987 .channels_min = 1,
988 .channels_max = 2,
989 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
990 .formats = SGTL5000_FORMATS,
991 },
992 .ops = &sgtl5000_ops,
993 .symmetric_rates = 1,
994 };
995
996 static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
997 unsigned int reg)
998 {
999 switch (reg) {
1000 case SGTL5000_CHIP_ID:
1001 case SGTL5000_CHIP_ADCDAC_CTRL:
1002 case SGTL5000_CHIP_ANA_STATUS:
1003 return 1;
1004 }
1005
1006 return 0;
1007 }
1008
1009 #ifdef CONFIG_SUSPEND
1010 static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state)
1011 {
1012 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1013
1014 return 0;
1015 }
1016
1017 /*
1018 * restore all sgtl5000 registers,
1019 * since a big hole between dap and regular registers,
1020 * we will restore them respectively.
1021 */
1022 static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
1023 {
1024 u16 *cache = codec->reg_cache;
1025 int i;
1026 int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1;
1027
1028 /* restore regular registers */
1029 for (i = 0; i < regular_regs; i++) {
1030 int reg = i << 1;
1031
1032 /* this regs depends on the others */
1033 if (reg == SGTL5000_CHIP_ANA_POWER ||
1034 reg == SGTL5000_CHIP_CLK_CTRL ||
1035 reg == SGTL5000_CHIP_LINREG_CTRL ||
1036 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
1037 reg == SGTL5000_CHIP_CLK_CTRL)
1038 continue;
1039
1040 snd_soc_write(codec, reg, cache[i]);
1041 }
1042
1043 /* restore dap registers */
1044 for (i = SGTL5000_DAP_REG_OFFSET >> 1;
1045 i < SGTL5000_MAX_REG_OFFSET >> 1; i++) {
1046 int reg = i << 1;
1047
1048 snd_soc_write(codec, reg, cache[i]);
1049 }
1050
1051 /*
1052 * restore power and other regs according
1053 * to set_power() and set_clock()
1054 */
1055 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
1056 cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);
1057
1058 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
1059 cache[SGTL5000_CHIP_ANA_POWER >> 1]);
1060
1061 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
1062 cache[SGTL5000_CHIP_CLK_CTRL >> 1]);
1063
1064 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
1065 cache[SGTL5000_CHIP_REF_CTRL >> 1]);
1066
1067 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1068 cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]);
1069 return 0;
1070 }
1071
1072 static int sgtl5000_resume(struct snd_soc_codec *codec)
1073 {
1074 /* Bring the codec back up to standby to enable regulators */
1075 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1076
1077 /* Restore registers by cached in memory */
1078 sgtl5000_restore_regs(codec);
1079 return 0;
1080 }
1081 #else
1082 #define sgtl5000_suspend NULL
1083 #define sgtl5000_resume NULL
1084 #endif /* CONFIG_SUSPEND */
1085
1086 /*
1087 * sgtl5000 has 3 internal power supplies:
1088 * 1. VAG, normally set to vdda/2
1089 * 2. chargepump, set to different value
1090 * according to voltage of vdda and vddio
1091 * 3. line out VAG, normally set to vddio/2
1092 *
1093 * and should be set according to:
1094 * 1. vddd provided by external or not
1095 * 2. vdda and vddio voltage value. > 3.1v or not
1096 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1097 */
1098 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1099 {
1100 int vddd;
1101 int vdda;
1102 int vddio;
1103 u16 ana_pwr;
1104 u16 lreg_ctrl;
1105 int vag;
1106 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1107
1108 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1109 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1110 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1111
1112 vdda = vdda / 1000;
1113 vddio = vddio / 1000;
1114 vddd = vddd / 1000;
1115
1116 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1117 dev_err(codec->dev, "regulator voltage not set correctly\n");
1118
1119 return -EINVAL;
1120 }
1121
1122 /* according to datasheet, maximum voltage of supplies */
1123 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1124 dev_err(codec->dev,
1125 "exceed max voltage vdda %dmv vddio %dma vddd %dma\n",
1126 vdda, vddio, vddd);
1127
1128 return -EINVAL;
1129 }
1130
1131 /* reset value */
1132 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1133 ana_pwr |= SGTL5000_DAC_STEREO |
1134 SGTL5000_ADC_STEREO |
1135 SGTL5000_REFTOP_POWERUP;
1136 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1137
1138 if (vddio < 3100 && vdda < 3100) {
1139 /* enable internal oscillator used for charge pump */
1140 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1141 SGTL5000_INT_OSC_EN,
1142 SGTL5000_INT_OSC_EN);
1143 /* Enable VDDC charge pump */
1144 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1145 } else if (vddio >= 3100 && vdda >= 3100) {
1146 /*
1147 * if vddio and vddd > 3.1v,
1148 * charge pump should be clean before set ana_pwr
1149 */
1150 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1151 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1152
1153 /* VDDC use VDDIO rail */
1154 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1155 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1156 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1157 }
1158
1159 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1160
1161 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1162
1163 /* set voltage to register */
1164 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1165 (0x1 << 4) - 1, 0x8);
1166
1167 /*
1168 * if vddd linear reg has been enabled,
1169 * simple digital supply should be clear to get
1170 * proper VDDD voltage.
1171 */
1172 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1173 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1174 SGTL5000_LINREG_SIMPLE_POWERUP,
1175 0);
1176 else
1177 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1178 SGTL5000_LINREG_SIMPLE_POWERUP |
1179 SGTL5000_STARTUP_POWERUP,
1180 0);
1181
1182 /*
1183 * set ADC/DAC VAG to vdda / 2,
1184 * should stay in range (0.8v, 1.575v)
1185 */
1186 vag = vdda / 2;
1187 if (vag <= SGTL5000_ANA_GND_BASE)
1188 vag = 0;
1189 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1190 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1191 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1192 else
1193 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1194
1195 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1196 vag << SGTL5000_ANA_GND_SHIFT,
1197 vag << SGTL5000_ANA_GND_SHIFT);
1198
1199 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1200 vag = vddio / 2;
1201 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1202 vag = 0;
1203 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1204 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1205 vag = SGTL5000_LINE_OUT_GND_MAX;
1206 else
1207 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1208 SGTL5000_LINE_OUT_GND_STP;
1209
1210 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1211 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1212 SGTL5000_LINE_OUT_CURRENT_360u <<
1213 SGTL5000_LINE_OUT_CURRENT_SHIFT,
1214 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1215 SGTL5000_LINE_OUT_CURRENT_360u <<
1216 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1217
1218 return 0;
1219 }
1220
1221 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1222 {
1223 u16 reg;
1224 int ret;
1225 int rev;
1226 int i;
1227 int external_vddd = 0;
1228 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1229
1230 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1231 sgtl5000->supplies[i].supply = supply_names[i];
1232
1233 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1234 sgtl5000->supplies);
1235 if (!ret)
1236 external_vddd = 1;
1237 else {
1238 /* set internal ldo to 1.2v */
1239 int voltage = LDO_VOLTAGE;
1240
1241 ret = ldo_regulator_register(codec, &ldo_init_data, voltage);
1242 if (ret) {
1243 dev_err(codec->dev,
1244 "Failed to register vddd internal supplies: %d\n",
1245 ret);
1246 return ret;
1247 }
1248
1249 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1250
1251 ret = regulator_bulk_get(codec->dev,
1252 ARRAY_SIZE(sgtl5000->supplies),
1253 sgtl5000->supplies);
1254
1255 if (ret) {
1256 ldo_regulator_remove(codec);
1257 dev_err(codec->dev,
1258 "Failed to request supplies: %d\n", ret);
1259
1260 return ret;
1261 }
1262 }
1263
1264 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1265 sgtl5000->supplies);
1266 if (ret)
1267 goto err_regulator_free;
1268
1269 /* wait for all power rails bring up */
1270 udelay(10);
1271
1272 /* read chip information */
1273 reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
1274 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1275 SGTL5000_PARTID_PART_ID) {
1276 dev_err(codec->dev,
1277 "Device with ID register %x is not a sgtl5000\n", reg);
1278 ret = -ENODEV;
1279 goto err_regulator_disable;
1280 }
1281
1282 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1283 dev_info(codec->dev, "sgtl5000 revision %d\n", rev);
1284
1285 /*
1286 * workaround for revision 0x11 and later,
1287 * roll back to use internal LDO
1288 */
1289 if (external_vddd && rev >= 0x11) {
1290 int voltage = LDO_VOLTAGE;
1291 /* disable all regulator first */
1292 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1293 sgtl5000->supplies);
1294 /* free VDDD regulator */
1295 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1296 sgtl5000->supplies);
1297
1298 ret = ldo_regulator_register(codec, &ldo_init_data, voltage);
1299 if (ret)
1300 return ret;
1301
1302 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1303
1304 ret = regulator_bulk_get(codec->dev,
1305 ARRAY_SIZE(sgtl5000->supplies),
1306 sgtl5000->supplies);
1307 if (ret) {
1308 ldo_regulator_remove(codec);
1309 dev_err(codec->dev,
1310 "Failed to request supplies: %d\n", ret);
1311
1312 return ret;
1313 }
1314
1315 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1316 sgtl5000->supplies);
1317 if (ret)
1318 goto err_regulator_free;
1319
1320 /* wait for all power rails bring up */
1321 udelay(10);
1322 }
1323
1324 return 0;
1325
1326 err_regulator_disable:
1327 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1328 sgtl5000->supplies);
1329 err_regulator_free:
1330 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1331 sgtl5000->supplies);
1332 if (external_vddd)
1333 ldo_regulator_remove(codec);
1334 return ret;
1335
1336 }
1337
1338 static int sgtl5000_probe(struct snd_soc_codec *codec)
1339 {
1340 int ret;
1341 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1342
1343 /* setup i2c data ops */
1344 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
1345 if (ret < 0) {
1346 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1347 return ret;
1348 }
1349
1350 ret = sgtl5000_enable_regulators(codec);
1351 if (ret)
1352 return ret;
1353
1354 /* power up sgtl5000 */
1355 ret = sgtl5000_set_power_regs(codec);
1356 if (ret)
1357 goto err;
1358
1359 /* enable small pop, introduce 400ms delay in turning off */
1360 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1361 SGTL5000_SMALL_POP,
1362 SGTL5000_SMALL_POP);
1363
1364 /* disable short cut detector */
1365 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1366
1367 /*
1368 * set i2s as default input of sound switch
1369 * TODO: add sound switch to control and dapm widge.
1370 */
1371 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1372 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1373 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1374 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1375
1376 /* enable dac volume ramp by default */
1377 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1378 SGTL5000_DAC_VOL_RAMP_EN |
1379 SGTL5000_DAC_MUTE_RIGHT |
1380 SGTL5000_DAC_MUTE_LEFT);
1381
1382 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1383
1384 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1385 SGTL5000_HP_ZCD_EN |
1386 SGTL5000_ADC_ZCD_EN);
1387
1388 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
1389
1390 /*
1391 * disable DAP
1392 * TODO:
1393 * Enable DAP in kcontrol and dapm.
1394 */
1395 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1396
1397 /* leading to standby state */
1398 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1399 if (ret)
1400 goto err;
1401
1402 snd_soc_add_controls(codec, sgtl5000_snd_controls,
1403 ARRAY_SIZE(sgtl5000_snd_controls));
1404
1405 snd_soc_dapm_new_controls(&codec->dapm, sgtl5000_dapm_widgets,
1406 ARRAY_SIZE(sgtl5000_dapm_widgets));
1407
1408 snd_soc_dapm_add_routes(&codec->dapm, audio_map,
1409 ARRAY_SIZE(audio_map));
1410
1411 snd_soc_dapm_new_widgets(&codec->dapm);
1412
1413 return 0;
1414
1415 err:
1416 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1417 sgtl5000->supplies);
1418 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1419 sgtl5000->supplies);
1420 ldo_regulator_remove(codec);
1421
1422 return ret;
1423 }
1424
1425 static int sgtl5000_remove(struct snd_soc_codec *codec)
1426 {
1427 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1428
1429 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1430
1431 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1432 sgtl5000->supplies);
1433 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1434 sgtl5000->supplies);
1435 ldo_regulator_remove(codec);
1436
1437 return 0;
1438 }
1439
1440 static struct snd_soc_codec_driver sgtl5000_driver = {
1441 .probe = sgtl5000_probe,
1442 .remove = sgtl5000_remove,
1443 .suspend = sgtl5000_suspend,
1444 .resume = sgtl5000_resume,
1445 .set_bias_level = sgtl5000_set_bias_level,
1446 .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
1447 .reg_word_size = sizeof(u16),
1448 .reg_cache_step = 2,
1449 .reg_cache_default = sgtl5000_regs,
1450 .volatile_register = sgtl5000_volatile_register,
1451 };
1452
1453 static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
1454 const struct i2c_device_id *id)
1455 {
1456 struct sgtl5000_priv *sgtl5000;
1457 int ret;
1458
1459 sgtl5000 = kzalloc(sizeof(struct sgtl5000_priv), GFP_KERNEL);
1460 if (!sgtl5000)
1461 return -ENOMEM;
1462
1463 /*
1464 * copy DAP default values to default value array.
1465 * sgtl5000 register space has a big hole, merge it
1466 * at init phase makes life easy.
1467 * FIXME: should we drop 'const' of sgtl5000_regs?
1468 */
1469 memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)),
1470 sgtl5000_dap_regs,
1471 SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET);
1472
1473 i2c_set_clientdata(client, sgtl5000);
1474
1475 ret = snd_soc_register_codec(&client->dev,
1476 &sgtl5000_driver, &sgtl5000_dai, 1);
1477 if (ret) {
1478 dev_err(&client->dev, "Failed to register codec: %d\n", ret);
1479 kfree(sgtl5000);
1480 return ret;
1481 }
1482
1483 return 0;
1484 }
1485
1486 static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
1487 {
1488 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1489
1490 snd_soc_unregister_codec(&client->dev);
1491
1492 kfree(sgtl5000);
1493 return 0;
1494 }
1495
1496 static const struct i2c_device_id sgtl5000_id[] = {
1497 {"sgtl5000", 0},
1498 {},
1499 };
1500
1501 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1502
1503 static struct i2c_driver sgtl5000_i2c_driver = {
1504 .driver = {
1505 .name = "sgtl5000",
1506 .owner = THIS_MODULE,
1507 },
1508 .probe = sgtl5000_i2c_probe,
1509 .remove = __devexit_p(sgtl5000_i2c_remove),
1510 .id_table = sgtl5000_id,
1511 };
1512
1513 static int __init sgtl5000_modinit(void)
1514 {
1515 return i2c_add_driver(&sgtl5000_i2c_driver);
1516 }
1517 module_init(sgtl5000_modinit);
1518
1519 static void __exit sgtl5000_exit(void)
1520 {
1521 i2c_del_driver(&sgtl5000_i2c_driver);
1522 }
1523 module_exit(sgtl5000_exit);
1524
1525 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1526 MODULE_AUTHOR("Zeng Zhaoming <zhaoming.zeng@freescale.com>");
1527 MODULE_LICENSE("GPL");
linux-next