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tifm: fix the MemoryStick host fifo handling code
[linux-2.6/next.git] / arch / ppc / syslib / mv64360_pic.c
blob2dd2dc5cd4045b2f82eee1cee9e74c9823225943
1 /*
2 * Interrupt controller support for Marvell's MV64360.
3 *
4 * Author: Rabeeh Khoury <rabeeh@galileo.co.il>
5 * Based on MV64360 PIC written by
6 * Chris Zankel <chris@mvista.com>
7 * Mark A. Greer <mgreer@mvista.com>
8 *
9 * Copyright 2004 MontaVista Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17 /*
18 * This file contains the specific functions to support the MV64360
19 * interrupt controller.
20 *
21 * The MV64360 has two main interrupt registers (high and low) that
22 * summarizes the interrupts generated by the units of the MV64360.
23 * Each bit is assigned to an interrupt number, where the low register
24 * are assigned from IRQ0 to IRQ31 and the high cause register
25 * from IRQ32 to IRQ63
26 * The GPP (General Purpose Pins) interrupts are assigned from IRQ64 (GPP0)
27 * to IRQ95 (GPP31).
28 * get_irq() returns the lowest interrupt number that is currently asserted.
29 *
30 * Note:
31 * - This driver does not initialize the GPP when used as an interrupt
32 * input.
33 */
34
35 #include <linux/stddef.h>
36 #include <linux/init.h>
37 #include <linux/sched.h>
38 #include <linux/signal.h>
39 #include <linux/delay.h>
40 #include <linux/irq.h>
41 #include <linux/interrupt.h>
42
43 #include <asm/io.h>
44 #include <asm/processor.h>
45 #include <asm/system.h>
46 #include <asm/irq.h>
47 #include <asm/mv64x60.h>
48 #include <asm/machdep.h>
49
50 #ifdef CONFIG_IRQ_ALL_CPUS
51 #error "The mv64360 does not support distribution of IRQs on all CPUs"
52 #endif
53 /* ========================== forward declaration ========================== */
54
55 static void mv64360_unmask_irq(unsigned int);
56 static void mv64360_mask_irq(unsigned int);
57 static irqreturn_t mv64360_cpu_error_int_handler(int, void *);
58 static irqreturn_t mv64360_sram_error_int_handler(int, void *);
59 static irqreturn_t mv64360_pci_error_int_handler(int, void *);
60
61 /* ========================== local declarations =========================== */
62
63 struct hw_interrupt_type mv64360_pic = {
64 .typename = " mv64360 ",
65 .enable = mv64360_unmask_irq,
66 .disable = mv64360_mask_irq,
67 .ack = mv64360_mask_irq,
68 .end = mv64360_unmask_irq,
69 };
70
71 #define CPU_INTR_STR "mv64360 cpu interface error"
72 #define SRAM_INTR_STR "mv64360 internal sram error"
73 #define PCI0_INTR_STR "mv64360 pci 0 error"
74 #define PCI1_INTR_STR "mv64360 pci 1 error"
75
76 static struct mv64x60_handle bh;
77
78 u32 mv64360_irq_base = 0; /* MV64360 handles the next 96 IRQs from here */
79
80 /* mv64360_init_irq()
81 *
82 * This function initializes the interrupt controller. It assigns
83 * all interrupts from IRQ0 to IRQ95 to the mv64360 interrupt controller.
84 *
85 * Input Variable(s):
86 * None.
87 *
88 * Outpu. Variable(s):
89 * None.
90 *
91 * Returns:
92 * void
93 *
94 * Note:
95 * We register all GPP inputs as interrupt source, but disable them.
96 */
97 void __init
98 mv64360_init_irq(void)
99 {
100 int i;
101
102 if (ppc_md.progress)
103 ppc_md.progress("mv64360_init_irq: enter", 0x0);
104
105 bh.v_base = mv64x60_get_bridge_vbase();
106
107 ppc_cached_irq_mask[0] = 0;
108 ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
109 ppc_cached_irq_mask[2] = 0;
110
111 /* disable all interrupts and clear current interrupts */
112 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0);
113 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
114 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,ppc_cached_irq_mask[0]);
115 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,ppc_cached_irq_mask[1]);
116
117 /* All interrupts are level interrupts */
118 for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) {
119 irq_desc[i].status |= IRQ_LEVEL;
120 irq_desc[i].chip = &mv64360_pic;
121 }
122
123 if (ppc_md.progress)
124 ppc_md.progress("mv64360_init_irq: exit", 0x0);
125 }
126
127 /* mv64360_get_irq()
128 *
129 * This function returns the lowest interrupt number of all interrupts that
130 * are currently asserted.
131 *
132 * Output Variable(s):
133 * None.
134 *
135 * Returns:
136 * int <interrupt number> or -2 (bogus interrupt)
137 *
138 */
139 int
140 mv64360_get_irq(void)
141 {
142 int irq;
143 int irq_gpp;
144
145 #ifdef CONFIG_SMP
146 /*
147 * Second CPU gets only doorbell (message) interrupts.
148 * The doorbell interrupt is BIT28 in the main interrupt low cause reg.
149 */
150 int cpu_nr = smp_processor_id();
151 if (cpu_nr == 1) {
152 if (!(mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO) &
153 (1 << MV64x60_IRQ_DOORBELL)))
154 return -1;
155 return mv64360_irq_base + MV64x60_IRQ_DOORBELL;
156 }
157 #endif
158
159 irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO);
160 irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
161
162 if (irq == -1) {
163 irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI);
164 irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
165
166 if (irq == -1)
167 irq = -2; /* bogus interrupt, should never happen */
168 else {
169 if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) {
170 irq_gpp = mv64x60_read(&bh,
171 MV64x60_GPP_INTR_CAUSE);
172 irq_gpp = __ilog2(irq_gpp &
173 ppc_cached_irq_mask[2]);
174
175 if (irq_gpp == -1)
176 irq = -2;
177 else {
178 irq = irq_gpp + 64;
179 mv64x60_write(&bh,
180 MV64x60_GPP_INTR_CAUSE,
181 ~(1 << (irq - 64)));
182 }
183 }
184 else
185 irq += 32;
186 }
187 }
188
189 (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
190
191 if (irq < 0)
192 return (irq);
193 else
194 return (mv64360_irq_base + irq);
195 }
196
197 /* mv64360_unmask_irq()
198 *
199 * This function enables an interrupt.
200 *
201 * Input Variable(s):
202 * unsigned int interrupt number (IRQ0...IRQ95).
203 *
204 * Output Variable(s):
205 * None.
206 *
207 * Returns:
208 * void
209 */
210 static void
211 mv64360_unmask_irq(unsigned int irq)
212 {
213 #ifdef CONFIG_SMP
214 /* second CPU gets only doorbell interrupts */
215 if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) {
216 mv64x60_set_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO,
217 (1 << MV64x60_IRQ_DOORBELL));
218 return;
219 }
220 #endif
221 irq -= mv64360_irq_base;
222
223 if (irq > 31) {
224 if (irq > 63) /* unmask GPP irq */
225 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
226 ppc_cached_irq_mask[2] |= (1 << (irq - 64)));
227 else /* mask high interrupt register */
228 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,
229 ppc_cached_irq_mask[1] |= (1 << (irq - 32)));
230 }
231 else /* mask low interrupt register */
232 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,
233 ppc_cached_irq_mask[0] |= (1 << irq));
234
235 (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
236 return;
237 }
238
239 /* mv64360_mask_irq()
240 *
241 * This function disables the requested interrupt.
242 *
243 * Input Variable(s):
244 * unsigned int interrupt number (IRQ0...IRQ95).
245 *
246 * Output Variable(s):
247 * None.
248 *
249 * Returns:
250 * void
251 */
252 static void
253 mv64360_mask_irq(unsigned int irq)
254 {
255 #ifdef CONFIG_SMP
256 if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) {
257 mv64x60_clr_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO,
258 (1 << MV64x60_IRQ_DOORBELL));
259 return;
260 }
261 #endif
262 irq -= mv64360_irq_base;
263
264 if (irq > 31) {
265 if (irq > 63) /* mask GPP irq */
266 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
267 ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
268 else /* mask high interrupt register */
269 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,
270 ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
271 }
272 else /* mask low interrupt register */
273 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,
274 ppc_cached_irq_mask[0] &= ~(1 << irq));
275
276 (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
277 return;
278 }
279
280 static irqreturn_t
281 mv64360_cpu_error_int_handler(int irq, void *dev_id)
282 {
283 printk(KERN_ERR "mv64360_cpu_error_int_handler: %s 0x%08x\n",
284 "Error on CPU interface - Cause regiser",
285 mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
286 printk(KERN_ERR "\tCPU error register dump:\n");
287 printk(KERN_ERR "\tAddress low 0x%08x\n",
288 mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
289 printk(KERN_ERR "\tAddress high 0x%08x\n",
290 mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
291 printk(KERN_ERR "\tData low 0x%08x\n",
292 mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
293 printk(KERN_ERR "\tData high 0x%08x\n",
294 mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
295 printk(KERN_ERR "\tParity 0x%08x\n",
296 mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
297 mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
298 return IRQ_HANDLED;
299 }
300
301 static irqreturn_t
302 mv64360_sram_error_int_handler(int irq, void *dev_id)
303 {
304 printk(KERN_ERR "mv64360_sram_error_int_handler: %s 0x%08x\n",
305 "Error in internal SRAM - Cause register",
306 mv64x60_read(&bh, MV64360_SRAM_ERR_CAUSE));
307 printk(KERN_ERR "\tSRAM error register dump:\n");
308 printk(KERN_ERR "\tAddress Low 0x%08x\n",
309 mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_LO));
310 printk(KERN_ERR "\tAddress High 0x%08x\n",
311 mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_HI));
312 printk(KERN_ERR "\tData Low 0x%08x\n",
313 mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_LO));
314 printk(KERN_ERR "\tData High 0x%08x\n",
315 mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_HI));
316 printk(KERN_ERR "\tParity 0x%08x\n",
317 mv64x60_read(&bh, MV64360_SRAM_ERR_PARITY));
318 mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
319 return IRQ_HANDLED;
320 }
321
322 static irqreturn_t
323 mv64360_pci_error_int_handler(int irq, void *dev_id)
324 {
325 u32 val;
326 unsigned int pci_bus = (unsigned int)dev_id;
327
328 if (pci_bus == 0) { /* Error on PCI 0 */
329 val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
330 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
331 "mv64360_pci_error_int_handler", pci_bus);
332 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
333 printk(KERN_ERR "\tCause register 0x%08x\n", val);
334 printk(KERN_ERR "\tAddress Low 0x%08x\n",
335 mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
336 printk(KERN_ERR "\tAddress High 0x%08x\n",
337 mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
338 printk(KERN_ERR "\tAttribute 0x%08x\n",
339 mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
340 printk(KERN_ERR "\tCommand 0x%08x\n",
341 mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
342 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);
343 }
344 if (pci_bus == 1) { /* Error on PCI 1 */
345 val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE);
346 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
347 "mv64360_pci_error_int_handler", pci_bus);
348 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
349 printk(KERN_ERR "\tCause register 0x%08x\n", val);
350 printk(KERN_ERR "\tAddress Low 0x%08x\n",
351 mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO));
352 printk(KERN_ERR "\tAddress High 0x%08x\n",
353 mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI));
354 printk(KERN_ERR "\tAttribute 0x%08x\n",
355 mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO));
356 printk(KERN_ERR "\tCommand 0x%08x\n",
357 mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD));
358 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val);
359 }
360 return IRQ_HANDLED;
361 }
362
363 /*
364 * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
365 * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
366 * well. IOW, don't set bit 0.
367 */
368 #define MV64360_PCI0_ERR_MASK_VAL 0x00a50c24
369
370 static int __init
371 mv64360_register_hdlrs(void)
372 {
373 int rc;
374
375 /* Clear old errors and register CPU interface error intr handler */
376 mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
377 if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base,
378 mv64360_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, NULL)))
379 printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
380
381 mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
382 mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff);
383
384 /* Clear old errors and register internal SRAM error intr handler */
385 mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
386 if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base,
387 mv64360_sram_error_int_handler,IRQF_DISABLED,SRAM_INTR_STR, NULL)))
388 printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
389
390 /* Clear old errors and register PCI 0 error intr handler */
391 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0);
392 if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base,
393 mv64360_pci_error_int_handler,
394 IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
395 printk(KERN_WARNING "Can't register pci 0 error handler: %d",
396 rc);
397
398 mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
399 mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
400
401 /* Erratum FEr PCI-#16 says to clear bit 0 of PCI SERRn Mask reg. */
402 mv64x60_write(&bh, MV64x60_PCI0_ERR_SERR_MASK,
403 mv64x60_read(&bh, MV64x60_PCI0_ERR_SERR_MASK) & ~0x1UL);
404
405 /* Clear old errors and register PCI 1 error intr handler */
406 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0);
407 if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base,
408 mv64360_pci_error_int_handler,
409 IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
410 printk(KERN_WARNING "Can't register pci 1 error handler: %d",
411 rc);
412
413 mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
414 mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
415
416 /* Erratum FEr PCI-#16 says to clear bit 0 of PCI Intr Mask reg. */
417 mv64x60_write(&bh, MV64x60_PCI1_ERR_SERR_MASK,
418 mv64x60_read(&bh, MV64x60_PCI1_ERR_SERR_MASK) & ~0x1UL);
419
420 return 0;
421 }
422
423 arch_initcall(mv64360_register_hdlrs);
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