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Documentation/iostats.txt: bit-size reference etc.
[linux-2.6/next.git] / arch / arm / mach-omap2 / mailbox.c
blob0a585dfa9874327406bf37bfa6e3ef85573e0feb
1 /*
2 * Mailbox reservation modules for OMAP2/3
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/err.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <plat/mailbox.h>
18 #include <mach/irqs.h>
19
20 #define MAILBOX_REVISION 0x000
21 #define MAILBOX_SYSCONFIG 0x010
22 #define MAILBOX_SYSSTATUS 0x014
23 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
24 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
25 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
26 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
27 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
28
29 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
30 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
31 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
32
33 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
34 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
35
36 /* SYSCONFIG: register bit definition */
37 #define AUTOIDLE (1 << 0)
38 #define SOFTRESET (1 << 1)
39 #define SMARTIDLE (2 << 3)
40 #define OMAP4_SOFTRESET (1 << 0)
41 #define OMAP4_NOIDLE (1 << 2)
42 #define OMAP4_SMARTIDLE (2 << 2)
43
44 /* SYSSTATUS: register bit definition */
45 #define RESETDONE (1 << 0)
46
47 #define MBOX_REG_SIZE 0x120
48
49 #define OMAP4_MBOX_REG_SIZE 0x130
50
51 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
52 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
53
54 static void __iomem *mbox_base;
55
56 struct omap_mbox2_fifo {
57 unsigned long msg;
58 unsigned long fifo_stat;
59 unsigned long msg_stat;
60 };
61
62 struct omap_mbox2_priv {
63 struct omap_mbox2_fifo tx_fifo;
64 struct omap_mbox2_fifo rx_fifo;
65 unsigned long irqenable;
66 unsigned long irqstatus;
67 u32 newmsg_bit;
68 u32 notfull_bit;
69 u32 ctx[OMAP4_MBOX_NR_REGS];
70 unsigned long irqdisable;
71 };
72
73 static struct clk *mbox_ick_handle;
74
75 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
76 omap_mbox_type_t irq);
77
78 static inline unsigned int mbox_read_reg(size_t ofs)
79 {
80 return __raw_readl(mbox_base + ofs);
81 }
82
83 static inline void mbox_write_reg(u32 val, size_t ofs)
84 {
85 __raw_writel(val, mbox_base + ofs);
86 }
87
88 /* Mailbox H/W preparations */
89 static int omap2_mbox_startup(struct omap_mbox *mbox)
90 {
91 u32 l;
92 unsigned long timeout;
93
94 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
95 if (IS_ERR(mbox_ick_handle)) {
96 printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
97 PTR_ERR(mbox_ick_handle));
98 return PTR_ERR(mbox_ick_handle);
99 }
100 clk_enable(mbox_ick_handle);
101
102 if (cpu_is_omap44xx()) {
103 mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
104 timeout = jiffies + msecs_to_jiffies(20);
105 do {
106 l = mbox_read_reg(MAILBOX_SYSCONFIG);
107 if (!(l & OMAP4_SOFTRESET))
108 break;
109 } while (!time_after(jiffies, timeout));
110
111 if (l & OMAP4_SOFTRESET) {
112 pr_err("Can't take mailbox out of reset\n");
113 return -ENODEV;
114 }
115 } else {
116 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
117 timeout = jiffies + msecs_to_jiffies(20);
118 do {
119 l = mbox_read_reg(MAILBOX_SYSSTATUS);
120 if (l & RESETDONE)
121 break;
122 } while (!time_after(jiffies, timeout));
123
124 if (!(l & RESETDONE)) {
125 pr_err("Can't take mailbox out of reset\n");
126 return -ENODEV;
127 }
128 }
129
130 l = mbox_read_reg(MAILBOX_REVISION);
131 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
132
133 if (cpu_is_omap44xx())
134 l = OMAP4_SMARTIDLE;
135 else
136 l = SMARTIDLE | AUTOIDLE;
137 mbox_write_reg(l, MAILBOX_SYSCONFIG);
138
139 omap2_mbox_enable_irq(mbox, IRQ_RX);
140
141 return 0;
142 }
143
144 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
145 {
146 clk_disable(mbox_ick_handle);
147 clk_put(mbox_ick_handle);
148 mbox_ick_handle = NULL;
149 }
150
151 /* Mailbox FIFO handle functions */
152 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
153 {
154 struct omap_mbox2_fifo *fifo =
155 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
156 return (mbox_msg_t) mbox_read_reg(fifo->msg);
157 }
158
159 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
160 {
161 struct omap_mbox2_fifo *fifo =
162 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
163 mbox_write_reg(msg, fifo->msg);
164 }
165
166 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
167 {
168 struct omap_mbox2_fifo *fifo =
169 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
170 return (mbox_read_reg(fifo->msg_stat) == 0);
171 }
172
173 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
174 {
175 struct omap_mbox2_fifo *fifo =
176 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
177 return mbox_read_reg(fifo->fifo_stat);
178 }
179
180 /* Mailbox IRQ handle functions */
181 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
182 omap_mbox_type_t irq)
183 {
184 struct omap_mbox2_priv *p = mbox->priv;
185 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
186
187 l = mbox_read_reg(p->irqenable);
188 l |= bit;
189 mbox_write_reg(l, p->irqenable);
190 }
191
192 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
193 omap_mbox_type_t irq)
194 {
195 struct omap_mbox2_priv *p = mbox->priv;
196 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
197 l = mbox_read_reg(p->irqdisable);
198 l &= ~bit;
199 mbox_write_reg(l, p->irqdisable);
200 }
201
202 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
203 omap_mbox_type_t irq)
204 {
205 struct omap_mbox2_priv *p = mbox->priv;
206 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
207
208 mbox_write_reg(bit, p->irqstatus);
209
210 /* Flush posted write for irq status to avoid spurious interrupts */
211 mbox_read_reg(p->irqstatus);
212 }
213
214 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
215 omap_mbox_type_t irq)
216 {
217 struct omap_mbox2_priv *p = mbox->priv;
218 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
219 u32 enable = mbox_read_reg(p->irqenable);
220 u32 status = mbox_read_reg(p->irqstatus);
221
222 return (int)(enable & status & bit);
223 }
224
225 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
226 {
227 int i;
228 struct omap_mbox2_priv *p = mbox->priv;
229 int nr_regs;
230 if (cpu_is_omap44xx())
231 nr_regs = OMAP4_MBOX_NR_REGS;
232 else
233 nr_regs = MBOX_NR_REGS;
234 for (i = 0; i < nr_regs; i++) {
235 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
236
237 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
238 i, p->ctx[i]);
239 }
240 }
241
242 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
243 {
244 int i;
245 struct omap_mbox2_priv *p = mbox->priv;
246 int nr_regs;
247 if (cpu_is_omap44xx())
248 nr_regs = OMAP4_MBOX_NR_REGS;
249 else
250 nr_regs = MBOX_NR_REGS;
251 for (i = 0; i < nr_regs; i++) {
252 mbox_write_reg(p->ctx[i], i * sizeof(u32));
253
254 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
255 i, p->ctx[i]);
256 }
257 }
258
259 static struct omap_mbox_ops omap2_mbox_ops = {
260 .type = OMAP_MBOX_TYPE2,
261 .startup = omap2_mbox_startup,
262 .shutdown = omap2_mbox_shutdown,
263 .fifo_read = omap2_mbox_fifo_read,
264 .fifo_write = omap2_mbox_fifo_write,
265 .fifo_empty = omap2_mbox_fifo_empty,
266 .fifo_full = omap2_mbox_fifo_full,
267 .enable_irq = omap2_mbox_enable_irq,
268 .disable_irq = omap2_mbox_disable_irq,
269 .ack_irq = omap2_mbox_ack_irq,
270 .is_irq = omap2_mbox_is_irq,
271 .save_ctx = omap2_mbox_save_ctx,
272 .restore_ctx = omap2_mbox_restore_ctx,
273 };
274
275 /*
276 * MAILBOX 0: ARM -> DSP,
277 * MAILBOX 1: ARM <- DSP.
278 * MAILBOX 2: ARM -> IVA,
279 * MAILBOX 3: ARM <- IVA.
280 */
281
282 /* FIXME: the following structs should be filled automatically by the user id */
283
284 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
285 /* DSP */
286 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
287 .tx_fifo = {
288 .msg = MAILBOX_MESSAGE(0),
289 .fifo_stat = MAILBOX_FIFOSTATUS(0),
290 },
291 .rx_fifo = {
292 .msg = MAILBOX_MESSAGE(1),
293 .msg_stat = MAILBOX_MSGSTATUS(1),
294 },
295 .irqenable = MAILBOX_IRQENABLE(0),
296 .irqstatus = MAILBOX_IRQSTATUS(0),
297 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
298 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
299 .irqdisable = MAILBOX_IRQENABLE(0),
300 };
301
302 struct omap_mbox mbox_dsp_info = {
303 .name = "dsp",
304 .ops = &omap2_mbox_ops,
305 .priv = &omap2_mbox_dsp_priv,
306 };
307 #endif
308
309 #if defined(CONFIG_ARCH_OMAP3)
310 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
311 #endif
312
313 #if defined(CONFIG_ARCH_OMAP2420)
314 /* IVA */
315 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
316 .tx_fifo = {
317 .msg = MAILBOX_MESSAGE(2),
318 .fifo_stat = MAILBOX_FIFOSTATUS(2),
319 },
320 .rx_fifo = {
321 .msg = MAILBOX_MESSAGE(3),
322 .msg_stat = MAILBOX_MSGSTATUS(3),
323 },
324 .irqenable = MAILBOX_IRQENABLE(3),
325 .irqstatus = MAILBOX_IRQSTATUS(3),
326 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
327 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
328 .irqdisable = MAILBOX_IRQENABLE(3),
329 };
330
331 static struct omap_mbox mbox_iva_info = {
332 .name = "iva",
333 .ops = &omap2_mbox_ops,
334 .priv = &omap2_mbox_iva_priv,
335 };
336
337 struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
338 #endif
339
340 #if defined(CONFIG_ARCH_OMAP4)
341 /* OMAP4 */
342 static struct omap_mbox2_priv omap2_mbox_1_priv = {
343 .tx_fifo = {
344 .msg = MAILBOX_MESSAGE(0),
345 .fifo_stat = MAILBOX_FIFOSTATUS(0),
346 },
347 .rx_fifo = {
348 .msg = MAILBOX_MESSAGE(1),
349 .msg_stat = MAILBOX_MSGSTATUS(1),
350 },
351 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
352 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
353 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
354 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
355 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
356 };
357
358 struct omap_mbox mbox_1_info = {
359 .name = "mailbox-1",
360 .ops = &omap2_mbox_ops,
361 .priv = &omap2_mbox_1_priv,
362 };
363
364 static struct omap_mbox2_priv omap2_mbox_2_priv = {
365 .tx_fifo = {
366 .msg = MAILBOX_MESSAGE(3),
367 .fifo_stat = MAILBOX_FIFOSTATUS(3),
368 },
369 .rx_fifo = {
370 .msg = MAILBOX_MESSAGE(2),
371 .msg_stat = MAILBOX_MSGSTATUS(2),
372 },
373 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
374 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
375 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
376 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
377 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
378 };
379
380 struct omap_mbox mbox_2_info = {
381 .name = "mailbox-2",
382 .ops = &omap2_mbox_ops,
383 .priv = &omap2_mbox_2_priv,
384 };
385
386 struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
387 #endif
388
389 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
390 {
391 struct resource *mem;
392 int ret;
393 struct omap_mbox **list;
394
395 if (false)
396 ;
397 #if defined(CONFIG_ARCH_OMAP3)
398 else if (cpu_is_omap34xx()) {
399 list = omap3_mboxes;
400
401 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
402 }
403 #endif
404 #if defined(CONFIG_ARCH_OMAP2)
405 else if (cpu_is_omap2430()) {
406 list = omap2_mboxes;
407
408 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
409 } else if (cpu_is_omap2420()) {
410 list = omap2_mboxes;
411
412 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
413 list[1]->irq = platform_get_irq_byname(pdev, "iva");
414 }
415 #endif
416 #if defined(CONFIG_ARCH_OMAP4)
417 else if (cpu_is_omap44xx()) {
418 list = omap4_mboxes;
419
420 list[0]->irq = list[1]->irq =
421 platform_get_irq_byname(pdev, "mbox");
422 }
423 #endif
424 else {
425 pr_err("%s: platform not supported\n", __func__);
426 return -ENODEV;
427 }
428
429 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430 mbox_base = ioremap(mem->start, resource_size(mem));
431 if (!mbox_base)
432 return -ENOMEM;
433
434 ret = omap_mbox_register(&pdev->dev, list);
435 if (ret) {
436 iounmap(mbox_base);
437 return ret;
438 }
439
440 return 0;
441 }
442
443 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
444 {
445 omap_mbox_unregister();
446 iounmap(mbox_base);
447 return 0;
448 }
449
450 static struct platform_driver omap2_mbox_driver = {
451 .probe = omap2_mbox_probe,
452 .remove = __devexit_p(omap2_mbox_remove),
453 .driver = {
454 .name = "omap-mailbox",
455 },
456 };
457
458 static int __init omap2_mbox_init(void)
459 {
460 return platform_driver_register(&omap2_mbox_driver);
461 }
462
463 static void __exit omap2_mbox_exit(void)
464 {
465 platform_driver_unregister(&omap2_mbox_driver);
466 }
467
468 module_init(omap2_mbox_init);
469 module_exit(omap2_mbox_exit);
470
471 MODULE_LICENSE("GPL v2");
472 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
473 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
474 MODULE_AUTHOR("Paul Mundt");
475 MODULE_ALIAS("platform:omap2-mailbox");
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