arch/arm/plat-omap/include/plat/clock.h

   1 /*
   2  * OMAP clock: data structure definitions, function prototypes, shared macros
   3  *
   4  * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
   5  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
  14 #define __ARCH_ARM_OMAP_CLOCK_H
  15
  16 #include <linux/list.h>
  17
  18 struct module;
  19 struct clk;
  20 struct clockdomain;
  21
  22 /**
  23  * struct clkops - some clock function pointers
  24  * @enable: fn ptr that enables the current clock in hardware
  25  * @disable: fn ptr that enables the current clock in hardware
  26  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  27  * @find_companion: function returning the "companion" clk reg for the clock
  28  *
  29  * A "companion" clk is an accompanying clock to the one being queried
  30  * that must be enabled for the IP module connected to the clock to
  31  * become accessible by the hardware.  Neither @find_idlest nor
  32  * @find_companion should be needed; that information is IP
  33  * block-specific; the hwmod code has been created to handle this, but
  34  * until hwmod data is ready and drivers have been converted to use PM
  35  * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
  36  * @find_companion must, unfortunately, remain.
  37  */
  38 struct clkops {
  39         int                     (*enable)(struct clk *);
  40         void                    (*disable)(struct clk *);
  41         void                    (*find_idlest)(struct clk *, void __iomem **,
  42                                                u8 *, u8 *);
  43         void                    (*find_companion)(struct clk *, void __iomem **,
  44                                                   u8 *);
  45 };
  46
  47 #ifdef CONFIG_ARCH_OMAP2PLUS
  48
  49 /* struct clksel_rate.flags possibilities */
  50 #define RATE_IN_242X            (1 << 0)
  51 #define RATE_IN_243X            (1 << 1)
  52 #define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
  53 #define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
  54 #define RATE_IN_36XX            (1 << 4)
  55 #define RATE_IN_4430            (1 << 5)
  56
  57 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
  58 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
  59 #define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
  60
  61 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
  62 #define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
  63
  64
  65 /**
  66  * struct clksel_rate - register bitfield values corresponding to clk divisors
  67  * @val: register bitfield value (shifted to bit 0)
  68  * @div: clock divisor corresponding to @val
  69  * @flags: (see "struct clksel_rate.flags possibilities" above)
  70  *
  71  * @val should match the value of a read from struct clk.clksel_reg
  72  * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
  73  *
  74  * @div is the divisor that should be applied to the parent clock's rate
  75  * to produce the current clock's rate.
  76  *
  77  * XXX @flags probably should be replaced with an struct omap_chip.
  78  */
  79 struct clksel_rate {
  80         u32                     val;
  81         u8                      div;
  82         u8                      flags;
  83 };
  84
  85 /**
  86  * struct clksel - available parent clocks, and a pointer to their divisors
  87  * @parent: struct clk * to a possible parent clock
  88  * @rates: available divisors for this parent clock
  89  *
  90  * A struct clksel is always associated with one or more struct clks
  91  * and one or more struct clksel_rates.
  92  */
  93 struct clksel {
  94         struct clk               *parent;
  95         const struct clksel_rate *rates;
  96 };
  97
  98 /**
  99  * struct dpll_data - DPLL registers and integration data
 100  * @mult_div1_reg: register containing the DPLL M and N bitfields
 101  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
 102  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
 103  * @clk_bypass: struct clk pointer to the clock's bypass clock input
 104  * @clk_ref: struct clk pointer to the clock's reference clock input
 105  * @control_reg: register containing the DPLL mode bitfield
 106  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
 107  * @rate_tolerance: maximum variance allowed from target rate (in Hz)
 108  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
 109  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
 110  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
 111  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
 112  * @min_divider: minimum valid non-bypass divider value (actual)
 113  * @max_divider: maximum valid non-bypass divider value (actual)
 114  * @modes: possible values of @enable_mask
 115  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
 116  * @idlest_reg: register containing the DPLL idle status bitfield
 117  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
 118  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
 119  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
 120  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
 121  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
 122  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
 123  * @flags: DPLL type/features (see below)
 124  *
 125  * Possible values for @flags:
 126  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
 127  *
 128  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
 129  *
 130  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
 131  * correct to only have one @clk_bypass pointer.
 132  *
 133  * XXX @rate_tolerance should probably be deprecated - currently there
 134  * don't seem to be any usecases for DPLL rounding that is not exact.
 135  *
 136  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
 137  * @last_rounded_n) should be separated from the runtime-fixed fields
 138  * and placed into a differenct structure, so that the runtime-fixed data
 139  * can be placed into read-only space.
 140  */
 141 struct dpll_data {
 142         void __iomem            *mult_div1_reg;
 143         u32                     mult_mask;
 144         u32                     div1_mask;
 145         struct clk              *clk_bypass;
 146         struct clk              *clk_ref;
 147         void __iomem            *control_reg;
 148         u32                     enable_mask;
 149         unsigned int            rate_tolerance;
 150         unsigned long           last_rounded_rate;
 151         u16                     last_rounded_m;
 152         u16                     max_multiplier;
 153         u8                      last_rounded_n;
 154         u8                      min_divider;
 155         u8                      max_divider;
 156         u8                      modes;
 157 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 158         void __iomem            *autoidle_reg;
 159         void __iomem            *idlest_reg;
 160         u32                     autoidle_mask;
 161         u32                     freqsel_mask;
 162         u32                     idlest_mask;
 163         u32                     dco_mask;
 164         u32                     sddiv_mask;
 165         u8                      auto_recal_bit;
 166         u8                      recal_en_bit;
 167         u8                      recal_st_bit;
 168         u8                      flags;
 169 #  endif
 170 };
 171
 172 #endif
 173
 174 /* struct clk.flags possibilities */
 175 #define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
 176 #define CLOCK_IDLE_CONTROL      (1 << 1)
 177 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
 178 #define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
 179 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
 180
 181 /**
 182  * struct clk - OMAP struct clk
 183  * @node: list_head connecting this clock into the full clock list
 184  * @ops: struct clkops * for this clock
 185  * @name: the name of the clock in the hardware (used in hwmod data and debug)
 186  * @parent: pointer to this clock's parent struct clk
 187  * @children: list_head connecting to the child clks' @sibling list_heads
 188  * @sibling: list_head connecting this clk to its parent clk's @children
 189  * @rate: current clock rate
 190  * @enable_reg: register to write to enable the clock (see @enable_bit)
 191  * @recalc: fn ptr that returns the clock's current rate
 192  * @set_rate: fn ptr that can change the clock's current rate
 193  * @round_rate: fn ptr that can round the clock's current rate
 194  * @init: fn ptr to do clock-specific initialization
 195  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
 196  * @usecount: number of users that have requested this clock to be enabled
 197  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
 198  * @flags: see "struct clk.flags possibilities" above
 199  * @clksel_reg: for clksel clks, register va containing src/divisor select
 200  * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
 201  * @clksel: for clksel clks, pointer to struct clksel for this clock
 202  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
 203  * @clkdm_name: clockdomain name that this clock is contained in
 204  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
 205  * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
 206  * @src_offset: bitshift for source selection bitfield (OMAP1 only)
 207  *
 208  * XXX @rate_offset, @src_offset should probably be removed and OMAP1
 209  * clock code converted to use clksel.
 210  *
 211  * XXX @usecount is poorly named.  It should be "enable_count" or
 212  * something similar.  "users" in the description refers to kernel
 213  * code (core code or drivers) that have called clk_enable() and not
 214  * yet called clk_disable(); the usecount of parent clocks is also
 215  * incremented by the clock code when clk_enable() is called on child
 216  * clocks and decremented by the clock code when clk_disable() is
 217  * called on child clocks.
 218  *
 219  * XXX @clkdm, @usecount, @children, @sibling should be marked for
 220  * internal use only.
 221  *
 222  * @children and @sibling are used to optimize parent-to-child clock
 223  * tree traversals.  (child-to-parent traversals use @parent.)
 224  *
 225  * XXX The notion of the clock's current rate probably needs to be
 226  * separated from the clock's target rate.
 227  */
 228 struct clk {
 229         struct list_head        node;
 230         const struct clkops     *ops;
 231         const char              *name;
 232         struct clk              *parent;
 233         struct list_head        children;
 234         struct list_head        sibling;        /* node for children */
 235         unsigned long           rate;
 236         void __iomem            *enable_reg;
 237         unsigned long           (*recalc)(struct clk *);
 238         int                     (*set_rate)(struct clk *, unsigned long);
 239         long                    (*round_rate)(struct clk *, unsigned long);
 240         void                    (*init)(struct clk *);
 241         u8                      enable_bit;
 242         s8                      usecount;
 243         u8                      fixed_div;
 244         u8                      flags;
 245 #ifdef CONFIG_ARCH_OMAP2PLUS
 246         void __iomem            *clksel_reg;
 247         u32                     clksel_mask;
 248         const struct clksel     *clksel;
 249         struct dpll_data        *dpll_data;
 250         const char              *clkdm_name;
 251         struct clockdomain      *clkdm;
 252 #else
 253         u8                      rate_offset;
 254         u8                      src_offset;
 255 #endif
 256 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 257         struct dentry           *dent;  /* For visible tree hierarchy */
 258 #endif
 259 };
 260
 261 struct cpufreq_frequency_table;
 262
 263 struct clk_functions {
 264         int             (*clk_enable)(struct clk *clk);
 265         void            (*clk_disable)(struct clk *clk);
 266         long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
 267         int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
 268         int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
 269         void            (*clk_allow_idle)(struct clk *clk);
 270         void            (*clk_deny_idle)(struct clk *clk);
 271         void            (*clk_disable_unused)(struct clk *clk);
 272 #ifdef CONFIG_CPU_FREQ
 273         void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
 274         void            (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
 275 #endif
 276 };
 277
 278 extern int mpurate;
 279
 280 extern int clk_init(struct clk_functions *custom_clocks);
 281 extern void clk_preinit(struct clk *clk);
 282 extern int clk_register(struct clk *clk);
 283 extern void clk_reparent(struct clk *child, struct clk *parent);
 284 extern void clk_unregister(struct clk *clk);
 285 extern void propagate_rate(struct clk *clk);
 286 extern void recalculate_root_clocks(void);
 287 extern unsigned long followparent_recalc(struct clk *clk);
 288 extern void clk_enable_init_clocks(void);
 289 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
 290 #ifdef CONFIG_CPU_FREQ
 291 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 292 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 293 #endif
 294 extern struct clk *omap_clk_get_by_name(const char *name);
 295
 296 extern const struct clkops clkops_null;
 297
 298 extern struct clk dummy_ck;
 299
 300 #endif