arch/arm/plat-omap/include/plat/mcbsp.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mcbsp.h
   3  *
   4  * Defines for Multi-Channel Buffered Serial Port
   5  *
   6  * Copyright (C) 2002 RidgeRun, Inc.
   7  * Author: Steve Johnson
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  *
  23  */
  24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
  25 #define __ASM_ARCH_OMAP_MCBSP_H
  26
  27 #include <linux/completion.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <mach/hardware.h>
  31 #include <plat/clock.h>
  32
  33 /* macro for building platform_device for McBSP ports */
  34 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
  35 static struct platform_device omap_mcbsp##port_nr = {   \
  36         .name   = "omap-mcbsp-dai",                     \
  37         .id     = OMAP_MCBSP##port_nr,                  \
  38 }
  39
  40 #define OMAP7XX_MCBSP1_BASE     0xfffb1000
  41 #define OMAP7XX_MCBSP2_BASE     0xfffb1800
  42
  43 #define OMAP1510_MCBSP1_BASE    0xe1011800
  44 #define OMAP1510_MCBSP2_BASE    0xfffb1000
  45 #define OMAP1510_MCBSP3_BASE    0xe1017000
  46
  47 #define OMAP1610_MCBSP1_BASE    0xe1011800
  48 #define OMAP1610_MCBSP2_BASE    0xfffb1000
  49 #define OMAP1610_MCBSP3_BASE    0xe1017000
  50
  51 #define OMAP24XX_MCBSP1_BASE    0x48074000
  52 #define OMAP24XX_MCBSP2_BASE    0x48076000
  53 #define OMAP2430_MCBSP3_BASE    0x4808c000
  54 #define OMAP2430_MCBSP4_BASE    0x4808e000
  55 #define OMAP2430_MCBSP5_BASE    0x48096000
  56
  57 #define OMAP34XX_MCBSP1_BASE    0x48074000
  58 #define OMAP34XX_MCBSP2_BASE    0x49022000
  59 #define OMAP34XX_MCBSP2_ST_BASE 0x49028000
  60 #define OMAP34XX_MCBSP3_BASE    0x49024000
  61 #define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
  62 #define OMAP34XX_MCBSP3_BASE    0x49024000
  63 #define OMAP34XX_MCBSP4_BASE    0x49026000
  64 #define OMAP34XX_MCBSP5_BASE    0x48096000
  65
  66 #define OMAP44XX_MCBSP1_BASE    0x49022000
  67 #define OMAP44XX_MCBSP2_BASE    0x49024000
  68 #define OMAP44XX_MCBSP3_BASE    0x49026000
  69 #define OMAP44XX_MCBSP4_BASE    0x48096000
  70
  71 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
  72
  73 #define OMAP_MCBSP_REG_DRR2     0x00
  74 #define OMAP_MCBSP_REG_DRR1     0x02
  75 #define OMAP_MCBSP_REG_DXR2     0x04
  76 #define OMAP_MCBSP_REG_DXR1     0x06
  77 #define OMAP_MCBSP_REG_SPCR2    0x08
  78 #define OMAP_MCBSP_REG_SPCR1    0x0a
  79 #define OMAP_MCBSP_REG_RCR2     0x0c
  80 #define OMAP_MCBSP_REG_RCR1     0x0e
  81 #define OMAP_MCBSP_REG_XCR2     0x10
  82 #define OMAP_MCBSP_REG_XCR1     0x12
  83 #define OMAP_MCBSP_REG_SRGR2    0x14
  84 #define OMAP_MCBSP_REG_SRGR1    0x16
  85 #define OMAP_MCBSP_REG_MCR2     0x18
  86 #define OMAP_MCBSP_REG_MCR1     0x1a
  87 #define OMAP_MCBSP_REG_RCERA    0x1c
  88 #define OMAP_MCBSP_REG_RCERB    0x1e
  89 #define OMAP_MCBSP_REG_XCERA    0x20
  90 #define OMAP_MCBSP_REG_XCERB    0x22
  91 #define OMAP_MCBSP_REG_PCR0     0x24
  92 #define OMAP_MCBSP_REG_RCERC    0x26
  93 #define OMAP_MCBSP_REG_RCERD    0x28
  94 #define OMAP_MCBSP_REG_XCERC    0x2A
  95 #define OMAP_MCBSP_REG_XCERD    0x2C
  96 #define OMAP_MCBSP_REG_RCERE    0x2E
  97 #define OMAP_MCBSP_REG_RCERF    0x30
  98 #define OMAP_MCBSP_REG_XCERE    0x32
  99 #define OMAP_MCBSP_REG_XCERF    0x34
 100 #define OMAP_MCBSP_REG_RCERG    0x36
 101 #define OMAP_MCBSP_REG_RCERH    0x38
 102 #define OMAP_MCBSP_REG_XCERG    0x3A
 103 #define OMAP_MCBSP_REG_XCERH    0x3C
 104
 105 /* Dummy defines, these are not available on omap1 */
 106 #define OMAP_MCBSP_REG_XCCR     0x00
 107 #define OMAP_MCBSP_REG_RCCR     0x00
 108
 109 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
 110 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
 111
 112 #define AUDIO_MCBSP             OMAP_MCBSP1
 113 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
 114 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 115
 116 #else
 117
 118 #define OMAP_MCBSP_REG_DRR2     0x00
 119 #define OMAP_MCBSP_REG_DRR1     0x04
 120 #define OMAP_MCBSP_REG_DXR2     0x08
 121 #define OMAP_MCBSP_REG_DXR1     0x0C
 122 #define OMAP_MCBSP_REG_DRR      0x00
 123 #define OMAP_MCBSP_REG_DXR      0x08
 124 #define OMAP_MCBSP_REG_SPCR2    0x10
 125 #define OMAP_MCBSP_REG_SPCR1    0x14
 126 #define OMAP_MCBSP_REG_RCR2     0x18
 127 #define OMAP_MCBSP_REG_RCR1     0x1C
 128 #define OMAP_MCBSP_REG_XCR2     0x20
 129 #define OMAP_MCBSP_REG_XCR1     0x24
 130 #define OMAP_MCBSP_REG_SRGR2    0x28
 131 #define OMAP_MCBSP_REG_SRGR1    0x2C
 132 #define OMAP_MCBSP_REG_MCR2     0x30
 133 #define OMAP_MCBSP_REG_MCR1     0x34
 134 #define OMAP_MCBSP_REG_RCERA    0x38
 135 #define OMAP_MCBSP_REG_RCERB    0x3C
 136 #define OMAP_MCBSP_REG_XCERA    0x40
 137 #define OMAP_MCBSP_REG_XCERB    0x44
 138 #define OMAP_MCBSP_REG_PCR0     0x48
 139 #define OMAP_MCBSP_REG_RCERC    0x4C
 140 #define OMAP_MCBSP_REG_RCERD    0x50
 141 #define OMAP_MCBSP_REG_XCERC    0x54
 142 #define OMAP_MCBSP_REG_XCERD    0x58
 143 #define OMAP_MCBSP_REG_RCERE    0x5C
 144 #define OMAP_MCBSP_REG_RCERF    0x60
 145 #define OMAP_MCBSP_REG_XCERE    0x64
 146 #define OMAP_MCBSP_REG_XCERF    0x68
 147 #define OMAP_MCBSP_REG_RCERG    0x6C
 148 #define OMAP_MCBSP_REG_RCERH    0x70
 149 #define OMAP_MCBSP_REG_XCERG    0x74
 150 #define OMAP_MCBSP_REG_XCERH    0x78
 151 #define OMAP_MCBSP_REG_SYSCON   0x8C
 152 #define OMAP_MCBSP_REG_THRSH2   0x90
 153 #define OMAP_MCBSP_REG_THRSH1   0x94
 154 #define OMAP_MCBSP_REG_IRQST    0xA0
 155 #define OMAP_MCBSP_REG_IRQEN    0xA4
 156 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 157 #define OMAP_MCBSP_REG_XCCR     0xAC
 158 #define OMAP_MCBSP_REG_RCCR     0xB0
 159 #define OMAP_MCBSP_REG_XBUFFSTAT        0xB4
 160 #define OMAP_MCBSP_REG_RBUFFSTAT        0xB8
 161 #define OMAP_MCBSP_REG_SSELCR   0xBC
 162
 163 #define OMAP_ST_REG_REV         0x00
 164 #define OMAP_ST_REG_SYSCONFIG   0x10
 165 #define OMAP_ST_REG_IRQSTATUS   0x18
 166 #define OMAP_ST_REG_IRQENABLE   0x1C
 167 #define OMAP_ST_REG_SGAINCR     0x24
 168 #define OMAP_ST_REG_SFIRCR      0x28
 169 #define OMAP_ST_REG_SSELCR      0x2C
 170
 171 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 172 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
 173
 174 #define AUDIO_MCBSP             OMAP_MCBSP2
 175 #define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
 176 #define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
 177
 178 #endif
 179
 180 /************************** McBSP SPCR1 bit definitions ***********************/
 181 #define RRST                    0x0001
 182 #define RRDY                    0x0002
 183 #define RFULL                   0x0004
 184 #define RSYNC_ERR               0x0008
 185 #define RINTM(value)            ((value)<<4)    /* bits 4:5 */
 186 #define ABIS                    0x0040
 187 #define DXENA                   0x0080
 188 #define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
 189 #define RJUST(value)            ((value)<<13)   /* bits 13:14 */
 190 #define ALB                     0x8000
 191 #define DLB                     0x8000
 192
 193 /************************** McBSP SPCR2 bit definitions ***********************/
 194 #define XRST            0x0001
 195 #define XRDY            0x0002
 196 #define XEMPTY          0x0004
 197 #define XSYNC_ERR       0x0008
 198 #define XINTM(value)    ((value)<<4)            /* bits 4:5 */
 199 #define GRST            0x0040
 200 #define FRST            0x0080
 201 #define SOFT            0x0100
 202 #define FREE            0x0200
 203
 204 /************************** McBSP PCR bit definitions *************************/
 205 #define CLKRP           0x0001
 206 #define CLKXP           0x0002
 207 #define FSRP            0x0004
 208 #define FSXP            0x0008
 209 #define DR_STAT         0x0010
 210 #define DX_STAT         0x0020
 211 #define CLKS_STAT       0x0040
 212 #define SCLKME          0x0080
 213 #define CLKRM           0x0100
 214 #define CLKXM           0x0200
 215 #define FSRM            0x0400
 216 #define FSXM            0x0800
 217 #define RIOEN           0x1000
 218 #define XIOEN           0x2000
 219 #define IDLE_EN         0x4000
 220
 221 /************************** McBSP RCR1 bit definitions ************************/
 222 #define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 223 #define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 224
 225 /************************** McBSP XCR1 bit definitions ************************/
 226 #define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 227 #define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 228
 229 /*************************** McBSP RCR2 bit definitions ***********************/
 230 #define RDATDLY(value)          (value)         /* Bits 0:1 */
 231 #define RFIG                    0x0004
 232 #define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 233 #define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 234 #define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 235 #define RPHASE                  0x8000
 236
 237 /*************************** McBSP XCR2 bit definitions ***********************/
 238 #define XDATDLY(value)          (value)         /* Bits 0:1 */
 239 #define XFIG                    0x0004
 240 #define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 241 #define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 242 #define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 243 #define XPHASE                  0x8000
 244
 245 /************************* McBSP SRGR1 bit definitions ************************/
 246 #define CLKGDV(value)           (value)         /* Bits 0:7 */
 247 #define FWID(value)             ((value)<<8)    /* Bits 8:15 */
 248
 249 /************************* McBSP SRGR2 bit definitions ************************/
 250 #define FPER(value)             (value)         /* Bits 0:11 */
 251 #define FSGM                    0x1000
 252 #define CLKSM                   0x2000
 253 #define CLKSP                   0x4000
 254 #define GSYNC                   0x8000
 255
 256 /************************* McBSP MCR1 bit definitions *************************/
 257 #define RMCM                    0x0001
 258 #define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 259 #define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 260 #define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 261
 262 /************************* McBSP MCR2 bit definitions *************************/
 263 #define XMCM(value)             (value)         /* Bits 0:1 */
 264 #define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 265 #define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 266 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 267
 268 /*********************** McBSP XCCR bit definitions *************************/
 269 #define EXTCLKGATE              0x8000
 270 #define PPCONNECT               0x4000
 271 #define DXENDLY(value)          ((value)<<12)   /* Bits 12:13 */
 272 #define XFULL_CYCLE             0x0800
 273 #define DILB                    0x0020
 274 #define XDMAEN                  0x0008
 275 #define XDISABLE                0x0001
 276
 277 /********************** McBSP RCCR bit definitions *************************/
 278 #define RFULL_CYCLE             0x0800
 279 #define RDMAEN                  0x0008
 280 #define RDISABLE                0x0001
 281
 282 /********************** McBSP SYSCONFIG bit definitions ********************/
 283 #define CLOCKACTIVITY(value)    ((value)<<8)
 284 #define SIDLEMODE(value)        ((value)<<3)
 285 #define ENAWAKEUP               0x0004
 286 #define SOFTRST                 0x0002
 287
 288 /********************** McBSP SSELCR bit definitions ***********************/
 289 #define SIDETONEEN              0x0400
 290
 291 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
 292 #define ST_AUTOIDLE             0x0001
 293
 294 /********************** McBSP Sidetone SGAINCR bit definitions *************/
 295 #define ST_CH1GAIN(value)       ((value<<16))   /* Bits 16:31 */
 296 #define ST_CH0GAIN(value)       (value)         /* Bits 0:15 */
 297
 298 /********************** McBSP Sidetone SFIRCR bit definitions **************/
 299 #define ST_FIRCOEFF(value)      (value)         /* Bits 0:15 */
 300
 301 /********************** McBSP Sidetone SSELCR bit definitions **************/
 302 #define ST_COEFFWRDONE          0x0004
 303 #define ST_COEFFWREN            0x0002
 304 #define ST_SIDETONEEN           0x0001
 305
 306 /********************** McBSP DMA operating modes **************************/
 307 #define MCBSP_DMA_MODE_ELEMENT          0
 308 #define MCBSP_DMA_MODE_THRESHOLD        1
 309 #define MCBSP_DMA_MODE_FRAME            2
 310
 311 /********************** McBSP WAKEUPEN bit definitions *********************/
 312 #define XEMPTYEOFEN             0x4000
 313 #define XRDYEN                  0x0400
 314 #define XEOFEN                  0x0200
 315 #define XFSXEN                  0x0100
 316 #define XSYNCERREN              0x0080
 317 #define RRDYEN                  0x0008
 318 #define REOFEN                  0x0004
 319 #define RFSREN                  0x0002
 320 #define RSYNCERREN              0x0001
 321
 322 /* CLKR signal muxing options */
 323 #define CLKR_SRC_CLKR           0
 324 #define CLKR_SRC_CLKX           1
 325
 326 /* FSR signal muxing options */
 327 #define FSR_SRC_FSR             0
 328 #define FSR_SRC_FSX             1
 329
 330 /* McBSP functional clock sources */
 331 #define MCBSP_CLKS_PRCM_SRC     0
 332 #define MCBSP_CLKS_PAD_SRC      1
 333
 334 /* we don't do multichannel for now */
 335 struct omap_mcbsp_reg_cfg {
 336         u16 spcr2;
 337         u16 spcr1;
 338         u16 rcr2;
 339         u16 rcr1;
 340         u16 xcr2;
 341         u16 xcr1;
 342         u16 srgr2;
 343         u16 srgr1;
 344         u16 mcr2;
 345         u16 mcr1;
 346         u16 pcr0;
 347         u16 rcerc;
 348         u16 rcerd;
 349         u16 xcerc;
 350         u16 xcerd;
 351         u16 rcere;
 352         u16 rcerf;
 353         u16 xcere;
 354         u16 xcerf;
 355         u16 rcerg;
 356         u16 rcerh;
 357         u16 xcerg;
 358         u16 xcerh;
 359         u16 xccr;
 360         u16 rccr;
 361 };
 362
 363 typedef enum {
 364         OMAP_MCBSP1 = 0,
 365         OMAP_MCBSP2,
 366         OMAP_MCBSP3,
 367         OMAP_MCBSP4,
 368         OMAP_MCBSP5
 369 } omap_mcbsp_id;
 370
 371 typedef int __bitwise omap_mcbsp_io_type_t;
 372 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
 373 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
 374
 375 typedef enum {
 376         OMAP_MCBSP_WORD_8 = 0,
 377         OMAP_MCBSP_WORD_12,
 378         OMAP_MCBSP_WORD_16,
 379         OMAP_MCBSP_WORD_20,
 380         OMAP_MCBSP_WORD_24,
 381         OMAP_MCBSP_WORD_32,
 382 } omap_mcbsp_word_length;
 383
 384 typedef enum {
 385         OMAP_MCBSP_CLK_RISING = 0,
 386         OMAP_MCBSP_CLK_FALLING,
 387 } omap_mcbsp_clk_polarity;
 388
 389 typedef enum {
 390         OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
 391         OMAP_MCBSP_FS_ACTIVE_LOW,
 392 } omap_mcbsp_fs_polarity;
 393
 394 typedef enum {
 395         OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
 396         OMAP_MCBSP_CLK_STP_MODE_DELAY,
 397 } omap_mcbsp_clk_stp_mode;
 398
 399
 400 /******* SPI specific mode **********/
 401 typedef enum {
 402         OMAP_MCBSP_SPI_MASTER = 0,
 403         OMAP_MCBSP_SPI_SLAVE,
 404 } omap_mcbsp_spi_mode;
 405
 406 struct omap_mcbsp_spi_cfg {
 407         omap_mcbsp_spi_mode             spi_mode;
 408         omap_mcbsp_clk_polarity         rx_clock_polarity;
 409         omap_mcbsp_clk_polarity         tx_clock_polarity;
 410         omap_mcbsp_fs_polarity          fsx_polarity;
 411         u8                              clk_div;
 412         omap_mcbsp_clk_stp_mode         clk_stp_mode;
 413         omap_mcbsp_word_length          word_length;
 414 };
 415
 416 /* Platform specific configuration */
 417 struct omap_mcbsp_ops {
 418         void (*request)(unsigned int);
 419         void (*free)(unsigned int);
 420         int (*set_clks_src)(u8, u8);
 421 };
 422
 423 struct omap_mcbsp_platform_data {
 424         unsigned long phys_base;
 425         u8 dma_rx_sync, dma_tx_sync;
 426         u16 rx_irq, tx_irq;
 427         struct omap_mcbsp_ops *ops;
 428 #ifdef CONFIG_ARCH_OMAP3
 429         /* Sidetone block for McBSP 2 and 3 */
 430         unsigned long phys_base_st;
 431         u16 buffer_size;
 432 #endif
 433 };
 434
 435 struct omap_mcbsp_st_data {
 436         void __iomem *io_base_st;
 437         bool running;
 438         bool enabled;
 439         s16 taps[128];  /* Sidetone filter coefficients */
 440         int nr_taps;    /* Number of filter coefficients in use */
 441         s16 ch0gain;
 442         s16 ch1gain;
 443 };
 444
 445 struct omap_mcbsp {
 446         struct device *dev;
 447         unsigned long phys_base;
 448         void __iomem *io_base;
 449         u8 id;
 450         u8 free;
 451         omap_mcbsp_word_length rx_word_length;
 452         omap_mcbsp_word_length tx_word_length;
 453
 454         omap_mcbsp_io_type_t io_type; /* IRQ or poll */
 455         /* IRQ based TX/RX */
 456         int rx_irq;
 457         int tx_irq;
 458
 459         /* DMA stuff */
 460         u8 dma_rx_sync;
 461         short dma_rx_lch;
 462         u8 dma_tx_sync;
 463         short dma_tx_lch;
 464
 465         /* Completion queues */
 466         struct completion tx_irq_completion;
 467         struct completion rx_irq_completion;
 468         struct completion tx_dma_completion;
 469         struct completion rx_dma_completion;
 470
 471         /* Protect the field .free, while checking if the mcbsp is in use */
 472         spinlock_t lock;
 473         struct omap_mcbsp_platform_data *pdata;
 474         struct clk *iclk;
 475         struct clk *fclk;
 476 #ifdef CONFIG_ARCH_OMAP3
 477         struct omap_mcbsp_st_data *st_data;
 478         int dma_op_mode;
 479         u16 max_tx_thres;
 480         u16 max_rx_thres;
 481 #endif
 482         void *reg_cache;
 483 };
 484 extern struct omap_mcbsp **mcbsp_ptr;
 485 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 486
 487 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
 488 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 489
 490 int omap_mcbsp_init(void);
 491 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 492                                         int size);
 493 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 494 #ifdef CONFIG_ARCH_OMAP3
 495 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 496 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 497 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
 498 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
 499 u16 omap_mcbsp_get_fifo_size(unsigned int id);
 500 u16 omap_mcbsp_get_tx_delay(unsigned int id);
 501 u16 omap_mcbsp_get_rx_delay(unsigned int id);
 502 int omap_mcbsp_get_dma_op_mode(unsigned int id);
 503 #else
 504 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 505 { }
 506 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 507 { }
 508 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
 509 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
 510 static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
 511 static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
 512 static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
 513 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
 514 #endif
 515 int omap_mcbsp_request(unsigned int id);
 516 void omap_mcbsp_free(unsigned int id);
 517 void omap_mcbsp_start(unsigned int id, int tx, int rx);
 518 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
 519 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 520 u32 omap_mcbsp_recv_word(unsigned int id);
 521
 522 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 523 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 524 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 525 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
 526
 527
 528 /* McBSP functional clock source changing function */
 529 extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
 530 /* SPI specific API */
 531 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
 532
 533 /* Polled read/write functions */
 534 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 535 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 536 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 537
 538 /* McBSP signal muxing API */
 539 void omap2_mcbsp1_mux_clkr_src(u8 mux);
 540 void omap2_mcbsp1_mux_fsr_src(u8 mux);
 541
 542 #ifdef CONFIG_ARCH_OMAP3
 543 /* Sidetone specific API */
 544 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
 545 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
 546 int omap_st_enable(unsigned int id);
 547 int omap_st_disable(unsigned int id);
 548 int omap_st_is_enabled(unsigned int id);
 549 #else
 550 static inline int omap_st_set_chgain(unsigned int id, int channel,
 551                                      s16 chgain) { return 0; }
 552 static inline int omap_st_get_chgain(unsigned int id, int channel,
 553                                      s16 *chgain) { return 0; }
 554 static inline int omap_st_enable(unsigned int id) { return 0; }
 555 static inline int omap_st_disable(unsigned int id) { return 0; }
 556 static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
 557 #endif
 558
 559 #endif