2 * arch/arm/plat-spear/clock.c
4 * Clock framework for SPEAr platform
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/bug.h>
15 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <mach/misc_regs.h>
21 #include <plat/clock.h>
23 static DEFINE_SPINLOCK(clocks_lock
);
24 static LIST_HEAD(root_clks
);
26 static void propagate_rate(struct list_head
*);
28 static int generic_clk_enable(struct clk
*clk
)
35 val
= readl(clk
->en_reg
);
36 if (unlikely(clk
->flags
& RESET_TO_ENABLE
))
37 val
&= ~(1 << clk
->en_reg_bit
);
39 val
|= 1 << clk
->en_reg_bit
;
41 writel(val
, clk
->en_reg
);
46 static void generic_clk_disable(struct clk
*clk
)
53 val
= readl(clk
->en_reg
);
54 if (unlikely(clk
->flags
& RESET_TO_ENABLE
))
55 val
|= 1 << clk
->en_reg_bit
;
57 val
&= ~(1 << clk
->en_reg_bit
);
59 writel(val
, clk
->en_reg
);
63 static struct clkops generic_clkops
= {
64 .enable
= generic_clk_enable
,
65 .disable
= generic_clk_disable
,
69 * clk_enable - inform the system when the clock source should be running.
72 * If the clock can not be enabled/disabled, this should return success.
74 * Returns success (0) or negative errno.
76 int clk_enable(struct clk
*clk
)
81 if (!clk
|| IS_ERR(clk
))
84 spin_lock_irqsave(&clocks_lock
, flags
);
85 if (clk
->usage_count
== 0) {
86 if (clk
->ops
&& clk
->ops
->enable
)
87 ret
= clk
->ops
->enable(clk
);
90 spin_unlock_irqrestore(&clocks_lock
, flags
);
94 EXPORT_SYMBOL(clk_enable
);
97 * clk_disable - inform the system when the clock source is no longer required.
100 * Inform the system that a clock source is no longer required by
101 * a driver and may be shut down.
103 * Implementation detail: if the clock source is shared between
104 * multiple drivers, clk_enable() calls must be balanced by the
105 * same number of clk_disable() calls for the clock source to be
108 void clk_disable(struct clk
*clk
)
112 if (!clk
|| IS_ERR(clk
))
115 WARN_ON(clk
->usage_count
== 0);
117 spin_lock_irqsave(&clocks_lock
, flags
);
119 if (clk
->usage_count
== 0) {
120 if (clk
->ops
&& clk
->ops
->disable
)
121 clk
->ops
->disable(clk
);
123 spin_unlock_irqrestore(&clocks_lock
, flags
);
125 EXPORT_SYMBOL(clk_disable
);
128 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
129 * This is only valid once the clock source has been enabled.
132 unsigned long clk_get_rate(struct clk
*clk
)
134 unsigned long flags
, rate
;
136 spin_lock_irqsave(&clocks_lock
, flags
);
138 spin_unlock_irqrestore(&clocks_lock
, flags
);
142 EXPORT_SYMBOL(clk_get_rate
);
145 * clk_set_parent - set the parent clock source for this clock
147 * @parent: parent clock source
149 * Returns success (0) or negative errno.
151 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
153 int i
, found
= 0, val
= 0;
156 if (!clk
|| IS_ERR(clk
) || !parent
|| IS_ERR(parent
))
158 if (clk
->usage_count
)
162 if (clk
->pclk
== parent
)
165 for (i
= 0; i
< clk
->pclk_sel
->pclk_count
; i
++) {
166 if (clk
->pclk_sel
->pclk_info
[i
].pclk
== parent
) {
175 spin_lock_irqsave(&clocks_lock
, flags
);
176 /* reflect parent change in hardware */
177 val
= readl(clk
->pclk_sel
->pclk_sel_reg
);
178 val
&= ~(clk
->pclk_sel
->pclk_sel_mask
<< clk
->pclk_sel_shift
);
179 val
|= clk
->pclk_sel
->pclk_info
[i
].pclk_mask
<< clk
->pclk_sel_shift
;
180 writel(val
, clk
->pclk_sel
->pclk_sel_reg
);
181 spin_unlock_irqrestore(&clocks_lock
, flags
);
183 /* reflect parent change in software */
185 propagate_rate(&clk
->children
);
188 EXPORT_SYMBOL(clk_set_parent
);
190 /* registers clock in platform clock framework */
191 void clk_register(struct clk_lookup
*cl
)
193 struct clk
*clk
= cl
->clk
;
196 if (!clk
|| IS_ERR(clk
))
199 spin_lock_irqsave(&clocks_lock
, flags
);
201 INIT_LIST_HEAD(&clk
->children
);
202 if (clk
->flags
& ALWAYS_ENABLED
)
205 clk
->ops
= &generic_clkops
;
207 /* root clock don't have any parents */
208 if (!clk
->pclk
&& !clk
->pclk_sel
) {
209 list_add(&clk
->sibling
, &root_clks
);
210 /* add clocks with only one parent to parent's children list */
211 } else if (clk
->pclk
&& !clk
->pclk_sel
) {
212 list_add(&clk
->sibling
, &clk
->pclk
->children
);
214 /* add clocks with > 1 parent to 1st parent's children list */
215 list_add(&clk
->sibling
,
216 &clk
->pclk_sel
->pclk_info
[0].pclk
->children
);
218 spin_unlock_irqrestore(&clocks_lock
, flags
);
220 /* add clock to arm clockdev framework */
225 * propagate_rate - recalculate and propagate all clocks in list head
227 * Recalculates all root clocks in list head, which if the clock's .recalc is
228 * set correctly, should also propagate their rates.
230 static void propagate_rate(struct list_head
*lhead
)
232 struct clk
*clkp
, *_temp
;
234 list_for_each_entry_safe(clkp
, _temp
, lhead
, sibling
) {
237 propagate_rate(&clkp
->children
);
241 /* returns current programmed clocks clock info structure */
242 static struct pclk_info
*pclk_info_get(struct clk
*clk
)
244 unsigned int mask
, i
;
246 struct pclk_info
*info
= NULL
;
248 spin_lock_irqsave(&clocks_lock
, flags
);
249 mask
= (readl(clk
->pclk_sel
->pclk_sel_reg
) >> clk
->pclk_sel_shift
)
250 & clk
->pclk_sel
->pclk_sel_mask
;
252 for (i
= 0; i
< clk
->pclk_sel
->pclk_count
; i
++) {
253 if (clk
->pclk_sel
->pclk_info
[i
].pclk_mask
== mask
)
254 info
= &clk
->pclk_sel
->pclk_info
[i
];
256 spin_unlock_irqrestore(&clocks_lock
, flags
);
262 * Set pclk as cclk's parent and add clock sibling node to current parents
265 static void change_parent(struct clk
*cclk
, struct clk
*pclk
)
269 spin_lock_irqsave(&clocks_lock
, flags
);
270 list_del(&cclk
->sibling
);
271 list_add(&cclk
->sibling
, &pclk
->children
);
274 spin_unlock_irqrestore(&clocks_lock
, flags
);
278 * calculates current programmed rate of pll1
281 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
284 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
286 void pll1_clk_recalc(struct clk
*clk
)
288 struct pll_clk_config
*config
= clk
->private_data
;
289 unsigned int num
= 2, den
= 0, val
, mode
= 0;
292 spin_lock_irqsave(&clocks_lock
, flags
);
293 mode
= (readl(config
->mode_reg
) >> PLL_MODE_SHIFT
) &
296 val
= readl(config
->cfg_reg
);
297 /* calculate denominator */
298 den
= (val
>> PLL_DIV_P_SHIFT
) & PLL_DIV_P_MASK
;
300 den
*= (val
>> PLL_DIV_N_SHIFT
) & PLL_DIV_N_MASK
;
302 /* calculate numerator & denominator */
305 num
*= (val
>> PLL_NORM_FDBK_M_SHIFT
) & PLL_NORM_FDBK_M_MASK
;
308 num
*= (val
>> PLL_DITH_FDBK_M_SHIFT
) & PLL_DITH_FDBK_M_MASK
;
312 clk
->rate
= (((clk
->pclk
->rate
/10000) * num
) / den
) * 10000;
313 spin_unlock_irqrestore(&clocks_lock
, flags
);
316 /* calculates current programmed rate of ahb or apb bus */
317 void bus_clk_recalc(struct clk
*clk
)
319 struct bus_clk_config
*config
= clk
->private_data
;
323 spin_lock_irqsave(&clocks_lock
, flags
);
324 div
= ((readl(config
->reg
) >> config
->shift
) & config
->mask
) + 1;
325 clk
->rate
= (unsigned long)clk
->pclk
->rate
/ div
;
326 spin_unlock_irqrestore(&clocks_lock
, flags
);
330 * calculates current programmed rate of auxiliary synthesizers
331 * used by: UART, FIRDA
333 * Fout from synthesizer can be given from two equations:
334 * Fout1 = (Fin * X/Y)/2
337 * Selection of eqn 1 or 2 is programmed in register
339 void aux_clk_recalc(struct clk
*clk
)
341 struct aux_clk_config
*config
= clk
->private_data
;
342 struct pclk_info
*pclk_info
= NULL
;
343 unsigned int num
= 1, den
= 1, val
, eqn
;
346 /* get current programmed parent */
347 pclk_info
= pclk_info_get(clk
);
349 spin_lock_irqsave(&clocks_lock
, flags
);
352 spin_unlock_irqrestore(&clocks_lock
, flags
);
356 change_parent(clk
, pclk_info
->pclk
);
358 spin_lock_irqsave(&clocks_lock
, flags
);
359 if (pclk_info
->scalable
) {
360 val
= readl(config
->synth_reg
);
362 eqn
= (val
>> AUX_EQ_SEL_SHIFT
) & AUX_EQ_SEL_MASK
;
363 if (eqn
== AUX_EQ1_SEL
)
366 /* calculate numerator */
367 num
= (val
>> AUX_XSCALE_SHIFT
) & AUX_XSCALE_MASK
;
369 /* calculate denominator */
370 den
*= (val
>> AUX_YSCALE_SHIFT
) & AUX_YSCALE_MASK
;
371 val
= (((clk
->pclk
->rate
/10000) * num
) / den
) * 10000;
373 val
= clk
->pclk
->rate
;
376 spin_unlock_irqrestore(&clocks_lock
, flags
);
380 * calculates current programmed rate of gpt synthesizers
381 * Fout from synthesizer can be given from below equations:
382 * Fout= Fin/((2 ^ (N+1)) * (M+1))
384 void gpt_clk_recalc(struct clk
*clk
)
386 struct aux_clk_config
*config
= clk
->private_data
;
387 struct pclk_info
*pclk_info
= NULL
;
388 unsigned int div
= 1, val
;
391 pclk_info
= pclk_info_get(clk
);
393 spin_lock_irqsave(&clocks_lock
, flags
);
396 spin_unlock_irqrestore(&clocks_lock
, flags
);
400 change_parent(clk
, pclk_info
->pclk
);
402 spin_lock_irqsave(&clocks_lock
, flags
);
403 if (pclk_info
->scalable
) {
404 val
= readl(config
->synth_reg
);
405 div
+= (val
>> GPT_MSCALE_SHIFT
) & GPT_MSCALE_MASK
;
406 div
*= 1 << (((val
>> GPT_NSCALE_SHIFT
) & GPT_NSCALE_MASK
) + 1);
409 clk
->rate
= (unsigned long)clk
->pclk
->rate
/ div
;
410 spin_unlock_irqrestore(&clocks_lock
, flags
);
414 * Used for clocks that always have same value as the parent clock divided by a
417 void follow_parent(struct clk
*clk
)
421 spin_lock_irqsave(&clocks_lock
, flags
);
422 clk
->rate
= clk
->pclk
->rate
;
423 spin_unlock_irqrestore(&clocks_lock
, flags
);
427 * recalc_root_clocks - recalculate and propagate all root clocks
429 * Recalculates all root clocks (clocks with no parent), which if the
430 * clock's .recalc is set correctly, should also propagate their rates.
432 void recalc_root_clocks(void)
434 propagate_rate(&root_clks
);