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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / bnx2x / bnx2x.h
blob6a858a29db56127d3f9346adb6b7ab31c617cf0c
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/types.h>
18
19 /* compilation time flags */
20
21 /* define this to make the driver freeze on error to allow getting debug info
22 * (you will need to reboot afterwards) */
23 /* #define BNX2X_STOP_ON_ERROR */
24
25 #define DRV_MODULE_VERSION "1.62.00-3"
26 #define DRV_MODULE_RELDATE "2010/12/21"
27 #define BNX2X_BC_VER 0x040200
28
29 #define BNX2X_MULTI_QUEUE
30
31 #define BNX2X_NEW_NAPI
32
33 #if defined(CONFIG_DCB)
34 #define BCM_DCB
35 #endif
36 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
37 #define BCM_CNIC 1
38 #include "../cnic_if.h"
39 #endif
40
41 #ifdef BCM_CNIC
42 #define BNX2X_MIN_MSIX_VEC_CNT 3
43 #define BNX2X_MSIX_VEC_FP_START 2
44 #else
45 #define BNX2X_MIN_MSIX_VEC_CNT 2
46 #define BNX2X_MSIX_VEC_FP_START 1
47 #endif
48
49 #include <linux/mdio.h>
50 #include <linux/pci.h>
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_hsi.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_dcb.h"
56 #include "bnx2x_stats.h"
57
58 /* error/debug prints */
59
60 #define DRV_MODULE_NAME "bnx2x"
61
62 /* for messages that are currently off */
63 #define BNX2X_MSG_OFF 0
64 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
66 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
68 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
69 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
70
71 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
72
73 /* regular debug print */
74 #define DP(__mask, __fmt, __args...) \
75 do { \
76 if (bp->msg_enable & (__mask)) \
77 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
78 __func__, __LINE__, \
79 bp->dev ? (bp->dev->name) : "?", \
80 ##__args); \
81 } while (0)
82
83 /* errors debug print */
84 #define BNX2X_DBG_ERR(__fmt, __args...) \
85 do { \
86 if (netif_msg_probe(bp)) \
87 pr_err("[%s:%d(%s)]" __fmt, \
88 __func__, __LINE__, \
89 bp->dev ? (bp->dev->name) : "?", \
90 ##__args); \
91 } while (0)
92
93 /* for errors (never masked) */
94 #define BNX2X_ERR(__fmt, __args...) \
95 do { \
96 pr_err("[%s:%d(%s)]" __fmt, \
97 __func__, __LINE__, \
98 bp->dev ? (bp->dev->name) : "?", \
99 ##__args); \
100 } while (0)
101
102 #define BNX2X_ERROR(__fmt, __args...) do { \
103 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
104 } while (0)
105
106
107 /* before we have a dev->name use dev_info() */
108 #define BNX2X_DEV_INFO(__fmt, __args...) \
109 do { \
110 if (netif_msg_probe(bp)) \
111 dev_info(&bp->pdev->dev, __fmt, ##__args); \
112 } while (0)
113
114 void bnx2x_panic_dump(struct bnx2x *bp);
115
116 #ifdef BNX2X_STOP_ON_ERROR
117 #define bnx2x_panic() do { \
118 bp->panic = 1; \
119 BNX2X_ERR("driver assert\n"); \
120 bnx2x_int_disable(bp); \
121 bnx2x_panic_dump(bp); \
122 } while (0)
123 #else
124 #define bnx2x_panic() do { \
125 bp->panic = 1; \
126 BNX2X_ERR("driver assert\n"); \
127 bnx2x_panic_dump(bp); \
128 } while (0)
129 #endif
130
131 #define bnx2x_mc_addr(ha) ((ha)->addr)
132
133 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
134 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
135 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
136
137
138 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
139
140 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
141 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
142 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
143
144 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
145 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
146 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
147
148 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
149 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
150
151 #define REG_RD_DMAE(bp, offset, valp, len32) \
152 do { \
153 bnx2x_read_dmae(bp, offset, len32);\
154 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
155 } while (0)
156
157 #define REG_WR_DMAE(bp, offset, valp, len32) \
158 do { \
159 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
160 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
161 offset, len32); \
162 } while (0)
163
164 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
165 REG_WR_DMAE(bp, offset, valp, len32)
166
167 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
168 do { \
169 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
170 bnx2x_write_big_buf_wb(bp, addr, len32); \
171 } while (0)
172
173 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
174 offsetof(struct shmem_region, field))
175 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
176 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
177
178 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
179 offsetof(struct shmem2_region, field))
180 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
181 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
182 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
183 offsetof(struct mf_cfg, field))
184 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
185 offsetof(struct mf2_cfg, field))
186
187 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
188 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
189 MF_CFG_ADDR(bp, field), (val))
190 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
191
192 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
193 (SHMEM2_RD((bp), size) > \
194 offsetof(struct shmem2_region, field)))
195
196 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
197 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
198
199 /* SP SB indices */
200
201 /* General SP events - stats query, cfc delete, etc */
202 #define HC_SP_INDEX_ETH_DEF_CONS 3
203
204 /* EQ completions */
205 #define HC_SP_INDEX_EQ_CONS 7
206
207 /* FCoE L2 connection completions */
208 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
209 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
210 /* iSCSI L2 */
211 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
212 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
213
214 /* Special clients parameters */
215
216 /* SB indices */
217 /* FCoE L2 */
218 #define BNX2X_FCOE_L2_RX_INDEX \
219 (&bp->def_status_blk->sp_sb.\
220 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
221
222 #define BNX2X_FCOE_L2_TX_INDEX \
223 (&bp->def_status_blk->sp_sb.\
224 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
225
226 /**
227 * CIDs and CLIDs:
228 * CLIDs below is a CLID for func 0, then the CLID for other
229 * functions will be calculated by the formula:
230 *
231 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
232 *
233 */
234 /* iSCSI L2 */
235 #define BNX2X_ISCSI_ETH_CL_ID 17
236 #define BNX2X_ISCSI_ETH_CID 17
237
238 /* FCoE L2 */
239 #define BNX2X_FCOE_ETH_CL_ID 18
240 #define BNX2X_FCOE_ETH_CID 18
241
242 /** Additional rings budgeting */
243 #ifdef BCM_CNIC
244 #define CNIC_CONTEXT_USE 1
245 #define FCOE_CONTEXT_USE 1
246 #else
247 #define CNIC_CONTEXT_USE 0
248 #define FCOE_CONTEXT_USE 0
249 #endif /* BCM_CNIC */
250 #define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE)
251
252 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
253 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
254
255 #define SM_RX_ID 0
256 #define SM_TX_ID 1
257
258 /* fast path */
259
260 struct sw_rx_bd {
261 struct sk_buff *skb;
262 DEFINE_DMA_UNMAP_ADDR(mapping);
263 };
264
265 struct sw_tx_bd {
266 struct sk_buff *skb;
267 u16 first_bd;
268 u8 flags;
269 /* Set on the first BD descriptor when there is a split BD */
270 #define BNX2X_TSO_SPLIT_BD (1<<0)
271 };
272
273 struct sw_rx_page {
274 struct page *page;
275 DEFINE_DMA_UNMAP_ADDR(mapping);
276 };
277
278 union db_prod {
279 struct doorbell_set_prod data;
280 u32 raw;
281 };
282
283
284 /* MC hsi */
285 #define BCM_PAGE_SHIFT 12
286 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
287 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
288 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
289
290 #define PAGES_PER_SGE_SHIFT 0
291 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
292 #define SGE_PAGE_SIZE PAGE_SIZE
293 #define SGE_PAGE_SHIFT PAGE_SHIFT
294 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
295
296 /* SGE ring related macros */
297 #define NUM_RX_SGE_PAGES 2
298 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
299 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
300 /* RX_SGE_CNT is promised to be a power of 2 */
301 #define RX_SGE_MASK (RX_SGE_CNT - 1)
302 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
303 #define MAX_RX_SGE (NUM_RX_SGE - 1)
304 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
305 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
306 #define RX_SGE(x) ((x) & MAX_RX_SGE)
307
308 /* SGE producer mask related macros */
309 /* Number of bits in one sge_mask array element */
310 #define RX_SGE_MASK_ELEM_SZ 64
311 #define RX_SGE_MASK_ELEM_SHIFT 6
312 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
313
314 /* Creates a bitmask of all ones in less significant bits.
315 idx - index of the most significant bit in the created mask */
316 #define RX_SGE_ONES_MASK(idx) \
317 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
318 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
319
320 /* Number of u64 elements in SGE mask array */
321 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
322 RX_SGE_MASK_ELEM_SZ)
323 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
324 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
325
326 union host_hc_status_block {
327 /* pointer to fp status block e1x */
328 struct host_hc_status_block_e1x *e1x_sb;
329 /* pointer to fp status block e2 */
330 struct host_hc_status_block_e2 *e2_sb;
331 };
332
333 struct bnx2x_fastpath {
334
335 #define BNX2X_NAPI_WEIGHT 128
336 struct napi_struct napi;
337 union host_hc_status_block status_blk;
338 /* chip independed shortcuts into sb structure */
339 __le16 *sb_index_values;
340 __le16 *sb_running_index;
341 /* chip independed shortcut into rx_prods_offset memory */
342 u32 ustorm_rx_prods_offset;
343
344 dma_addr_t status_blk_mapping;
345
346 struct sw_tx_bd *tx_buf_ring;
347
348 union eth_tx_bd_types *tx_desc_ring;
349 dma_addr_t tx_desc_mapping;
350
351 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
352 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
353
354 struct eth_rx_bd *rx_desc_ring;
355 dma_addr_t rx_desc_mapping;
356
357 union eth_rx_cqe *rx_comp_ring;
358 dma_addr_t rx_comp_mapping;
359
360 /* SGE ring */
361 struct eth_rx_sge *rx_sge_ring;
362 dma_addr_t rx_sge_mapping;
363
364 u64 sge_mask[RX_SGE_MASK_LEN];
365
366 int state;
367 #define BNX2X_FP_STATE_CLOSED 0
368 #define BNX2X_FP_STATE_IRQ 0x80000
369 #define BNX2X_FP_STATE_OPENING 0x90000
370 #define BNX2X_FP_STATE_OPEN 0xa0000
371 #define BNX2X_FP_STATE_HALTING 0xb0000
372 #define BNX2X_FP_STATE_HALTED 0xc0000
373 #define BNX2X_FP_STATE_TERMINATING 0xd0000
374 #define BNX2X_FP_STATE_TERMINATED 0xe0000
375
376 u8 index; /* number in fp array */
377 u8 cl_id; /* eth client id */
378 u8 cl_qzone_id;
379 u8 fw_sb_id; /* status block number in FW */
380 u8 igu_sb_id; /* status block number in HW */
381 u32 cid;
382
383 union db_prod tx_db;
384
385 u16 tx_pkt_prod;
386 u16 tx_pkt_cons;
387 u16 tx_bd_prod;
388 u16 tx_bd_cons;
389 __le16 *tx_cons_sb;
390
391 __le16 fp_hc_idx;
392
393 u16 rx_bd_prod;
394 u16 rx_bd_cons;
395 u16 rx_comp_prod;
396 u16 rx_comp_cons;
397 u16 rx_sge_prod;
398 /* The last maximal completed SGE */
399 u16 last_max_sge;
400 __le16 *rx_cons_sb;
401
402 unsigned long tx_pkt,
403 rx_pkt,
404 rx_calls;
405
406 /* TPA related */
407 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
408 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
409 #define BNX2X_TPA_START 1
410 #define BNX2X_TPA_STOP 2
411 u8 disable_tpa;
412 #ifdef BNX2X_STOP_ON_ERROR
413 u64 tpa_queue_used;
414 #endif
415
416 struct tstorm_per_client_stats old_tclient;
417 struct ustorm_per_client_stats old_uclient;
418 struct xstorm_per_client_stats old_xclient;
419 struct bnx2x_eth_q_stats eth_q_stats;
420
421 /* The size is calculated using the following:
422 sizeof name field from netdev structure +
423 4 ('-Xx-' string) +
424 4 (for the digits and to make it DWORD aligned) */
425 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
426 char name[FP_NAME_SIZE];
427 struct bnx2x *bp; /* parent */
428 };
429
430 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
431 #ifdef BCM_CNIC
432 /* FCoE L2 `fastpath' is right after the eth entries */
433 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
434 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
435 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
436 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
437 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
438 #else
439 #define IS_FCOE_FP(fp) false
440 #define IS_FCOE_IDX(idx) false
441 #endif
442
443
444 /* MC hsi */
445 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
446 #define RX_COPY_THRESH 92
447
448 #define NUM_TX_RINGS 16
449 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
450 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
451 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
452 #define MAX_TX_BD (NUM_TX_BD - 1)
453 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
454 #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL
455 #define INIT_TX_RING_SIZE MAX_TX_AVAIL
456 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
457 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
458 #define TX_BD(x) ((x) & MAX_TX_BD)
459 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
460
461 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
462 #define NUM_RX_RINGS 8
463 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
464 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
465 #define RX_DESC_MASK (RX_DESC_CNT - 1)
466 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
467 #define MAX_RX_BD (NUM_RX_BD - 1)
468 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
469 #define MIN_RX_AVAIL 128
470 #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL
471 #define INIT_RX_RING_SIZE MAX_RX_AVAIL
472 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
473 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
474 #define RX_BD(x) ((x) & MAX_RX_BD)
475
476 /* As long as CQE is 4 times bigger than BD entry we have to allocate
477 4 times more pages for CQ ring in order to keep it balanced with
478 BD ring */
479 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
480 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
481 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
482 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
483 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
484 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
485 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
486 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
487 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
488
489
490 /* This is needed for determining of last_max */
491 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
492
493 #define __SGE_MASK_SET_BIT(el, bit) \
494 do { \
495 el = ((el) | ((u64)0x1 << (bit))); \
496 } while (0)
497
498 #define __SGE_MASK_CLEAR_BIT(el, bit) \
499 do { \
500 el = ((el) & (~((u64)0x1 << (bit)))); \
501 } while (0)
502
503 #define SGE_MASK_SET_BIT(fp, idx) \
504 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
505 ((idx) & RX_SGE_MASK_ELEM_MASK))
506
507 #define SGE_MASK_CLEAR_BIT(fp, idx) \
508 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
509 ((idx) & RX_SGE_MASK_ELEM_MASK))
510
511
512 /* used on a CID received from the HW */
513 #define SW_CID(x) (le32_to_cpu(x) & \
514 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
515 #define CQE_CMD(x) (le32_to_cpu(x) >> \
516 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
517
518 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
519 le32_to_cpu((bd)->addr_lo))
520 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
521
522 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
523 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
524 #define DPM_TRIGER_TYPE 0x40
525 #define DOORBELL(bp, cid, val) \
526 do { \
527 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
528 DPM_TRIGER_TYPE); \
529 } while (0)
530
531
532 /* TX CSUM helpers */
533 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
534 skb->csum_offset)
535 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
536 skb->csum_offset))
537
538 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
539
540 #define XMIT_PLAIN 0
541 #define XMIT_CSUM_V4 0x1
542 #define XMIT_CSUM_V6 0x2
543 #define XMIT_CSUM_TCP 0x4
544 #define XMIT_GSO_V4 0x8
545 #define XMIT_GSO_V6 0x10
546
547 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
548 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
549
550
551 /* stuff added to make the code fit 80Col */
552
553 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
554
555 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
556 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
557 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
558 (TPA_TYPE_START | TPA_TYPE_END))
559
560 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
561
562 #define BNX2X_IP_CSUM_ERR(cqe) \
563 (!((cqe)->fast_path_cqe.status_flags & \
564 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
565 ((cqe)->fast_path_cqe.type_error_flags & \
566 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
567
568 #define BNX2X_L4_CSUM_ERR(cqe) \
569 (!((cqe)->fast_path_cqe.status_flags & \
570 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
571 ((cqe)->fast_path_cqe.type_error_flags & \
572 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
573
574 #define BNX2X_RX_CSUM_OK(cqe) \
575 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
576
577 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
578 (((le16_to_cpu(flags) & \
579 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
580 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
581 == PRS_FLAG_OVERETH_IPV4)
582 #define BNX2X_RX_SUM_FIX(cqe) \
583 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
584
585 #define U_SB_ETH_RX_CQ_INDEX 1
586 #define U_SB_ETH_RX_BD_INDEX 2
587 #define C_SB_ETH_TX_CQ_INDEX 5
588
589 #define BNX2X_RX_SB_INDEX \
590 (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX])
591
592 #define BNX2X_TX_SB_INDEX \
593 (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
594
595 /* end of fast path */
596
597 /* common */
598
599 struct bnx2x_common {
600
601 u32 chip_id;
602 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
603 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
604
605 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
606 #define CHIP_NUM_57710 0x164e
607 #define CHIP_NUM_57711 0x164f
608 #define CHIP_NUM_57711E 0x1650
609 #define CHIP_NUM_57712 0x1662
610 #define CHIP_NUM_57712E 0x1663
611 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
612 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
613 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
614 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
615 #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E)
616 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
617 CHIP_IS_57711E(bp))
618 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
619 CHIP_IS_57712E(bp))
620 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
621 #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp))
622
623 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
624 #define CHIP_REV_Ax 0x00000000
625 /* assume maximum 5 revisions */
626 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
627 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
628 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
629 !(CHIP_REV(bp) & 0x00001000))
630 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
631 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
632 (CHIP_REV(bp) & 0x00001000))
633
634 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
635 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
636
637 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
638 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
639 #define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
640
641 int flash_size;
642 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
643 #define NVRAM_TIMEOUT_COUNT 30000
644 #define NVRAM_PAGE_SIZE 256
645
646 u32 shmem_base;
647 u32 shmem2_base;
648 u32 mf_cfg_base;
649 u32 mf2_cfg_base;
650
651 u32 hw_config;
652
653 u32 bc_ver;
654
655 u8 int_block;
656 #define INT_BLOCK_HC 0
657 #define INT_BLOCK_IGU 1
658 #define INT_BLOCK_MODE_NORMAL 0
659 #define INT_BLOCK_MODE_BW_COMP 2
660 #define CHIP_INT_MODE_IS_NBC(bp) \
661 (CHIP_IS_E2(bp) && \
662 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
663 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
664
665 u8 chip_port_mode;
666 #define CHIP_4_PORT_MODE 0x0
667 #define CHIP_2_PORT_MODE 0x1
668 #define CHIP_PORT_MODE_NONE 0x2
669 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
670 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
671 };
672
673 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
674 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
675 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
676
677 /* end of common */
678
679 /* port */
680
681 struct bnx2x_port {
682 u32 pmf;
683
684 u32 link_config[LINK_CONFIG_SIZE];
685
686 u32 supported[LINK_CONFIG_SIZE];
687 /* link settings - missing defines */
688 #define SUPPORTED_2500baseX_Full (1 << 15)
689
690 u32 advertising[LINK_CONFIG_SIZE];
691 /* link settings - missing defines */
692 #define ADVERTISED_2500baseX_Full (1 << 15)
693
694 u32 phy_addr;
695
696 /* used to synchronize phy accesses */
697 struct mutex phy_mutex;
698 int need_hw_lock;
699
700 u32 port_stx;
701
702 struct nig_stats old_nig_stats;
703 };
704
705 /* end of port */
706
707 /* e1h Classification CAM line allocations */
708 enum {
709 CAM_ETH_LINE = 0,
710 CAM_ISCSI_ETH_LINE,
711 CAM_FIP_ETH_LINE,
712 CAM_FIP_MCAST_LINE,
713 CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE
714 };
715 /* number of MACs per function in NIG memory - used for SI mode */
716 #define NIG_LLH_FUNC_MEM_SIZE 16
717 /* number of entries in NIG_REG_LLHX_FUNC_MEM */
718 #define NIG_LLH_FUNC_MEM_MAX_OFFSET 8
719
720 #define BNX2X_VF_ID_INVALID 0xFF
721
722 /*
723 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
724 * control by the number of fast-path status blocks supported by the
725 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
726 * status block represents an independent interrupts context that can
727 * serve a regular L2 networking queue. However special L2 queues such
728 * as the FCoE queue do not require a FP-SB and other components like
729 * the CNIC may consume FP-SB reducing the number of possible L2 queues
730 *
731 * If the maximum number of FP-SB available is X then:
732 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
733 * regular L2 queues is Y=X-1
734 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
735 * c. If the FCoE L2 queue is supported the actual number of L2 queues
736 * is Y+1
737 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
738 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
739 * FP interrupt context for the CNIC).
740 * e. The number of HW context (CID count) is always X or X+1 if FCoE
741 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
742 */
743
744 #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */
745 #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */
746
747 /*
748 * cid_cnt paramter below refers to the value returned by
749 * 'bnx2x_get_l2_cid_count()' routine
750 */
751
752 /*
753 * The number of FP context allocated by the driver == max number of regular
754 * L2 queues + 1 for the FCoE L2 queue
755 */
756 #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
757
758 /*
759 * The number of FP-SB allocated by the driver == max number of regular L2
760 * queues + 1 for the CNIC which also consumes an FP-SB
761 */
762 #define FP_SB_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE)
763 #define NUM_IGU_SB_REQUIRED(cid_cnt) \
764 (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE)
765
766 union cdu_context {
767 struct eth_context eth;
768 char pad[1024];
769 };
770
771 /* CDU host DB constants */
772 #define CDU_ILT_PAGE_SZ_HW 3
773 #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
774 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
775
776 #ifdef BCM_CNIC
777 #define CNIC_ISCSI_CID_MAX 256
778 #define CNIC_FCOE_CID_MAX 2048
779 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
780 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
781 #endif
782
783 #define QM_ILT_PAGE_SZ_HW 3
784 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */
785 #define QM_CID_ROUND 1024
786
787 #ifdef BCM_CNIC
788 /* TM (timers) host DB constants */
789 #define TM_ILT_PAGE_SZ_HW 2
790 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */
791 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
792 #define TM_CONN_NUM 1024
793 #define TM_ILT_SZ (8 * TM_CONN_NUM)
794 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
795
796 /* SRC (Searcher) host DB constants */
797 #define SRC_ILT_PAGE_SZ_HW 3
798 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */
799 #define SRC_HASH_BITS 10
800 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
801 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
802 #define SRC_T2_SZ SRC_ILT_SZ
803 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
804 #endif
805
806 #define MAX_DMAE_C 8
807
808 /* DMA memory not used in fastpath */
809 struct bnx2x_slowpath {
810 struct eth_stats_query fw_stats;
811 struct mac_configuration_cmd mac_config;
812 struct mac_configuration_cmd mcast_config;
813 struct client_init_ramrod_data client_init_data;
814
815 /* used by dmae command executer */
816 struct dmae_command dmae[MAX_DMAE_C];
817
818 u32 stats_comp;
819 union mac_stats mac_stats;
820 struct nig_stats nig_stats;
821 struct host_port_stats port_stats;
822 struct host_func_stats func_stats;
823 struct host_func_stats func_stats_base;
824
825 u32 wb_comp;
826 u32 wb_data[4];
827 /* pfc configuration for DCBX ramrod */
828 struct flow_control_configuration pfc_config;
829 };
830
831 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
832 #define bnx2x_sp_mapping(bp, var) \
833 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
834
835
836 /* attn group wiring */
837 #define MAX_DYNAMIC_ATTN_GRPS 8
838
839 struct attn_route {
840 u32 sig[5];
841 };
842
843 struct iro {
844 u32 base;
845 u16 m1;
846 u16 m2;
847 u16 m3;
848 u16 size;
849 };
850
851 struct hw_context {
852 union cdu_context *vcxt;
853 dma_addr_t cxt_mapping;
854 size_t size;
855 };
856
857 /* forward */
858 struct bnx2x_ilt;
859
860 typedef enum {
861 BNX2X_RECOVERY_DONE,
862 BNX2X_RECOVERY_INIT,
863 BNX2X_RECOVERY_WAIT,
864 } bnx2x_recovery_state_t;
865
866 /**
867 * Event queue (EQ or event ring) MC hsi
868 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
869 */
870 #define NUM_EQ_PAGES 1
871 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
872 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
873 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
874 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
875 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
876
877 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
878 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
879 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
880
881 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
882 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
883
884 #define BNX2X_EQ_INDEX \
885 (&bp->def_status_blk->sp_sb.\
886 index_values[HC_SP_INDEX_EQ_CONS])
887
888 struct bnx2x {
889 /* Fields used in the tx and intr/napi performance paths
890 * are grouped together in the beginning of the structure
891 */
892 struct bnx2x_fastpath *fp;
893 void __iomem *regview;
894 void __iomem *doorbells;
895 u16 db_size;
896
897 struct net_device *dev;
898 struct pci_dev *pdev;
899
900 struct iro *iro_arr;
901 #define IRO (bp->iro_arr)
902
903 atomic_t intr_sem;
904
905 bnx2x_recovery_state_t recovery_state;
906 int is_leader;
907 struct msix_entry *msix_table;
908 #define INT_MODE_INTx 1
909 #define INT_MODE_MSI 2
910
911 int tx_ring_size;
912
913 u32 rx_csum;
914 u32 rx_buf_size;
915 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
916 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
917 #define ETH_MIN_PACKET_SIZE 60
918 #define ETH_MAX_PACKET_SIZE 1500
919 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
920
921 /* Max supported alignment is 256 (8 shift) */
922 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
923 L1_CACHE_SHIFT : 8)
924 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
925 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
926
927 struct host_sp_status_block *def_status_blk;
928 #define DEF_SB_IGU_ID 16
929 #define DEF_SB_ID HC_SP_SB_ID
930 __le16 def_idx;
931 __le16 def_att_idx;
932 u32 attn_state;
933 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
934
935 /* slow path ring */
936 struct eth_spe *spq;
937 dma_addr_t spq_mapping;
938 u16 spq_prod_idx;
939 struct eth_spe *spq_prod_bd;
940 struct eth_spe *spq_last_bd;
941 __le16 *dsb_sp_prod;
942 atomic_t spq_left; /* serialize spq */
943 /* used to synchronize spq accesses */
944 spinlock_t spq_lock;
945
946 /* event queue */
947 union event_ring_elem *eq_ring;
948 dma_addr_t eq_mapping;
949 u16 eq_prod;
950 u16 eq_cons;
951 __le16 *eq_cons_sb;
952
953 /* Flags for marking that there is a STAT_QUERY or
954 SET_MAC ramrod pending */
955 int stats_pending;
956 int set_mac_pending;
957
958 /* End of fields used in the performance code paths */
959
960 int panic;
961 int msg_enable;
962
963 u32 flags;
964 #define PCIX_FLAG 1
965 #define PCI_32BIT_FLAG 2
966 #define ONE_PORT_FLAG 4
967 #define NO_WOL_FLAG 8
968 #define USING_DAC_FLAG 0x10
969 #define USING_MSIX_FLAG 0x20
970 #define USING_MSI_FLAG 0x40
971
972 #define TPA_ENABLE_FLAG 0x80
973 #define NO_MCP_FLAG 0x100
974 #define DISABLE_MSI_FLAG 0x200
975 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
976 #define MF_FUNC_DIS 0x1000
977 #define FCOE_MACS_SET 0x2000
978 #define NO_FCOE_FLAG 0x4000
979
980 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
981
982 int pf_num; /* absolute PF number */
983 int pfid; /* per-path PF number */
984 int base_fw_ndsb;
985 #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \
986 0 : (bp->pf_num & 1))
987 #define BP_PORT(bp) (bp->pfid & 1)
988 #define BP_FUNC(bp) (bp->pfid)
989 #define BP_ABS_FUNC(bp) (bp->pf_num)
990 #define BP_E1HVN(bp) (bp->pfid >> 1)
991 #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \
992 0 : BP_E1HVN(bp))
993 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
994 #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
995 BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1))
996
997 #ifdef BCM_CNIC
998 #define BCM_CNIC_CID_START 16
999 #define BCM_ISCSI_ETH_CL_ID 17
1000 #endif
1001
1002 int pm_cap;
1003 int pcie_cap;
1004 int mrrs;
1005
1006 struct delayed_work sp_task;
1007 struct delayed_work reset_task;
1008 struct timer_list timer;
1009 int current_interval;
1010
1011 u16 fw_seq;
1012 u16 fw_drv_pulse_wr_seq;
1013 u32 func_stx;
1014
1015 struct link_params link_params;
1016 struct link_vars link_vars;
1017 struct mdio_if_info mdio;
1018
1019 struct bnx2x_common common;
1020 struct bnx2x_port port;
1021
1022 struct cmng_struct_per_port cmng;
1023 u32 vn_weight_sum;
1024
1025 u32 mf_config[E1HVN_MAX];
1026 u32 mf2_config[E2_FUNC_MAX];
1027 u16 mf_ov;
1028 u8 mf_mode;
1029 #define IS_MF(bp) (bp->mf_mode != 0)
1030 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1031 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1032
1033 u8 wol;
1034
1035 int rx_ring_size;
1036
1037 u16 tx_quick_cons_trip_int;
1038 u16 tx_quick_cons_trip;
1039 u16 tx_ticks_int;
1040 u16 tx_ticks;
1041
1042 u16 rx_quick_cons_trip_int;
1043 u16 rx_quick_cons_trip;
1044 u16 rx_ticks_int;
1045 u16 rx_ticks;
1046 /* Maximal coalescing timeout in us */
1047 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1048
1049 u32 lin_cnt;
1050
1051 int state;
1052 #define BNX2X_STATE_CLOSED 0
1053 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1054 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1055 #define BNX2X_STATE_OPEN 0x3000
1056 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1057 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1058 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
1059 #define BNX2X_STATE_FUNC_STARTED 0x7000
1060 #define BNX2X_STATE_DIAG 0xe000
1061 #define BNX2X_STATE_ERROR 0xf000
1062
1063 int multi_mode;
1064 int num_queues;
1065 int disable_tpa;
1066 int int_mode;
1067
1068 struct tstorm_eth_mac_filter_config mac_filters;
1069 #define BNX2X_ACCEPT_NONE 0x0000
1070 #define BNX2X_ACCEPT_UNICAST 0x0001
1071 #define BNX2X_ACCEPT_MULTICAST 0x0002
1072 #define BNX2X_ACCEPT_ALL_UNICAST 0x0004
1073 #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008
1074 #define BNX2X_ACCEPT_BROADCAST 0x0010
1075 #define BNX2X_ACCEPT_UNMATCHED_UCAST 0x0020
1076 #define BNX2X_PROMISCUOUS_MODE 0x10000
1077
1078 u32 rx_mode;
1079 #define BNX2X_RX_MODE_NONE 0
1080 #define BNX2X_RX_MODE_NORMAL 1
1081 #define BNX2X_RX_MODE_ALLMULTI 2
1082 #define BNX2X_RX_MODE_PROMISC 3
1083 #define BNX2X_MAX_MULTICAST 64
1084 #define BNX2X_MAX_EMUL_MULTI 16
1085
1086 u8 igu_dsb_id;
1087 u8 igu_base_sb;
1088 u8 igu_sb_cnt;
1089 dma_addr_t def_status_blk_mapping;
1090
1091 struct bnx2x_slowpath *slowpath;
1092 dma_addr_t slowpath_mapping;
1093 struct hw_context context;
1094
1095 struct bnx2x_ilt *ilt;
1096 #define BP_ILT(bp) ((bp)->ilt)
1097 #define ILT_MAX_LINES 128
1098
1099 int l2_cid_count;
1100 #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
1101 ILT_PAGE_CIDS))
1102 #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
1103
1104 int qm_cid_count;
1105
1106 int dropless_fc;
1107
1108 #ifdef BCM_CNIC
1109 u32 cnic_flags;
1110 #define BNX2X_CNIC_FLAG_MAC_SET 1
1111 void *t2;
1112 dma_addr_t t2_mapping;
1113 struct cnic_ops *cnic_ops;
1114 void *cnic_data;
1115 u32 cnic_tag;
1116 struct cnic_eth_dev cnic_eth_dev;
1117 union host_hc_status_block cnic_sb;
1118 dma_addr_t cnic_sb_mapping;
1119 #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp))
1120 #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb)
1121 struct eth_spe *cnic_kwq;
1122 struct eth_spe *cnic_kwq_prod;
1123 struct eth_spe *cnic_kwq_cons;
1124 struct eth_spe *cnic_kwq_last;
1125 u16 cnic_kwq_pending;
1126 u16 cnic_spq_pending;
1127 struct mutex cnic_mutex;
1128 u8 iscsi_mac[ETH_ALEN];
1129 u8 fip_mac[ETH_ALEN];
1130 #endif
1131
1132 int dmae_ready;
1133 /* used to synchronize dmae accesses */
1134 struct mutex dmae_mutex;
1135
1136 /* used to protect the FW mail box */
1137 struct mutex fw_mb_mutex;
1138
1139 /* used to synchronize stats collecting */
1140 int stats_state;
1141
1142 /* used for synchronization of concurrent threads statistics handling */
1143 spinlock_t stats_lock;
1144
1145 /* used by dmae command loader */
1146 struct dmae_command stats_dmae;
1147 int executer_idx;
1148
1149 u16 stats_counter;
1150 struct bnx2x_eth_stats eth_stats;
1151
1152 struct z_stream_s *strm;
1153 void *gunzip_buf;
1154 dma_addr_t gunzip_mapping;
1155 int gunzip_outlen;
1156 #define FW_BUF_SIZE 0x8000
1157 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1158 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1159 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1160
1161 struct raw_op *init_ops;
1162 /* Init blocks offsets inside init_ops */
1163 u16 *init_ops_offsets;
1164 /* Data blob - has 32 bit granularity */
1165 u32 *init_data;
1166 /* Zipped PRAM blobs - raw data */
1167 const u8 *tsem_int_table_data;
1168 const u8 *tsem_pram_data;
1169 const u8 *usem_int_table_data;
1170 const u8 *usem_pram_data;
1171 const u8 *xsem_int_table_data;
1172 const u8 *xsem_pram_data;
1173 const u8 *csem_int_table_data;
1174 const u8 *csem_pram_data;
1175 #define INIT_OPS(bp) (bp->init_ops)
1176 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1177 #define INIT_DATA(bp) (bp->init_data)
1178 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1179 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1180 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1181 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1182 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1183 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1184 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1185 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1186
1187 char fw_ver[32];
1188 const struct firmware *firmware;
1189 /* LLDP params */
1190 struct bnx2x_config_lldp_params lldp_config_params;
1191
1192 /* DCB support on/off */
1193 u16 dcb_state;
1194 #define BNX2X_DCB_STATE_OFF 0
1195 #define BNX2X_DCB_STATE_ON 1
1196
1197 /* DCBX engine mode */
1198 int dcbx_enabled;
1199 #define BNX2X_DCBX_ENABLED_OFF 0
1200 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1201 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1202 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1203
1204 bool dcbx_mode_uset;
1205
1206 struct bnx2x_config_dcbx_params dcbx_config_params;
1207
1208 struct bnx2x_dcbx_port_params dcbx_port_params;
1209 int dcb_version;
1210
1211 /* DCBX Negotation results */
1212 struct dcbx_features dcbx_local_feat;
1213 u32 dcbx_error;
1214 };
1215
1216 /**
1217 * Init queue/func interface
1218 */
1219 /* queue init flags */
1220 #define QUEUE_FLG_TPA 0x0001
1221 #define QUEUE_FLG_CACHE_ALIGN 0x0002
1222 #define QUEUE_FLG_STATS 0x0004
1223 #define QUEUE_FLG_OV 0x0008
1224 #define QUEUE_FLG_VLAN 0x0010
1225 #define QUEUE_FLG_COS 0x0020
1226 #define QUEUE_FLG_HC 0x0040
1227 #define QUEUE_FLG_DHC 0x0080
1228 #define QUEUE_FLG_OOO 0x0100
1229
1230 #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR
1231 #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR
1232 #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0
1233 #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR
1234
1235
1236
1237 /* rss capabilities */
1238 #define RSS_IPV4_CAP 0x0001
1239 #define RSS_IPV4_TCP_CAP 0x0002
1240 #define RSS_IPV6_CAP 0x0004
1241 #define RSS_IPV6_TCP_CAP 0x0008
1242
1243 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1244 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE)
1245
1246 /* ethtool statistics are displayed for all regular ethernet queues and the
1247 * fcoe L2 queue if not disabled
1248 */
1249 #define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \
1250 (BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE))
1251
1252 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1253
1254 #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
1255
1256 #define RSS_IPV4_CAP_MASK \
1257 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1258
1259 #define RSS_IPV4_TCP_CAP_MASK \
1260 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1261
1262 #define RSS_IPV6_CAP_MASK \
1263 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1264
1265 #define RSS_IPV6_TCP_CAP_MASK \
1266 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1267
1268 /* func init flags */
1269 #define FUNC_FLG_STATS 0x0001
1270 #define FUNC_FLG_TPA 0x0002
1271 #define FUNC_FLG_SPQ 0x0004
1272 #define FUNC_FLG_LEADING 0x0008 /* PF only */
1273
1274 struct rxq_pause_params {
1275 u16 bd_th_lo;
1276 u16 bd_th_hi;
1277 u16 rcq_th_lo;
1278 u16 rcq_th_hi;
1279 u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */
1280 u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */
1281 u16 pri_map;
1282 };
1283
1284 struct bnx2x_rxq_init_params {
1285 /* cxt*/
1286 struct eth_context *cxt;
1287
1288 /* dma */
1289 dma_addr_t dscr_map;
1290 dma_addr_t sge_map;
1291 dma_addr_t rcq_map;
1292 dma_addr_t rcq_np_map;
1293
1294 u16 flags;
1295 u16 drop_flags;
1296 u16 mtu;
1297 u16 buf_sz;
1298 u16 fw_sb_id;
1299 u16 cl_id;
1300 u16 spcl_id;
1301 u16 cl_qzone_id;
1302
1303 /* valid iff QUEUE_FLG_STATS */
1304 u16 stat_id;
1305
1306 /* valid iff QUEUE_FLG_TPA */
1307 u16 tpa_agg_sz;
1308 u16 sge_buf_sz;
1309 u16 max_sges_pkt;
1310
1311 /* valid iff QUEUE_FLG_CACHE_ALIGN */
1312 u8 cache_line_log;
1313
1314 u8 sb_cq_index;
1315 u32 cid;
1316
1317 /* desired interrupts per sec. valid iff QUEUE_FLG_HC */
1318 u32 hc_rate;
1319 };
1320
1321 struct bnx2x_txq_init_params {
1322 /* cxt*/
1323 struct eth_context *cxt;
1324
1325 /* dma */
1326 dma_addr_t dscr_map;
1327
1328 u16 flags;
1329 u16 fw_sb_id;
1330 u8 sb_cq_index;
1331 u8 cos; /* valid iff QUEUE_FLG_COS */
1332 u16 stat_id; /* valid iff QUEUE_FLG_STATS */
1333 u16 traffic_type;
1334 u32 cid;
1335 u16 hc_rate; /* desired interrupts per sec.*/
1336 /* valid iff QUEUE_FLG_HC */
1337
1338 };
1339
1340 struct bnx2x_client_ramrod_params {
1341 int *pstate;
1342 int state;
1343 u16 index;
1344 u16 cl_id;
1345 u32 cid;
1346 u8 poll;
1347 #define CLIENT_IS_FCOE 0x01
1348 #define CLIENT_IS_LEADING_RSS 0x02
1349 u8 flags;
1350 };
1351
1352 struct bnx2x_client_init_params {
1353 struct rxq_pause_params pause;
1354 struct bnx2x_rxq_init_params rxq_params;
1355 struct bnx2x_txq_init_params txq_params;
1356 struct bnx2x_client_ramrod_params ramrod_params;
1357 };
1358
1359 struct bnx2x_rss_params {
1360 int mode;
1361 u16 cap;
1362 u16 result_mask;
1363 };
1364
1365 struct bnx2x_func_init_params {
1366
1367 /* rss */
1368 struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */
1369
1370 /* dma */
1371 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1372 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1373
1374 u16 func_flgs;
1375 u16 func_id; /* abs fid */
1376 u16 pf_id;
1377 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1378 };
1379
1380 #define for_each_eth_queue(bp, var) \
1381 for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1382
1383 #define for_each_nondefault_eth_queue(bp, var) \
1384 for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1385
1386 #define for_each_napi_queue(bp, var) \
1387 for (var = 0; \
1388 var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \
1389 if (skip_queue(bp, var)) \
1390 continue; \
1391 else
1392
1393 #define for_each_queue(bp, var) \
1394 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1395 if (skip_queue(bp, var)) \
1396 continue; \
1397 else
1398
1399 #define for_each_rx_queue(bp, var) \
1400 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1401 if (skip_rx_queue(bp, var)) \
1402 continue; \
1403 else
1404
1405 #define for_each_tx_queue(bp, var) \
1406 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1407 if (skip_tx_queue(bp, var)) \
1408 continue; \
1409 else
1410
1411 #define for_each_nondefault_queue(bp, var) \
1412 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \
1413 if (skip_queue(bp, var)) \
1414 continue; \
1415 else
1416
1417 /* skip rx queue
1418 * if FCOE l2 support is diabled and this is the fcoe L2 queue
1419 */
1420 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1421
1422 /* skip tx queue
1423 * if FCOE l2 support is diabled and this is the fcoe L2 queue
1424 */
1425 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1426
1427 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1428
1429 #define WAIT_RAMROD_POLL 0x01
1430 #define WAIT_RAMROD_COMMON 0x02
1431
1432 /* dmae */
1433 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1434 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1435 u32 len32);
1436 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1437 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1438 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1439 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1440 bool with_comp, u8 comp_type);
1441
1442 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1443 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1444 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1445 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
1446
1447 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1448 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1449 u32 data_hi, u32 data_lo, int common);
1450 void bnx2x_update_coalesce(struct bnx2x *bp);
1451 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1452
1453 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1454 int wait)
1455 {
1456 u32 val;
1457
1458 do {
1459 val = REG_RD(bp, reg);
1460 if (val == expected)
1461 break;
1462 ms -= wait;
1463 msleep(wait);
1464
1465 } while (ms > 0);
1466
1467 return val;
1468 }
1469
1470 #define BNX2X_ILT_ZALLOC(x, y, size) \
1471 do { \
1472 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1473 if (x) \
1474 memset(x, 0, size); \
1475 } while (0)
1476
1477 #define BNX2X_ILT_FREE(x, y, size) \
1478 do { \
1479 if (x) { \
1480 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1481 x = NULL; \
1482 y = 0; \
1483 } \
1484 } while (0)
1485
1486 #define ILOG2(x) (ilog2((x)))
1487
1488 #define ILT_NUM_PAGE_ENTRIES (3072)
1489 /* In 57710/11 we use whole table since we have 8 func
1490 * In 57712 we have only 4 func, but use same size per func, then only half of
1491 * the table in use
1492 */
1493 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1494
1495 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1496 /*
1497 * the phys address is shifted right 12 bits and has an added
1498 * 1=valid bit added to the 53rd bit
1499 * then since this is a wide register(TM)
1500 * we split it into two 32 bit writes
1501 */
1502 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1503 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1504
1505 /* load/unload mode */
1506 #define LOAD_NORMAL 0
1507 #define LOAD_OPEN 1
1508 #define LOAD_DIAG 2
1509 #define UNLOAD_NORMAL 0
1510 #define UNLOAD_CLOSE 1
1511 #define UNLOAD_RECOVERY 2
1512
1513
1514 /* DMAE command defines */
1515 #define DMAE_TIMEOUT -1
1516 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1517 #define DMAE_NOT_RDY -3
1518 #define DMAE_PCI_ERR_FLAG 0x80000000
1519
1520 #define DMAE_SRC_PCI 0
1521 #define DMAE_SRC_GRC 1
1522
1523 #define DMAE_DST_NONE 0
1524 #define DMAE_DST_PCI 1
1525 #define DMAE_DST_GRC 2
1526
1527 #define DMAE_COMP_PCI 0
1528 #define DMAE_COMP_GRC 1
1529
1530 /* E2 and onward - PCI error handling in the completion */
1531
1532 #define DMAE_COMP_REGULAR 0
1533 #define DMAE_COM_SET_ERR 1
1534
1535 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1536 DMAE_COMMAND_SRC_SHIFT)
1537 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1538 DMAE_COMMAND_SRC_SHIFT)
1539
1540 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1541 DMAE_COMMAND_DST_SHIFT)
1542 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1543 DMAE_COMMAND_DST_SHIFT)
1544
1545 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1546 DMAE_COMMAND_C_DST_SHIFT)
1547 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1548 DMAE_COMMAND_C_DST_SHIFT)
1549
1550 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1551
1552 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1553 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1554 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1555 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1556
1557 #define DMAE_CMD_PORT_0 0
1558 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1559
1560 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1561 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1562 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1563
1564 #define DMAE_SRC_PF 0
1565 #define DMAE_SRC_VF 1
1566
1567 #define DMAE_DST_PF 0
1568 #define DMAE_DST_VF 1
1569
1570 #define DMAE_C_SRC 0
1571 #define DMAE_C_DST 1
1572
1573 #define DMAE_LEN32_RD_MAX 0x80
1574 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1575
1576 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1577 indicates eror */
1578
1579 #define MAX_DMAE_C_PER_PORT 8
1580 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1581 BP_E1HVN(bp))
1582 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1583 E1HVN_MAX)
1584
1585 /* PCIE link and speed */
1586 #define PCICFG_LINK_WIDTH 0x1f00000
1587 #define PCICFG_LINK_WIDTH_SHIFT 20
1588 #define PCICFG_LINK_SPEED 0xf0000
1589 #define PCICFG_LINK_SPEED_SHIFT 16
1590
1591
1592 #define BNX2X_NUM_TESTS 7
1593
1594 #define BNX2X_PHY_LOOPBACK 0
1595 #define BNX2X_MAC_LOOPBACK 1
1596 #define BNX2X_PHY_LOOPBACK_FAILED 1
1597 #define BNX2X_MAC_LOOPBACK_FAILED 2
1598 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1599 BNX2X_PHY_LOOPBACK_FAILED)
1600
1601
1602 #define STROM_ASSERT_ARRAY_SIZE 50
1603
1604
1605 /* must be used on a CID before placing it on a HW ring */
1606 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1607 (BP_E1HVN(bp) << 17) | (x))
1608
1609 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1610 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1611
1612
1613 #define BNX2X_BTR 4
1614 #define MAX_SPQ_PENDING 8
1615
1616
1617 /* CMNG constants
1618 derived from lab experiments, and not from system spec calculations !!! */
1619 #define DEF_MIN_RATE 100
1620 /* resolution of the rate shaping timer - 100 usec */
1621 #define RS_PERIODIC_TIMEOUT_USEC 100
1622 /* resolution of fairness algorithm in usecs -
1623 coefficient for calculating the actual t fair */
1624 #define T_FAIR_COEF 10000000
1625 /* number of bytes in single QM arbitration cycle -
1626 coefficient for calculating the fairness timer */
1627 #define QM_ARB_BYTES 40000
1628 #define FAIR_MEM 2
1629
1630
1631 #define ATTN_NIG_FOR_FUNC (1L << 8)
1632 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1633 #define GPIO_2_FUNC (1L << 10)
1634 #define GPIO_3_FUNC (1L << 11)
1635 #define GPIO_4_FUNC (1L << 12)
1636 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1637 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1638 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1639 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1640 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1641 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1642
1643 #define ATTN_HARD_WIRED_MASK 0xff00
1644 #define ATTENTION_ID 4
1645
1646
1647 /* stuff added to make the code fit 80Col */
1648
1649 #define BNX2X_PMF_LINK_ASSERT \
1650 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1651
1652 #define BNX2X_MC_ASSERT_BITS \
1653 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1654 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1655 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1656 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1657
1658 #define BNX2X_MCP_ASSERT \
1659 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1660
1661 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1662 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1663 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1664 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1665 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1666 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1667 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1668
1669 #define HW_INTERRUT_ASSERT_SET_0 \
1670 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1671 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1672 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1673 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1674 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1675 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1676 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1677 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1678 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1679 #define HW_INTERRUT_ASSERT_SET_1 \
1680 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1681 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1682 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1683 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1684 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1685 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1686 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1687 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1688 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1689 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1690 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1691 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1692 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1693 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1694 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1695 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1696 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1697 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1698 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1699 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1700 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1701 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1702 #define HW_INTERRUT_ASSERT_SET_2 \
1703 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1704 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1705 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1706 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1707 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1708 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1709 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1710 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1711 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1712 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1713 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1714 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1715
1716 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1717 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1718 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1719 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1720
1721 #define RSS_FLAGS(bp) \
1722 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1723 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1724 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1725 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1726 (bp->multi_mode << \
1727 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1728 #define MULTI_MASK 0x7f
1729
1730 #define BNX2X_SP_DSB_INDEX \
1731 (&bp->def_status_blk->sp_sb.\
1732 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1733
1734 #define SET_FLAG(value, mask, flag) \
1735 do {\
1736 (value) &= ~(mask);\
1737 (value) |= ((flag) << (mask##_SHIFT));\
1738 } while (0)
1739
1740 #define GET_FLAG(value, mask) \
1741 (((value) &= (mask)) >> (mask##_SHIFT))
1742
1743 #define GET_FIELD(value, fname) \
1744 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
1745
1746 #define CAM_IS_INVALID(x) \
1747 (GET_FLAG(x.flags, \
1748 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1749 (T_ETH_MAC_COMMAND_INVALIDATE))
1750
1751 /* Number of u32 elements in MC hash array */
1752 #define MC_HASH_SIZE 8
1753 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1754 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1755
1756
1757 #ifndef PXP2_REG_PXP2_INT_STS
1758 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1759 #endif
1760
1761 #ifndef ETH_MAX_RX_CLIENTS_E2
1762 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
1763 #endif
1764
1765 #define BNX2X_VPD_LEN 128
1766 #define VENDOR_ID_LEN 4
1767
1768 /* Congestion management fairness mode */
1769 #define CMNG_FNS_NONE 0
1770 #define CMNG_FNS_MINMAX 1
1771
1772 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1773 #define HC_SEG_ACCESS_ATTN 4
1774 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1775
1776 #ifdef BNX2X_MAIN
1777 #define BNX2X_EXTERN
1778 #else
1779 #define BNX2X_EXTERN extern
1780 #endif
1781
1782 BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */
1783
1784 extern void bnx2x_set_ethtool_ops(struct net_device *netdev);
1785
1786 #endif /* bnx2x.h */
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