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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / e1000e / lib.c
blobff2872153b211dfdc447c9a82b133ce44479aa85
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000.h"
30
31 enum e1000_mng_mode {
32 e1000_mng_mode_none = 0,
33 e1000_mng_mode_asf,
34 e1000_mng_mode_pt,
35 e1000_mng_mode_ipmi,
36 e1000_mng_mode_host_if_only
37 };
38
39 #define E1000_FACTPS_MNGCG 0x20000000
40
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
43
44 /**
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
47 *
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
51 **/
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
53 {
54 struct e1000_mac_info *mac = &hw->mac;
55 struct e1000_bus_info *bus = &hw->bus;
56 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, cap_offset;
58
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
60 if (!cap_offset) {
61 bus->width = e1000_bus_width_unknown;
62 } else {
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
65 &pcie_link_status);
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
69 }
70
71 mac->ops.set_lan_id(hw);
72
73 return 0;
74 }
75
76 /**
77 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
78 *
79 * @hw: pointer to the HW structure
80 *
81 * Determines the LAN function id by reading memory-mapped registers
82 * and swaps the port value if requested.
83 **/
84 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
85 {
86 struct e1000_bus_info *bus = &hw->bus;
87 u32 reg;
88
89 /*
90 * The status register reports the correct function number
91 * for the device regardless of function swap state.
92 */
93 reg = er32(STATUS);
94 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
95 }
96
97 /**
98 * e1000_set_lan_id_single_port - Set LAN id for a single port device
99 * @hw: pointer to the HW structure
100 *
101 * Sets the LAN function id to zero for a single port device.
102 **/
103 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
104 {
105 struct e1000_bus_info *bus = &hw->bus;
106
107 bus->func = 0;
108 }
109
110 /**
111 * e1000_clear_vfta_generic - Clear VLAN filter table
112 * @hw: pointer to the HW structure
113 *
114 * Clears the register array which contains the VLAN filter table by
115 * setting all the values to 0.
116 **/
117 void e1000_clear_vfta_generic(struct e1000_hw *hw)
118 {
119 u32 offset;
120
121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
123 e1e_flush();
124 }
125 }
126
127 /**
128 * e1000_write_vfta_generic - Write value to VLAN filter table
129 * @hw: pointer to the HW structure
130 * @offset: register offset in VLAN filter table
131 * @value: register value written to VLAN filter table
132 *
133 * Writes value at the given offset in the register array which stores
134 * the VLAN filter table.
135 **/
136 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
137 {
138 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
139 e1e_flush();
140 }
141
142 /**
143 * e1000e_init_rx_addrs - Initialize receive address's
144 * @hw: pointer to the HW structure
145 * @rar_count: receive address registers
146 *
147 * Setups the receive address registers by setting the base receive address
148 * register to the devices MAC address and clearing all the other receive
149 * address registers to 0.
150 **/
151 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
152 {
153 u32 i;
154 u8 mac_addr[ETH_ALEN] = {0};
155
156 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n");
158
159 e1000e_rar_set(hw, hw->mac.addr, 0);
160
161 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
163 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i);
165 }
166
167 /**
168 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
169 * @hw: pointer to the HW structure
170 *
171 * Checks the nvm for an alternate MAC address. An alternate MAC address
172 * can be setup by pre-boot software and must be treated like a permanent
173 * address and must override the actual permanent MAC address. If an
174 * alternate MAC address is found it is programmed into RAR0, replacing
175 * the permanent address that was installed into RAR0 by the Si on reset.
176 * This function will return SUCCESS unless it encounters an error while
177 * reading the EEPROM.
178 **/
179 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
180 {
181 u32 i;
182 s32 ret_val = 0;
183 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
184 u8 alt_mac_addr[ETH_ALEN];
185
186 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
187 if (ret_val)
188 goto out;
189
190 /* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
191 if (!((nvm_data & NVM_COMPAT_LOM) ||
192 (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
193 (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)))
194 goto out;
195
196 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
197 &nvm_alt_mac_addr_offset);
198 if (ret_val) {
199 e_dbg("NVM Read Error\n");
200 goto out;
201 }
202
203 if (nvm_alt_mac_addr_offset == 0xFFFF) {
204 /* There is no Alternate MAC Address */
205 goto out;
206 }
207
208 if (hw->bus.func == E1000_FUNC_1)
209 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
210 for (i = 0; i < ETH_ALEN; i += 2) {
211 offset = nvm_alt_mac_addr_offset + (i >> 1);
212 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
213 if (ret_val) {
214 e_dbg("NVM Read Error\n");
215 goto out;
216 }
217
218 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
219 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
220 }
221
222 /* if multicast bit is set, the alternate address will not be used */
223 if (alt_mac_addr[0] & 0x01) {
224 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
225 goto out;
226 }
227
228 /*
229 * We have a valid alternate MAC address, and we want to treat it the
230 * same as the normal permanent MAC address stored by the HW into the
231 * RAR. Do this by mapping this address into RAR0.
232 */
233 e1000e_rar_set(hw, alt_mac_addr, 0);
234
235 out:
236 return ret_val;
237 }
238
239 /**
240 * e1000e_rar_set - Set receive address register
241 * @hw: pointer to the HW structure
242 * @addr: pointer to the receive address
243 * @index: receive address array register
244 *
245 * Sets the receive address array register at index to the address passed
246 * in by addr.
247 **/
248 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
249 {
250 u32 rar_low, rar_high;
251
252 /*
253 * HW expects these in little endian so we reverse the byte order
254 * from network order (big endian) to little endian
255 */
256 rar_low = ((u32) addr[0] |
257 ((u32) addr[1] << 8) |
258 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
259
260 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
261
262 /* If MAC address zero, no need to set the AV bit */
263 if (rar_low || rar_high)
264 rar_high |= E1000_RAH_AV;
265
266 /*
267 * Some bridges will combine consecutive 32-bit writes into
268 * a single burst write, which will malfunction on some parts.
269 * The flushes avoid this.
270 */
271 ew32(RAL(index), rar_low);
272 e1e_flush();
273 ew32(RAH(index), rar_high);
274 e1e_flush();
275 }
276
277 /**
278 * e1000_hash_mc_addr - Generate a multicast hash value
279 * @hw: pointer to the HW structure
280 * @mc_addr: pointer to a multicast address
281 *
282 * Generates a multicast address hash value which is used to determine
283 * the multicast filter table array address and new table value. See
284 * e1000_mta_set_generic()
285 **/
286 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
287 {
288 u32 hash_value, hash_mask;
289 u8 bit_shift = 0;
290
291 /* Register count multiplied by bits per register */
292 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
293
294 /*
295 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
296 * where 0xFF would still fall within the hash mask.
297 */
298 while (hash_mask >> bit_shift != 0xFF)
299 bit_shift++;
300
301 /*
302 * The portion of the address that is used for the hash table
303 * is determined by the mc_filter_type setting.
304 * The algorithm is such that there is a total of 8 bits of shifting.
305 * The bit_shift for a mc_filter_type of 0 represents the number of
306 * left-shifts where the MSB of mc_addr[5] would still fall within
307 * the hash_mask. Case 0 does this exactly. Since there are a total
308 * of 8 bits of shifting, then mc_addr[4] will shift right the
309 * remaining number of bits. Thus 8 - bit_shift. The rest of the
310 * cases are a variation of this algorithm...essentially raising the
311 * number of bits to shift mc_addr[5] left, while still keeping the
312 * 8-bit shifting total.
313 *
314 * For example, given the following Destination MAC Address and an
315 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
316 * we can see that the bit_shift for case 0 is 4. These are the hash
317 * values resulting from each mc_filter_type...
318 * [0] [1] [2] [3] [4] [5]
319 * 01 AA 00 12 34 56
320 * LSB MSB
321 *
322 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
323 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
324 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
325 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
326 */
327 switch (hw->mac.mc_filter_type) {
328 default:
329 case 0:
330 break;
331 case 1:
332 bit_shift += 1;
333 break;
334 case 2:
335 bit_shift += 2;
336 break;
337 case 3:
338 bit_shift += 4;
339 break;
340 }
341
342 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
343 (((u16) mc_addr[5]) << bit_shift)));
344
345 return hash_value;
346 }
347
348 /**
349 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
350 * @hw: pointer to the HW structure
351 * @mc_addr_list: array of multicast addresses to program
352 * @mc_addr_count: number of multicast addresses to program
353 *
354 * Updates entire Multicast Table Array.
355 * The caller must have a packed mc_addr_list of multicast addresses.
356 **/
357 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
358 u8 *mc_addr_list, u32 mc_addr_count)
359 {
360 u32 hash_value, hash_bit, hash_reg;
361 int i;
362
363 /* clear mta_shadow */
364 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
365
366 /* update mta_shadow from mc_addr_list */
367 for (i = 0; (u32) i < mc_addr_count; i++) {
368 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
369
370 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
371 hash_bit = hash_value & 0x1F;
372
373 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
374 mc_addr_list += (ETH_ALEN);
375 }
376
377 /* replace the entire MTA table */
378 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
379 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
380 e1e_flush();
381 }
382
383 /**
384 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
385 * @hw: pointer to the HW structure
386 *
387 * Clears the base hardware counters by reading the counter registers.
388 **/
389 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
390 {
391 er32(CRCERRS);
392 er32(SYMERRS);
393 er32(MPC);
394 er32(SCC);
395 er32(ECOL);
396 er32(MCC);
397 er32(LATECOL);
398 er32(COLC);
399 er32(DC);
400 er32(SEC);
401 er32(RLEC);
402 er32(XONRXC);
403 er32(XONTXC);
404 er32(XOFFRXC);
405 er32(XOFFTXC);
406 er32(FCRUC);
407 er32(GPRC);
408 er32(BPRC);
409 er32(MPRC);
410 er32(GPTC);
411 er32(GORCL);
412 er32(GORCH);
413 er32(GOTCL);
414 er32(GOTCH);
415 er32(RNBC);
416 er32(RUC);
417 er32(RFC);
418 er32(ROC);
419 er32(RJC);
420 er32(TORL);
421 er32(TORH);
422 er32(TOTL);
423 er32(TOTH);
424 er32(TPR);
425 er32(TPT);
426 er32(MPTC);
427 er32(BPTC);
428 }
429
430 /**
431 * e1000e_check_for_copper_link - Check for link (Copper)
432 * @hw: pointer to the HW structure
433 *
434 * Checks to see of the link status of the hardware has changed. If a
435 * change in link status has been detected, then we read the PHY registers
436 * to get the current speed/duplex if link exists.
437 **/
438 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
439 {
440 struct e1000_mac_info *mac = &hw->mac;
441 s32 ret_val;
442 bool link;
443
444 /*
445 * We only want to go out to the PHY registers to see if Auto-Neg
446 * has completed and/or if our link status has changed. The
447 * get_link_status flag is set upon receiving a Link Status
448 * Change or Rx Sequence Error interrupt.
449 */
450 if (!mac->get_link_status)
451 return 0;
452
453 /*
454 * First we want to see if the MII Status Register reports
455 * link. If so, then we want to get the current speed/duplex
456 * of the PHY.
457 */
458 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
459 if (ret_val)
460 return ret_val;
461
462 if (!link)
463 return ret_val; /* No link detected */
464
465 mac->get_link_status = false;
466
467 /*
468 * Check if there was DownShift, must be checked
469 * immediately after link-up
470 */
471 e1000e_check_downshift(hw);
472
473 /*
474 * If we are forcing speed/duplex, then we simply return since
475 * we have already determined whether we have link or not.
476 */
477 if (!mac->autoneg) {
478 ret_val = -E1000_ERR_CONFIG;
479 return ret_val;
480 }
481
482 /*
483 * Auto-Neg is enabled. Auto Speed Detection takes care
484 * of MAC speed/duplex configuration. So we only need to
485 * configure Collision Distance in the MAC.
486 */
487 e1000e_config_collision_dist(hw);
488
489 /*
490 * Configure Flow Control now that Auto-Neg has completed.
491 * First, we need to restore the desired flow control
492 * settings because we may have had to re-autoneg with a
493 * different link partner.
494 */
495 ret_val = e1000e_config_fc_after_link_up(hw);
496 if (ret_val)
497 e_dbg("Error configuring flow control\n");
498
499 return ret_val;
500 }
501
502 /**
503 * e1000e_check_for_fiber_link - Check for link (Fiber)
504 * @hw: pointer to the HW structure
505 *
506 * Checks for link up on the hardware. If link is not up and we have
507 * a signal, then we need to force link up.
508 **/
509 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
510 {
511 struct e1000_mac_info *mac = &hw->mac;
512 u32 rxcw;
513 u32 ctrl;
514 u32 status;
515 s32 ret_val;
516
517 ctrl = er32(CTRL);
518 status = er32(STATUS);
519 rxcw = er32(RXCW);
520
521 /*
522 * If we don't have link (auto-negotiation failed or link partner
523 * cannot auto-negotiate), the cable is plugged in (we have signal),
524 * and our link partner is not trying to auto-negotiate with us (we
525 * are receiving idles or data), we need to force link up. We also
526 * need to give auto-negotiation time to complete, in case the cable
527 * was just plugged in. The autoneg_failed flag does this.
528 */
529 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
530 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
531 (!(rxcw & E1000_RXCW_C))) {
532 if (mac->autoneg_failed == 0) {
533 mac->autoneg_failed = 1;
534 return 0;
535 }
536 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
537
538 /* Disable auto-negotiation in the TXCW register */
539 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
540
541 /* Force link-up and also force full-duplex. */
542 ctrl = er32(CTRL);
543 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
544 ew32(CTRL, ctrl);
545
546 /* Configure Flow Control after forcing link up. */
547 ret_val = e1000e_config_fc_after_link_up(hw);
548 if (ret_val) {
549 e_dbg("Error configuring flow control\n");
550 return ret_val;
551 }
552 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
553 /*
554 * If we are forcing link and we are receiving /C/ ordered
555 * sets, re-enable auto-negotiation in the TXCW register
556 * and disable forced link in the Device Control register
557 * in an attempt to auto-negotiate with our link partner.
558 */
559 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
560 ew32(TXCW, mac->txcw);
561 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
562
563 mac->serdes_has_link = true;
564 }
565
566 return 0;
567 }
568
569 /**
570 * e1000e_check_for_serdes_link - Check for link (Serdes)
571 * @hw: pointer to the HW structure
572 *
573 * Checks for link up on the hardware. If link is not up and we have
574 * a signal, then we need to force link up.
575 **/
576 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
577 {
578 struct e1000_mac_info *mac = &hw->mac;
579 u32 rxcw;
580 u32 ctrl;
581 u32 status;
582 s32 ret_val;
583
584 ctrl = er32(CTRL);
585 status = er32(STATUS);
586 rxcw = er32(RXCW);
587
588 /*
589 * If we don't have link (auto-negotiation failed or link partner
590 * cannot auto-negotiate), and our link partner is not trying to
591 * auto-negotiate with us (we are receiving idles or data),
592 * we need to force link up. We also need to give auto-negotiation
593 * time to complete.
594 */
595 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
596 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
597 if (mac->autoneg_failed == 0) {
598 mac->autoneg_failed = 1;
599 return 0;
600 }
601 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
602
603 /* Disable auto-negotiation in the TXCW register */
604 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
605
606 /* Force link-up and also force full-duplex. */
607 ctrl = er32(CTRL);
608 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
609 ew32(CTRL, ctrl);
610
611 /* Configure Flow Control after forcing link up. */
612 ret_val = e1000e_config_fc_after_link_up(hw);
613 if (ret_val) {
614 e_dbg("Error configuring flow control\n");
615 return ret_val;
616 }
617 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
618 /*
619 * If we are forcing link and we are receiving /C/ ordered
620 * sets, re-enable auto-negotiation in the TXCW register
621 * and disable forced link in the Device Control register
622 * in an attempt to auto-negotiate with our link partner.
623 */
624 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
625 ew32(TXCW, mac->txcw);
626 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
627
628 mac->serdes_has_link = true;
629 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
630 /*
631 * If we force link for non-auto-negotiation switch, check
632 * link status based on MAC synchronization for internal
633 * serdes media type.
634 */
635 /* SYNCH bit and IV bit are sticky. */
636 udelay(10);
637 rxcw = er32(RXCW);
638 if (rxcw & E1000_RXCW_SYNCH) {
639 if (!(rxcw & E1000_RXCW_IV)) {
640 mac->serdes_has_link = true;
641 e_dbg("SERDES: Link up - forced.\n");
642 }
643 } else {
644 mac->serdes_has_link = false;
645 e_dbg("SERDES: Link down - force failed.\n");
646 }
647 }
648
649 if (E1000_TXCW_ANE & er32(TXCW)) {
650 status = er32(STATUS);
651 if (status & E1000_STATUS_LU) {
652 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
653 udelay(10);
654 rxcw = er32(RXCW);
655 if (rxcw & E1000_RXCW_SYNCH) {
656 if (!(rxcw & E1000_RXCW_IV)) {
657 mac->serdes_has_link = true;
658 e_dbg("SERDES: Link up - autoneg "
659 "completed successfully.\n");
660 } else {
661 mac->serdes_has_link = false;
662 e_dbg("SERDES: Link down - invalid"
663 "codewords detected in autoneg.\n");
664 }
665 } else {
666 mac->serdes_has_link = false;
667 e_dbg("SERDES: Link down - no sync.\n");
668 }
669 } else {
670 mac->serdes_has_link = false;
671 e_dbg("SERDES: Link down - autoneg failed\n");
672 }
673 }
674
675 return 0;
676 }
677
678 /**
679 * e1000_set_default_fc_generic - Set flow control default values
680 * @hw: pointer to the HW structure
681 *
682 * Read the EEPROM for the default values for flow control and store the
683 * values.
684 **/
685 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
686 {
687 s32 ret_val;
688 u16 nvm_data;
689
690 /*
691 * Read and store word 0x0F of the EEPROM. This word contains bits
692 * that determine the hardware's default PAUSE (flow control) mode,
693 * a bit that determines whether the HW defaults to enabling or
694 * disabling auto-negotiation, and the direction of the
695 * SW defined pins. If there is no SW over-ride of the flow
696 * control setting, then the variable hw->fc will
697 * be initialized based on a value in the EEPROM.
698 */
699 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
700
701 if (ret_val) {
702 e_dbg("NVM Read Error\n");
703 return ret_val;
704 }
705
706 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
707 hw->fc.requested_mode = e1000_fc_none;
708 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
709 NVM_WORD0F_ASM_DIR)
710 hw->fc.requested_mode = e1000_fc_tx_pause;
711 else
712 hw->fc.requested_mode = e1000_fc_full;
713
714 return 0;
715 }
716
717 /**
718 * e1000e_setup_link - Setup flow control and link settings
719 * @hw: pointer to the HW structure
720 *
721 * Determines which flow control settings to use, then configures flow
722 * control. Calls the appropriate media-specific link configuration
723 * function. Assuming the adapter has a valid link partner, a valid link
724 * should be established. Assumes the hardware has previously been reset
725 * and the transmitter and receiver are not enabled.
726 **/
727 s32 e1000e_setup_link(struct e1000_hw *hw)
728 {
729 struct e1000_mac_info *mac = &hw->mac;
730 s32 ret_val;
731
732 /*
733 * In the case of the phy reset being blocked, we already have a link.
734 * We do not need to set it up again.
735 */
736 if (e1000_check_reset_block(hw))
737 return 0;
738
739 /*
740 * If requested flow control is set to default, set flow control
741 * based on the EEPROM flow control settings.
742 */
743 if (hw->fc.requested_mode == e1000_fc_default) {
744 ret_val = e1000_set_default_fc_generic(hw);
745 if (ret_val)
746 return ret_val;
747 }
748
749 /*
750 * Save off the requested flow control mode for use later. Depending
751 * on the link partner's capabilities, we may or may not use this mode.
752 */
753 hw->fc.current_mode = hw->fc.requested_mode;
754
755 e_dbg("After fix-ups FlowControl is now = %x\n",
756 hw->fc.current_mode);
757
758 /* Call the necessary media_type subroutine to configure the link. */
759 ret_val = mac->ops.setup_physical_interface(hw);
760 if (ret_val)
761 return ret_val;
762
763 /*
764 * Initialize the flow control address, type, and PAUSE timer
765 * registers to their default values. This is done even if flow
766 * control is disabled, because it does not hurt anything to
767 * initialize these registers.
768 */
769 e_dbg("Initializing the Flow Control address, type and timer regs\n");
770 ew32(FCT, FLOW_CONTROL_TYPE);
771 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
772 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
773
774 ew32(FCTTV, hw->fc.pause_time);
775
776 return e1000e_set_fc_watermarks(hw);
777 }
778
779 /**
780 * e1000_commit_fc_settings_generic - Configure flow control
781 * @hw: pointer to the HW structure
782 *
783 * Write the flow control settings to the Transmit Config Word Register (TXCW)
784 * base on the flow control settings in e1000_mac_info.
785 **/
786 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
787 {
788 struct e1000_mac_info *mac = &hw->mac;
789 u32 txcw;
790
791 /*
792 * Check for a software override of the flow control settings, and
793 * setup the device accordingly. If auto-negotiation is enabled, then
794 * software will have to set the "PAUSE" bits to the correct value in
795 * the Transmit Config Word Register (TXCW) and re-start auto-
796 * negotiation. However, if auto-negotiation is disabled, then
797 * software will have to manually configure the two flow control enable
798 * bits in the CTRL register.
799 *
800 * The possible values of the "fc" parameter are:
801 * 0: Flow control is completely disabled
802 * 1: Rx flow control is enabled (we can receive pause frames,
803 * but not send pause frames).
804 * 2: Tx flow control is enabled (we can send pause frames but we
805 * do not support receiving pause frames).
806 * 3: Both Rx and Tx flow control (symmetric) are enabled.
807 */
808 switch (hw->fc.current_mode) {
809 case e1000_fc_none:
810 /* Flow control completely disabled by a software over-ride. */
811 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
812 break;
813 case e1000_fc_rx_pause:
814 /*
815 * Rx Flow control is enabled and Tx Flow control is disabled
816 * by a software over-ride. Since there really isn't a way to
817 * advertise that we are capable of Rx Pause ONLY, we will
818 * advertise that we support both symmetric and asymmetric Rx
819 * PAUSE. Later, we will disable the adapter's ability to send
820 * PAUSE frames.
821 */
822 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
823 break;
824 case e1000_fc_tx_pause:
825 /*
826 * Tx Flow control is enabled, and Rx Flow control is disabled,
827 * by a software over-ride.
828 */
829 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
830 break;
831 case e1000_fc_full:
832 /*
833 * Flow control (both Rx and Tx) is enabled by a software
834 * over-ride.
835 */
836 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
837 break;
838 default:
839 e_dbg("Flow control param set incorrectly\n");
840 return -E1000_ERR_CONFIG;
841 break;
842 }
843
844 ew32(TXCW, txcw);
845 mac->txcw = txcw;
846
847 return 0;
848 }
849
850 /**
851 * e1000_poll_fiber_serdes_link_generic - Poll for link up
852 * @hw: pointer to the HW structure
853 *
854 * Polls for link up by reading the status register, if link fails to come
855 * up with auto-negotiation, then the link is forced if a signal is detected.
856 **/
857 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
858 {
859 struct e1000_mac_info *mac = &hw->mac;
860 u32 i, status;
861 s32 ret_val;
862
863 /*
864 * If we have a signal (the cable is plugged in, or assumed true for
865 * serdes media) then poll for a "Link-Up" indication in the Device
866 * Status Register. Time-out if a link isn't seen in 500 milliseconds
867 * seconds (Auto-negotiation should complete in less than 500
868 * milliseconds even if the other end is doing it in SW).
869 */
870 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
871 msleep(10);
872 status = er32(STATUS);
873 if (status & E1000_STATUS_LU)
874 break;
875 }
876 if (i == FIBER_LINK_UP_LIMIT) {
877 e_dbg("Never got a valid link from auto-neg!!!\n");
878 mac->autoneg_failed = 1;
879 /*
880 * AutoNeg failed to achieve a link, so we'll call
881 * mac->check_for_link. This routine will force the
882 * link up if we detect a signal. This will allow us to
883 * communicate with non-autonegotiating link partners.
884 */
885 ret_val = mac->ops.check_for_link(hw);
886 if (ret_val) {
887 e_dbg("Error while checking for link\n");
888 return ret_val;
889 }
890 mac->autoneg_failed = 0;
891 } else {
892 mac->autoneg_failed = 0;
893 e_dbg("Valid Link Found\n");
894 }
895
896 return 0;
897 }
898
899 /**
900 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
901 * @hw: pointer to the HW structure
902 *
903 * Configures collision distance and flow control for fiber and serdes
904 * links. Upon successful setup, poll for link.
905 **/
906 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
907 {
908 u32 ctrl;
909 s32 ret_val;
910
911 ctrl = er32(CTRL);
912
913 /* Take the link out of reset */
914 ctrl &= ~E1000_CTRL_LRST;
915
916 e1000e_config_collision_dist(hw);
917
918 ret_val = e1000_commit_fc_settings_generic(hw);
919 if (ret_val)
920 return ret_val;
921
922 /*
923 * Since auto-negotiation is enabled, take the link out of reset (the
924 * link will be in reset, because we previously reset the chip). This
925 * will restart auto-negotiation. If auto-negotiation is successful
926 * then the link-up status bit will be set and the flow control enable
927 * bits (RFCE and TFCE) will be set according to their negotiated value.
928 */
929 e_dbg("Auto-negotiation enabled\n");
930
931 ew32(CTRL, ctrl);
932 e1e_flush();
933 msleep(1);
934
935 /*
936 * For these adapters, the SW definable pin 1 is set when the optics
937 * detect a signal. If we have a signal, then poll for a "Link-Up"
938 * indication.
939 */
940 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
941 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
942 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
943 } else {
944 e_dbg("No signal detected\n");
945 }
946
947 return 0;
948 }
949
950 /**
951 * e1000e_config_collision_dist - Configure collision distance
952 * @hw: pointer to the HW structure
953 *
954 * Configures the collision distance to the default value and is used
955 * during link setup. Currently no func pointer exists and all
956 * implementations are handled in the generic version of this function.
957 **/
958 void e1000e_config_collision_dist(struct e1000_hw *hw)
959 {
960 u32 tctl;
961
962 tctl = er32(TCTL);
963
964 tctl &= ~E1000_TCTL_COLD;
965 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
966
967 ew32(TCTL, tctl);
968 e1e_flush();
969 }
970
971 /**
972 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
973 * @hw: pointer to the HW structure
974 *
975 * Sets the flow control high/low threshold (watermark) registers. If
976 * flow control XON frame transmission is enabled, then set XON frame
977 * transmission as well.
978 **/
979 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
980 {
981 u32 fcrtl = 0, fcrth = 0;
982
983 /*
984 * Set the flow control receive threshold registers. Normally,
985 * these registers will be set to a default threshold that may be
986 * adjusted later by the driver's runtime code. However, if the
987 * ability to transmit pause frames is not enabled, then these
988 * registers will be set to 0.
989 */
990 if (hw->fc.current_mode & e1000_fc_tx_pause) {
991 /*
992 * We need to set up the Receive Threshold high and low water
993 * marks as well as (optionally) enabling the transmission of
994 * XON frames.
995 */
996 fcrtl = hw->fc.low_water;
997 fcrtl |= E1000_FCRTL_XONE;
998 fcrth = hw->fc.high_water;
999 }
1000 ew32(FCRTL, fcrtl);
1001 ew32(FCRTH, fcrth);
1002
1003 return 0;
1004 }
1005
1006 /**
1007 * e1000e_force_mac_fc - Force the MAC's flow control settings
1008 * @hw: pointer to the HW structure
1009 *
1010 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1011 * device control register to reflect the adapter settings. TFCE and RFCE
1012 * need to be explicitly set by software when a copper PHY is used because
1013 * autonegotiation is managed by the PHY rather than the MAC. Software must
1014 * also configure these bits when link is forced on a fiber connection.
1015 **/
1016 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1017 {
1018 u32 ctrl;
1019
1020 ctrl = er32(CTRL);
1021
1022 /*
1023 * Because we didn't get link via the internal auto-negotiation
1024 * mechanism (we either forced link or we got link via PHY
1025 * auto-neg), we have to manually enable/disable transmit an
1026 * receive flow control.
1027 *
1028 * The "Case" statement below enables/disable flow control
1029 * according to the "hw->fc.current_mode" parameter.
1030 *
1031 * The possible values of the "fc" parameter are:
1032 * 0: Flow control is completely disabled
1033 * 1: Rx flow control is enabled (we can receive pause
1034 * frames but not send pause frames).
1035 * 2: Tx flow control is enabled (we can send pause frames
1036 * frames but we do not receive pause frames).
1037 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1038 * other: No other values should be possible at this point.
1039 */
1040 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1041
1042 switch (hw->fc.current_mode) {
1043 case e1000_fc_none:
1044 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1045 break;
1046 case e1000_fc_rx_pause:
1047 ctrl &= (~E1000_CTRL_TFCE);
1048 ctrl |= E1000_CTRL_RFCE;
1049 break;
1050 case e1000_fc_tx_pause:
1051 ctrl &= (~E1000_CTRL_RFCE);
1052 ctrl |= E1000_CTRL_TFCE;
1053 break;
1054 case e1000_fc_full:
1055 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1056 break;
1057 default:
1058 e_dbg("Flow control param set incorrectly\n");
1059 return -E1000_ERR_CONFIG;
1060 }
1061
1062 ew32(CTRL, ctrl);
1063
1064 return 0;
1065 }
1066
1067 /**
1068 * e1000e_config_fc_after_link_up - Configures flow control after link
1069 * @hw: pointer to the HW structure
1070 *
1071 * Checks the status of auto-negotiation after link up to ensure that the
1072 * speed and duplex were not forced. If the link needed to be forced, then
1073 * flow control needs to be forced also. If auto-negotiation is enabled
1074 * and did not fail, then we configure flow control based on our link
1075 * partner.
1076 **/
1077 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1078 {
1079 struct e1000_mac_info *mac = &hw->mac;
1080 s32 ret_val = 0;
1081 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1082 u16 speed, duplex;
1083
1084 /*
1085 * Check for the case where we have fiber media and auto-neg failed
1086 * so we had to force link. In this case, we need to force the
1087 * configuration of the MAC to match the "fc" parameter.
1088 */
1089 if (mac->autoneg_failed) {
1090 if (hw->phy.media_type == e1000_media_type_fiber ||
1091 hw->phy.media_type == e1000_media_type_internal_serdes)
1092 ret_val = e1000e_force_mac_fc(hw);
1093 } else {
1094 if (hw->phy.media_type == e1000_media_type_copper)
1095 ret_val = e1000e_force_mac_fc(hw);
1096 }
1097
1098 if (ret_val) {
1099 e_dbg("Error forcing flow control settings\n");
1100 return ret_val;
1101 }
1102
1103 /*
1104 * Check for the case where we have copper media and auto-neg is
1105 * enabled. In this case, we need to check and see if Auto-Neg
1106 * has completed, and if so, how the PHY and link partner has
1107 * flow control configured.
1108 */
1109 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1110 /*
1111 * Read the MII Status Register and check to see if AutoNeg
1112 * has completed. We read this twice because this reg has
1113 * some "sticky" (latched) bits.
1114 */
1115 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1116 if (ret_val)
1117 return ret_val;
1118 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1119 if (ret_val)
1120 return ret_val;
1121
1122 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1123 e_dbg("Copper PHY and Auto Neg "
1124 "has not completed.\n");
1125 return ret_val;
1126 }
1127
1128 /*
1129 * The AutoNeg process has completed, so we now need to
1130 * read both the Auto Negotiation Advertisement
1131 * Register (Address 4) and the Auto_Negotiation Base
1132 * Page Ability Register (Address 5) to determine how
1133 * flow control was negotiated.
1134 */
1135 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1136 if (ret_val)
1137 return ret_val;
1138 ret_val =
1139 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1140 if (ret_val)
1141 return ret_val;
1142
1143 /*
1144 * Two bits in the Auto Negotiation Advertisement Register
1145 * (Address 4) and two bits in the Auto Negotiation Base
1146 * Page Ability Register (Address 5) determine flow control
1147 * for both the PHY and the link partner. The following
1148 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1149 * 1999, describes these PAUSE resolution bits and how flow
1150 * control is determined based upon these settings.
1151 * NOTE: DC = Don't Care
1152 *
1153 * LOCAL DEVICE | LINK PARTNER
1154 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1155 *-------|---------|-------|---------|--------------------
1156 * 0 | 0 | DC | DC | e1000_fc_none
1157 * 0 | 1 | 0 | DC | e1000_fc_none
1158 * 0 | 1 | 1 | 0 | e1000_fc_none
1159 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1160 * 1 | 0 | 0 | DC | e1000_fc_none
1161 * 1 | DC | 1 | DC | e1000_fc_full
1162 * 1 | 1 | 0 | 0 | e1000_fc_none
1163 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1164 *
1165 * Are both PAUSE bits set to 1? If so, this implies
1166 * Symmetric Flow Control is enabled at both ends. The
1167 * ASM_DIR bits are irrelevant per the spec.
1168 *
1169 * For Symmetric Flow Control:
1170 *
1171 * LOCAL DEVICE | LINK PARTNER
1172 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1173 *-------|---------|-------|---------|--------------------
1174 * 1 | DC | 1 | DC | E1000_fc_full
1175 *
1176 */
1177 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1178 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1179 /*
1180 * Now we need to check if the user selected Rx ONLY
1181 * of pause frames. In this case, we had to advertise
1182 * FULL flow control because we could not advertise Rx
1183 * ONLY. Hence, we must now check to see if we need to
1184 * turn OFF the TRANSMISSION of PAUSE frames.
1185 */
1186 if (hw->fc.requested_mode == e1000_fc_full) {
1187 hw->fc.current_mode = e1000_fc_full;
1188 e_dbg("Flow Control = FULL.\r\n");
1189 } else {
1190 hw->fc.current_mode = e1000_fc_rx_pause;
1191 e_dbg("Flow Control = "
1192 "RX PAUSE frames only.\r\n");
1193 }
1194 }
1195 /*
1196 * For receiving PAUSE frames ONLY.
1197 *
1198 * LOCAL DEVICE | LINK PARTNER
1199 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1200 *-------|---------|-------|---------|--------------------
1201 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1202 */
1203 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1204 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1205 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1206 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1207 hw->fc.current_mode = e1000_fc_tx_pause;
1208 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1209 }
1210 /*
1211 * For transmitting PAUSE frames ONLY.
1212 *
1213 * LOCAL DEVICE | LINK PARTNER
1214 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1215 *-------|---------|-------|---------|--------------------
1216 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1217 */
1218 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1219 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1220 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1221 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1222 hw->fc.current_mode = e1000_fc_rx_pause;
1223 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1224 } else {
1225 /*
1226 * Per the IEEE spec, at this point flow control
1227 * should be disabled.
1228 */
1229 hw->fc.current_mode = e1000_fc_none;
1230 e_dbg("Flow Control = NONE.\r\n");
1231 }
1232
1233 /*
1234 * Now we need to do one last check... If we auto-
1235 * negotiated to HALF DUPLEX, flow control should not be
1236 * enabled per IEEE 802.3 spec.
1237 */
1238 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1239 if (ret_val) {
1240 e_dbg("Error getting link speed and duplex\n");
1241 return ret_val;
1242 }
1243
1244 if (duplex == HALF_DUPLEX)
1245 hw->fc.current_mode = e1000_fc_none;
1246
1247 /*
1248 * Now we call a subroutine to actually force the MAC
1249 * controller to use the correct flow control settings.
1250 */
1251 ret_val = e1000e_force_mac_fc(hw);
1252 if (ret_val) {
1253 e_dbg("Error forcing flow control settings\n");
1254 return ret_val;
1255 }
1256 }
1257
1258 return 0;
1259 }
1260
1261 /**
1262 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1263 * @hw: pointer to the HW structure
1264 * @speed: stores the current speed
1265 * @duplex: stores the current duplex
1266 *
1267 * Read the status register for the current speed/duplex and store the current
1268 * speed and duplex for copper connections.
1269 **/
1270 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1271 {
1272 u32 status;
1273
1274 status = er32(STATUS);
1275 if (status & E1000_STATUS_SPEED_1000)
1276 *speed = SPEED_1000;
1277 else if (status & E1000_STATUS_SPEED_100)
1278 *speed = SPEED_100;
1279 else
1280 *speed = SPEED_10;
1281
1282 if (status & E1000_STATUS_FD)
1283 *duplex = FULL_DUPLEX;
1284 else
1285 *duplex = HALF_DUPLEX;
1286
1287 e_dbg("%u Mbps, %s Duplex\n",
1288 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1289 *duplex == FULL_DUPLEX ? "Full" : "Half");
1290
1291 return 0;
1292 }
1293
1294 /**
1295 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1296 * @hw: pointer to the HW structure
1297 * @speed: stores the current speed
1298 * @duplex: stores the current duplex
1299 *
1300 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1301 * for fiber/serdes links.
1302 **/
1303 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1304 {
1305 *speed = SPEED_1000;
1306 *duplex = FULL_DUPLEX;
1307
1308 return 0;
1309 }
1310
1311 /**
1312 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1313 * @hw: pointer to the HW structure
1314 *
1315 * Acquire the HW semaphore to access the PHY or NVM
1316 **/
1317 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1318 {
1319 u32 swsm;
1320 s32 timeout = hw->nvm.word_size + 1;
1321 s32 i = 0;
1322
1323 /* Get the SW semaphore */
1324 while (i < timeout) {
1325 swsm = er32(SWSM);
1326 if (!(swsm & E1000_SWSM_SMBI))
1327 break;
1328
1329 udelay(50);
1330 i++;
1331 }
1332
1333 if (i == timeout) {
1334 e_dbg("Driver can't access device - SMBI bit is set.\n");
1335 return -E1000_ERR_NVM;
1336 }
1337
1338 /* Get the FW semaphore. */
1339 for (i = 0; i < timeout; i++) {
1340 swsm = er32(SWSM);
1341 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1342
1343 /* Semaphore acquired if bit latched */
1344 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1345 break;
1346
1347 udelay(50);
1348 }
1349
1350 if (i == timeout) {
1351 /* Release semaphores */
1352 e1000e_put_hw_semaphore(hw);
1353 e_dbg("Driver can't access the NVM\n");
1354 return -E1000_ERR_NVM;
1355 }
1356
1357 return 0;
1358 }
1359
1360 /**
1361 * e1000e_put_hw_semaphore - Release hardware semaphore
1362 * @hw: pointer to the HW structure
1363 *
1364 * Release hardware semaphore used to access the PHY or NVM
1365 **/
1366 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1367 {
1368 u32 swsm;
1369
1370 swsm = er32(SWSM);
1371 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1372 ew32(SWSM, swsm);
1373 }
1374
1375 /**
1376 * e1000e_get_auto_rd_done - Check for auto read completion
1377 * @hw: pointer to the HW structure
1378 *
1379 * Check EEPROM for Auto Read done bit.
1380 **/
1381 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1382 {
1383 s32 i = 0;
1384
1385 while (i < AUTO_READ_DONE_TIMEOUT) {
1386 if (er32(EECD) & E1000_EECD_AUTO_RD)
1387 break;
1388 msleep(1);
1389 i++;
1390 }
1391
1392 if (i == AUTO_READ_DONE_TIMEOUT) {
1393 e_dbg("Auto read by HW from NVM has not completed.\n");
1394 return -E1000_ERR_RESET;
1395 }
1396
1397 return 0;
1398 }
1399
1400 /**
1401 * e1000e_valid_led_default - Verify a valid default LED config
1402 * @hw: pointer to the HW structure
1403 * @data: pointer to the NVM (EEPROM)
1404 *
1405 * Read the EEPROM for the current default LED configuration. If the
1406 * LED configuration is not valid, set to a valid LED configuration.
1407 **/
1408 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1409 {
1410 s32 ret_val;
1411
1412 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1413 if (ret_val) {
1414 e_dbg("NVM Read Error\n");
1415 return ret_val;
1416 }
1417
1418 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1419 *data = ID_LED_DEFAULT;
1420
1421 return 0;
1422 }
1423
1424 /**
1425 * e1000e_id_led_init -
1426 * @hw: pointer to the HW structure
1427 *
1428 **/
1429 s32 e1000e_id_led_init(struct e1000_hw *hw)
1430 {
1431 struct e1000_mac_info *mac = &hw->mac;
1432 s32 ret_val;
1433 const u32 ledctl_mask = 0x000000FF;
1434 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1435 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1436 u16 data, i, temp;
1437 const u16 led_mask = 0x0F;
1438
1439 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1440 if (ret_val)
1441 return ret_val;
1442
1443 mac->ledctl_default = er32(LEDCTL);
1444 mac->ledctl_mode1 = mac->ledctl_default;
1445 mac->ledctl_mode2 = mac->ledctl_default;
1446
1447 for (i = 0; i < 4; i++) {
1448 temp = (data >> (i << 2)) & led_mask;
1449 switch (temp) {
1450 case ID_LED_ON1_DEF2:
1451 case ID_LED_ON1_ON2:
1452 case ID_LED_ON1_OFF2:
1453 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1454 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1455 break;
1456 case ID_LED_OFF1_DEF2:
1457 case ID_LED_OFF1_ON2:
1458 case ID_LED_OFF1_OFF2:
1459 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1460 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1461 break;
1462 default:
1463 /* Do nothing */
1464 break;
1465 }
1466 switch (temp) {
1467 case ID_LED_DEF1_ON2:
1468 case ID_LED_ON1_ON2:
1469 case ID_LED_OFF1_ON2:
1470 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1471 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1472 break;
1473 case ID_LED_DEF1_OFF2:
1474 case ID_LED_ON1_OFF2:
1475 case ID_LED_OFF1_OFF2:
1476 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1477 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1478 break;
1479 default:
1480 /* Do nothing */
1481 break;
1482 }
1483 }
1484
1485 return 0;
1486 }
1487
1488 /**
1489 * e1000e_setup_led_generic - Configures SW controllable LED
1490 * @hw: pointer to the HW structure
1491 *
1492 * This prepares the SW controllable LED for use and saves the current state
1493 * of the LED so it can be later restored.
1494 **/
1495 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1496 {
1497 u32 ledctl;
1498
1499 if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1500 return -E1000_ERR_CONFIG;
1501
1502 if (hw->phy.media_type == e1000_media_type_fiber) {
1503 ledctl = er32(LEDCTL);
1504 hw->mac.ledctl_default = ledctl;
1505 /* Turn off LED0 */
1506 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1507 E1000_LEDCTL_LED0_BLINK |
1508 E1000_LEDCTL_LED0_MODE_MASK);
1509 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1510 E1000_LEDCTL_LED0_MODE_SHIFT);
1511 ew32(LEDCTL, ledctl);
1512 } else if (hw->phy.media_type == e1000_media_type_copper) {
1513 ew32(LEDCTL, hw->mac.ledctl_mode1);
1514 }
1515
1516 return 0;
1517 }
1518
1519 /**
1520 * e1000e_cleanup_led_generic - Set LED config to default operation
1521 * @hw: pointer to the HW structure
1522 *
1523 * Remove the current LED configuration and set the LED configuration
1524 * to the default value, saved from the EEPROM.
1525 **/
1526 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1527 {
1528 ew32(LEDCTL, hw->mac.ledctl_default);
1529 return 0;
1530 }
1531
1532 /**
1533 * e1000e_blink_led - Blink LED
1534 * @hw: pointer to the HW structure
1535 *
1536 * Blink the LEDs which are set to be on.
1537 **/
1538 s32 e1000e_blink_led(struct e1000_hw *hw)
1539 {
1540 u32 ledctl_blink = 0;
1541 u32 i;
1542
1543 if (hw->phy.media_type == e1000_media_type_fiber) {
1544 /* always blink LED0 for PCI-E fiber */
1545 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1546 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1547 } else {
1548 /*
1549 * set the blink bit for each LED that's "on" (0x0E)
1550 * in ledctl_mode2
1551 */
1552 ledctl_blink = hw->mac.ledctl_mode2;
1553 for (i = 0; i < 4; i++)
1554 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1555 E1000_LEDCTL_MODE_LED_ON)
1556 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1557 (i * 8));
1558 }
1559
1560 ew32(LEDCTL, ledctl_blink);
1561
1562 return 0;
1563 }
1564
1565 /**
1566 * e1000e_led_on_generic - Turn LED on
1567 * @hw: pointer to the HW structure
1568 *
1569 * Turn LED on.
1570 **/
1571 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1572 {
1573 u32 ctrl;
1574
1575 switch (hw->phy.media_type) {
1576 case e1000_media_type_fiber:
1577 ctrl = er32(CTRL);
1578 ctrl &= ~E1000_CTRL_SWDPIN0;
1579 ctrl |= E1000_CTRL_SWDPIO0;
1580 ew32(CTRL, ctrl);
1581 break;
1582 case e1000_media_type_copper:
1583 ew32(LEDCTL, hw->mac.ledctl_mode2);
1584 break;
1585 default:
1586 break;
1587 }
1588
1589 return 0;
1590 }
1591
1592 /**
1593 * e1000e_led_off_generic - Turn LED off
1594 * @hw: pointer to the HW structure
1595 *
1596 * Turn LED off.
1597 **/
1598 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1599 {
1600 u32 ctrl;
1601
1602 switch (hw->phy.media_type) {
1603 case e1000_media_type_fiber:
1604 ctrl = er32(CTRL);
1605 ctrl |= E1000_CTRL_SWDPIN0;
1606 ctrl |= E1000_CTRL_SWDPIO0;
1607 ew32(CTRL, ctrl);
1608 break;
1609 case e1000_media_type_copper:
1610 ew32(LEDCTL, hw->mac.ledctl_mode1);
1611 break;
1612 default:
1613 break;
1614 }
1615
1616 return 0;
1617 }
1618
1619 /**
1620 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1621 * @hw: pointer to the HW structure
1622 * @no_snoop: bitmap of snoop events
1623 *
1624 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1625 **/
1626 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1627 {
1628 u32 gcr;
1629
1630 if (no_snoop) {
1631 gcr = er32(GCR);
1632 gcr &= ~(PCIE_NO_SNOOP_ALL);
1633 gcr |= no_snoop;
1634 ew32(GCR, gcr);
1635 }
1636 }
1637
1638 /**
1639 * e1000e_disable_pcie_master - Disables PCI-express master access
1640 * @hw: pointer to the HW structure
1641 *
1642 * Returns 0 if successful, else returns -10
1643 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1644 * the master requests to be disabled.
1645 *
1646 * Disables PCI-Express master access and verifies there are no pending
1647 * requests.
1648 **/
1649 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1650 {
1651 u32 ctrl;
1652 s32 timeout = MASTER_DISABLE_TIMEOUT;
1653
1654 ctrl = er32(CTRL);
1655 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1656 ew32(CTRL, ctrl);
1657
1658 while (timeout) {
1659 if (!(er32(STATUS) &
1660 E1000_STATUS_GIO_MASTER_ENABLE))
1661 break;
1662 udelay(100);
1663 timeout--;
1664 }
1665
1666 if (!timeout) {
1667 e_dbg("Master requests are pending.\n");
1668 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1669 }
1670
1671 return 0;
1672 }
1673
1674 /**
1675 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1676 * @hw: pointer to the HW structure
1677 *
1678 * Reset the Adaptive Interframe Spacing throttle to default values.
1679 **/
1680 void e1000e_reset_adaptive(struct e1000_hw *hw)
1681 {
1682 struct e1000_mac_info *mac = &hw->mac;
1683
1684 if (!mac->adaptive_ifs) {
1685 e_dbg("Not in Adaptive IFS mode!\n");
1686 goto out;
1687 }
1688
1689 mac->current_ifs_val = 0;
1690 mac->ifs_min_val = IFS_MIN;
1691 mac->ifs_max_val = IFS_MAX;
1692 mac->ifs_step_size = IFS_STEP;
1693 mac->ifs_ratio = IFS_RATIO;
1694
1695 mac->in_ifs_mode = false;
1696 ew32(AIT, 0);
1697 out:
1698 return;
1699 }
1700
1701 /**
1702 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1703 * @hw: pointer to the HW structure
1704 *
1705 * Update the Adaptive Interframe Spacing Throttle value based on the
1706 * time between transmitted packets and time between collisions.
1707 **/
1708 void e1000e_update_adaptive(struct e1000_hw *hw)
1709 {
1710 struct e1000_mac_info *mac = &hw->mac;
1711
1712 if (!mac->adaptive_ifs) {
1713 e_dbg("Not in Adaptive IFS mode!\n");
1714 goto out;
1715 }
1716
1717 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1718 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1719 mac->in_ifs_mode = true;
1720 if (mac->current_ifs_val < mac->ifs_max_val) {
1721 if (!mac->current_ifs_val)
1722 mac->current_ifs_val = mac->ifs_min_val;
1723 else
1724 mac->current_ifs_val +=
1725 mac->ifs_step_size;
1726 ew32(AIT, mac->current_ifs_val);
1727 }
1728 }
1729 } else {
1730 if (mac->in_ifs_mode &&
1731 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1732 mac->current_ifs_val = 0;
1733 mac->in_ifs_mode = false;
1734 ew32(AIT, 0);
1735 }
1736 }
1737 out:
1738 return;
1739 }
1740
1741 /**
1742 * e1000_raise_eec_clk - Raise EEPROM clock
1743 * @hw: pointer to the HW structure
1744 * @eecd: pointer to the EEPROM
1745 *
1746 * Enable/Raise the EEPROM clock bit.
1747 **/
1748 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1749 {
1750 *eecd = *eecd | E1000_EECD_SK;
1751 ew32(EECD, *eecd);
1752 e1e_flush();
1753 udelay(hw->nvm.delay_usec);
1754 }
1755
1756 /**
1757 * e1000_lower_eec_clk - Lower EEPROM clock
1758 * @hw: pointer to the HW structure
1759 * @eecd: pointer to the EEPROM
1760 *
1761 * Clear/Lower the EEPROM clock bit.
1762 **/
1763 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1764 {
1765 *eecd = *eecd & ~E1000_EECD_SK;
1766 ew32(EECD, *eecd);
1767 e1e_flush();
1768 udelay(hw->nvm.delay_usec);
1769 }
1770
1771 /**
1772 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1773 * @hw: pointer to the HW structure
1774 * @data: data to send to the EEPROM
1775 * @count: number of bits to shift out
1776 *
1777 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1778 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1779 * In order to do this, "data" must be broken down into bits.
1780 **/
1781 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1782 {
1783 struct e1000_nvm_info *nvm = &hw->nvm;
1784 u32 eecd = er32(EECD);
1785 u32 mask;
1786
1787 mask = 0x01 << (count - 1);
1788 if (nvm->type == e1000_nvm_eeprom_spi)
1789 eecd |= E1000_EECD_DO;
1790
1791 do {
1792 eecd &= ~E1000_EECD_DI;
1793
1794 if (data & mask)
1795 eecd |= E1000_EECD_DI;
1796
1797 ew32(EECD, eecd);
1798 e1e_flush();
1799
1800 udelay(nvm->delay_usec);
1801
1802 e1000_raise_eec_clk(hw, &eecd);
1803 e1000_lower_eec_clk(hw, &eecd);
1804
1805 mask >>= 1;
1806 } while (mask);
1807
1808 eecd &= ~E1000_EECD_DI;
1809 ew32(EECD, eecd);
1810 }
1811
1812 /**
1813 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1814 * @hw: pointer to the HW structure
1815 * @count: number of bits to shift in
1816 *
1817 * In order to read a register from the EEPROM, we need to shift 'count' bits
1818 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1819 * the EEPROM (setting the SK bit), and then reading the value of the data out
1820 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1821 * always be clear.
1822 **/
1823 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1824 {
1825 u32 eecd;
1826 u32 i;
1827 u16 data;
1828
1829 eecd = er32(EECD);
1830
1831 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1832 data = 0;
1833
1834 for (i = 0; i < count; i++) {
1835 data <<= 1;
1836 e1000_raise_eec_clk(hw, &eecd);
1837
1838 eecd = er32(EECD);
1839
1840 eecd &= ~E1000_EECD_DI;
1841 if (eecd & E1000_EECD_DO)
1842 data |= 1;
1843
1844 e1000_lower_eec_clk(hw, &eecd);
1845 }
1846
1847 return data;
1848 }
1849
1850 /**
1851 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1852 * @hw: pointer to the HW structure
1853 * @ee_reg: EEPROM flag for polling
1854 *
1855 * Polls the EEPROM status bit for either read or write completion based
1856 * upon the value of 'ee_reg'.
1857 **/
1858 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1859 {
1860 u32 attempts = 100000;
1861 u32 i, reg = 0;
1862
1863 for (i = 0; i < attempts; i++) {
1864 if (ee_reg == E1000_NVM_POLL_READ)
1865 reg = er32(EERD);
1866 else
1867 reg = er32(EEWR);
1868
1869 if (reg & E1000_NVM_RW_REG_DONE)
1870 return 0;
1871
1872 udelay(5);
1873 }
1874
1875 return -E1000_ERR_NVM;
1876 }
1877
1878 /**
1879 * e1000e_acquire_nvm - Generic request for access to EEPROM
1880 * @hw: pointer to the HW structure
1881 *
1882 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1883 * Return successful if access grant bit set, else clear the request for
1884 * EEPROM access and return -E1000_ERR_NVM (-1).
1885 **/
1886 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1887 {
1888 u32 eecd = er32(EECD);
1889 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1890
1891 ew32(EECD, eecd | E1000_EECD_REQ);
1892 eecd = er32(EECD);
1893
1894 while (timeout) {
1895 if (eecd & E1000_EECD_GNT)
1896 break;
1897 udelay(5);
1898 eecd = er32(EECD);
1899 timeout--;
1900 }
1901
1902 if (!timeout) {
1903 eecd &= ~E1000_EECD_REQ;
1904 ew32(EECD, eecd);
1905 e_dbg("Could not acquire NVM grant\n");
1906 return -E1000_ERR_NVM;
1907 }
1908
1909 return 0;
1910 }
1911
1912 /**
1913 * e1000_standby_nvm - Return EEPROM to standby state
1914 * @hw: pointer to the HW structure
1915 *
1916 * Return the EEPROM to a standby state.
1917 **/
1918 static void e1000_standby_nvm(struct e1000_hw *hw)
1919 {
1920 struct e1000_nvm_info *nvm = &hw->nvm;
1921 u32 eecd = er32(EECD);
1922
1923 if (nvm->type == e1000_nvm_eeprom_spi) {
1924 /* Toggle CS to flush commands */
1925 eecd |= E1000_EECD_CS;
1926 ew32(EECD, eecd);
1927 e1e_flush();
1928 udelay(nvm->delay_usec);
1929 eecd &= ~E1000_EECD_CS;
1930 ew32(EECD, eecd);
1931 e1e_flush();
1932 udelay(nvm->delay_usec);
1933 }
1934 }
1935
1936 /**
1937 * e1000_stop_nvm - Terminate EEPROM command
1938 * @hw: pointer to the HW structure
1939 *
1940 * Terminates the current command by inverting the EEPROM's chip select pin.
1941 **/
1942 static void e1000_stop_nvm(struct e1000_hw *hw)
1943 {
1944 u32 eecd;
1945
1946 eecd = er32(EECD);
1947 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1948 /* Pull CS high */
1949 eecd |= E1000_EECD_CS;
1950 e1000_lower_eec_clk(hw, &eecd);
1951 }
1952 }
1953
1954 /**
1955 * e1000e_release_nvm - Release exclusive access to EEPROM
1956 * @hw: pointer to the HW structure
1957 *
1958 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1959 **/
1960 void e1000e_release_nvm(struct e1000_hw *hw)
1961 {
1962 u32 eecd;
1963
1964 e1000_stop_nvm(hw);
1965
1966 eecd = er32(EECD);
1967 eecd &= ~E1000_EECD_REQ;
1968 ew32(EECD, eecd);
1969 }
1970
1971 /**
1972 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1973 * @hw: pointer to the HW structure
1974 *
1975 * Setups the EEPROM for reading and writing.
1976 **/
1977 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1978 {
1979 struct e1000_nvm_info *nvm = &hw->nvm;
1980 u32 eecd = er32(EECD);
1981 u16 timeout = 0;
1982 u8 spi_stat_reg;
1983
1984 if (nvm->type == e1000_nvm_eeprom_spi) {
1985 /* Clear SK and CS */
1986 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1987 ew32(EECD, eecd);
1988 udelay(1);
1989 timeout = NVM_MAX_RETRY_SPI;
1990
1991 /*
1992 * Read "Status Register" repeatedly until the LSB is cleared.
1993 * The EEPROM will signal that the command has been completed
1994 * by clearing bit 0 of the internal status register. If it's
1995 * not cleared within 'timeout', then error out.
1996 */
1997 while (timeout) {
1998 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1999 hw->nvm.opcode_bits);
2000 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
2001 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
2002 break;
2003
2004 udelay(5);
2005 e1000_standby_nvm(hw);
2006 timeout--;
2007 }
2008
2009 if (!timeout) {
2010 e_dbg("SPI NVM Status error\n");
2011 return -E1000_ERR_NVM;
2012 }
2013 }
2014
2015 return 0;
2016 }
2017
2018 /**
2019 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2020 * @hw: pointer to the HW structure
2021 * @offset: offset of word in the EEPROM to read
2022 * @words: number of words to read
2023 * @data: word read from the EEPROM
2024 *
2025 * Reads a 16 bit word from the EEPROM using the EERD register.
2026 **/
2027 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2028 {
2029 struct e1000_nvm_info *nvm = &hw->nvm;
2030 u32 i, eerd = 0;
2031 s32 ret_val = 0;
2032
2033 /*
2034 * A check for invalid values: offset too large, too many words,
2035 * too many words for the offset, and not enough words.
2036 */
2037 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2038 (words == 0)) {
2039 e_dbg("nvm parameter(s) out of bounds\n");
2040 return -E1000_ERR_NVM;
2041 }
2042
2043 for (i = 0; i < words; i++) {
2044 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2045 E1000_NVM_RW_REG_START;
2046
2047 ew32(EERD, eerd);
2048 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2049 if (ret_val)
2050 break;
2051
2052 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2053 }
2054
2055 return ret_val;
2056 }
2057
2058 /**
2059 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2060 * @hw: pointer to the HW structure
2061 * @offset: offset within the EEPROM to be written to
2062 * @words: number of words to write
2063 * @data: 16 bit word(s) to be written to the EEPROM
2064 *
2065 * Writes data to EEPROM at offset using SPI interface.
2066 *
2067 * If e1000e_update_nvm_checksum is not called after this function , the
2068 * EEPROM will most likely contain an invalid checksum.
2069 **/
2070 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2071 {
2072 struct e1000_nvm_info *nvm = &hw->nvm;
2073 s32 ret_val;
2074 u16 widx = 0;
2075
2076 /*
2077 * A check for invalid values: offset too large, too many words,
2078 * and not enough words.
2079 */
2080 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2081 (words == 0)) {
2082 e_dbg("nvm parameter(s) out of bounds\n");
2083 return -E1000_ERR_NVM;
2084 }
2085
2086 ret_val = nvm->ops.acquire(hw);
2087 if (ret_val)
2088 return ret_val;
2089
2090 msleep(10);
2091
2092 while (widx < words) {
2093 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2094
2095 ret_val = e1000_ready_nvm_eeprom(hw);
2096 if (ret_val) {
2097 nvm->ops.release(hw);
2098 return ret_val;
2099 }
2100
2101 e1000_standby_nvm(hw);
2102
2103 /* Send the WRITE ENABLE command (8 bit opcode) */
2104 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2105 nvm->opcode_bits);
2106
2107 e1000_standby_nvm(hw);
2108
2109 /*
2110 * Some SPI eeproms use the 8th address bit embedded in the
2111 * opcode
2112 */
2113 if ((nvm->address_bits == 8) && (offset >= 128))
2114 write_opcode |= NVM_A8_OPCODE_SPI;
2115
2116 /* Send the Write command (8-bit opcode + addr) */
2117 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2118 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2119 nvm->address_bits);
2120
2121 /* Loop to allow for up to whole page write of eeprom */
2122 while (widx < words) {
2123 u16 word_out = data[widx];
2124 word_out = (word_out >> 8) | (word_out << 8);
2125 e1000_shift_out_eec_bits(hw, word_out, 16);
2126 widx++;
2127
2128 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2129 e1000_standby_nvm(hw);
2130 break;
2131 }
2132 }
2133 }
2134
2135 msleep(10);
2136 nvm->ops.release(hw);
2137 return 0;
2138 }
2139
2140 /**
2141 * e1000_read_pba_string_generic - Read device part number
2142 * @hw: pointer to the HW structure
2143 * @pba_num: pointer to device part number
2144 * @pba_num_size: size of part number buffer
2145 *
2146 * Reads the product board assembly (PBA) number from the EEPROM and stores
2147 * the value in pba_num.
2148 **/
2149 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
2150 u32 pba_num_size)
2151 {
2152 s32 ret_val;
2153 u16 nvm_data;
2154 u16 pba_ptr;
2155 u16 offset;
2156 u16 length;
2157
2158 if (pba_num == NULL) {
2159 e_dbg("PBA string buffer was null\n");
2160 ret_val = E1000_ERR_INVALID_ARGUMENT;
2161 goto out;
2162 }
2163
2164 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2165 if (ret_val) {
2166 e_dbg("NVM Read Error\n");
2167 goto out;
2168 }
2169
2170 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
2171 if (ret_val) {
2172 e_dbg("NVM Read Error\n");
2173 goto out;
2174 }
2175
2176 /*
2177 * if nvm_data is not ptr guard the PBA must be in legacy format which
2178 * means pba_ptr is actually our second data word for the PBA number
2179 * and we can decode it into an ascii string
2180 */
2181 if (nvm_data != NVM_PBA_PTR_GUARD) {
2182 e_dbg("NVM PBA number is not stored as string\n");
2183
2184 /* we will need 11 characters to store the PBA */
2185 if (pba_num_size < 11) {
2186 e_dbg("PBA string buffer too small\n");
2187 return E1000_ERR_NO_SPACE;
2188 }
2189
2190 /* extract hex string from data and pba_ptr */
2191 pba_num[0] = (nvm_data >> 12) & 0xF;
2192 pba_num[1] = (nvm_data >> 8) & 0xF;
2193 pba_num[2] = (nvm_data >> 4) & 0xF;
2194 pba_num[3] = nvm_data & 0xF;
2195 pba_num[4] = (pba_ptr >> 12) & 0xF;
2196 pba_num[5] = (pba_ptr >> 8) & 0xF;
2197 pba_num[6] = '-';
2198 pba_num[7] = 0;
2199 pba_num[8] = (pba_ptr >> 4) & 0xF;
2200 pba_num[9] = pba_ptr & 0xF;
2201
2202 /* put a null character on the end of our string */
2203 pba_num[10] = '\0';
2204
2205 /* switch all the data but the '-' to hex char */
2206 for (offset = 0; offset < 10; offset++) {
2207 if (pba_num[offset] < 0xA)
2208 pba_num[offset] += '0';
2209 else if (pba_num[offset] < 0x10)
2210 pba_num[offset] += 'A' - 0xA;
2211 }
2212
2213 goto out;
2214 }
2215
2216 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
2217 if (ret_val) {
2218 e_dbg("NVM Read Error\n");
2219 goto out;
2220 }
2221
2222 if (length == 0xFFFF || length == 0) {
2223 e_dbg("NVM PBA number section invalid length\n");
2224 ret_val = E1000_ERR_NVM_PBA_SECTION;
2225 goto out;
2226 }
2227 /* check if pba_num buffer is big enough */
2228 if (pba_num_size < (((u32)length * 2) - 1)) {
2229 e_dbg("PBA string buffer too small\n");
2230 ret_val = E1000_ERR_NO_SPACE;
2231 goto out;
2232 }
2233
2234 /* trim pba length from start of string */
2235 pba_ptr++;
2236 length--;
2237
2238 for (offset = 0; offset < length; offset++) {
2239 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
2240 if (ret_val) {
2241 e_dbg("NVM Read Error\n");
2242 goto out;
2243 }
2244 pba_num[offset * 2] = (u8)(nvm_data >> 8);
2245 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
2246 }
2247 pba_num[offset * 2] = '\0';
2248
2249 out:
2250 return ret_val;
2251 }
2252
2253 /**
2254 * e1000_read_mac_addr_generic - Read device MAC address
2255 * @hw: pointer to the HW structure
2256 *
2257 * Reads the device MAC address from the EEPROM and stores the value.
2258 * Since devices with two ports use the same EEPROM, we increment the
2259 * last bit in the MAC address for the second port.
2260 **/
2261 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2262 {
2263 u32 rar_high;
2264 u32 rar_low;
2265 u16 i;
2266
2267 rar_high = er32(RAH(0));
2268 rar_low = er32(RAL(0));
2269
2270 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2271 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2272
2273 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2274 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2275
2276 for (i = 0; i < ETH_ALEN; i++)
2277 hw->mac.addr[i] = hw->mac.perm_addr[i];
2278
2279 return 0;
2280 }
2281
2282 /**
2283 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2284 * @hw: pointer to the HW structure
2285 *
2286 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2287 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2288 **/
2289 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2290 {
2291 s32 ret_val;
2292 u16 checksum = 0;
2293 u16 i, nvm_data;
2294
2295 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2296 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2297 if (ret_val) {
2298 e_dbg("NVM Read Error\n");
2299 return ret_val;
2300 }
2301 checksum += nvm_data;
2302 }
2303
2304 if (checksum != (u16) NVM_SUM) {
2305 e_dbg("NVM Checksum Invalid\n");
2306 return -E1000_ERR_NVM;
2307 }
2308
2309 return 0;
2310 }
2311
2312 /**
2313 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2314 * @hw: pointer to the HW structure
2315 *
2316 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2317 * up to the checksum. Then calculates the EEPROM checksum and writes the
2318 * value to the EEPROM.
2319 **/
2320 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2321 {
2322 s32 ret_val;
2323 u16 checksum = 0;
2324 u16 i, nvm_data;
2325
2326 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2327 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2328 if (ret_val) {
2329 e_dbg("NVM Read Error while updating checksum.\n");
2330 return ret_val;
2331 }
2332 checksum += nvm_data;
2333 }
2334 checksum = (u16) NVM_SUM - checksum;
2335 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2336 if (ret_val)
2337 e_dbg("NVM Write Error while updating checksum.\n");
2338
2339 return ret_val;
2340 }
2341
2342 /**
2343 * e1000e_reload_nvm - Reloads EEPROM
2344 * @hw: pointer to the HW structure
2345 *
2346 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2347 * extended control register.
2348 **/
2349 void e1000e_reload_nvm(struct e1000_hw *hw)
2350 {
2351 u32 ctrl_ext;
2352
2353 udelay(10);
2354 ctrl_ext = er32(CTRL_EXT);
2355 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2356 ew32(CTRL_EXT, ctrl_ext);
2357 e1e_flush();
2358 }
2359
2360 /**
2361 * e1000_calculate_checksum - Calculate checksum for buffer
2362 * @buffer: pointer to EEPROM
2363 * @length: size of EEPROM to calculate a checksum for
2364 *
2365 * Calculates the checksum for some buffer on a specified length. The
2366 * checksum calculated is returned.
2367 **/
2368 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2369 {
2370 u32 i;
2371 u8 sum = 0;
2372
2373 if (!buffer)
2374 return 0;
2375
2376 for (i = 0; i < length; i++)
2377 sum += buffer[i];
2378
2379 return (u8) (0 - sum);
2380 }
2381
2382 /**
2383 * e1000_mng_enable_host_if - Checks host interface is enabled
2384 * @hw: pointer to the HW structure
2385 *
2386 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2387 *
2388 * This function checks whether the HOST IF is enabled for command operation
2389 * and also checks whether the previous command is completed. It busy waits
2390 * in case of previous command is not completed.
2391 **/
2392 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2393 {
2394 u32 hicr;
2395 u8 i;
2396
2397 if (!(hw->mac.arc_subsystem_valid)) {
2398 e_dbg("ARC subsystem not valid.\n");
2399 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2400 }
2401
2402 /* Check that the host interface is enabled. */
2403 hicr = er32(HICR);
2404 if ((hicr & E1000_HICR_EN) == 0) {
2405 e_dbg("E1000_HOST_EN bit disabled.\n");
2406 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2407 }
2408 /* check the previous command is completed */
2409 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2410 hicr = er32(HICR);
2411 if (!(hicr & E1000_HICR_C))
2412 break;
2413 mdelay(1);
2414 }
2415
2416 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2417 e_dbg("Previous command timeout failed .\n");
2418 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2419 }
2420
2421 return 0;
2422 }
2423
2424 /**
2425 * e1000e_check_mng_mode_generic - check management mode
2426 * @hw: pointer to the HW structure
2427 *
2428 * Reads the firmware semaphore register and returns true (>0) if
2429 * manageability is enabled, else false (0).
2430 **/
2431 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2432 {
2433 u32 fwsm = er32(FWSM);
2434
2435 return (fwsm & E1000_FWSM_MODE_MASK) ==
2436 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2437 }
2438
2439 /**
2440 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2441 * @hw: pointer to the HW structure
2442 *
2443 * Enables packet filtering on transmit packets if manageability is enabled
2444 * and host interface is enabled.
2445 **/
2446 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2447 {
2448 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2449 u32 *buffer = (u32 *)&hw->mng_cookie;
2450 u32 offset;
2451 s32 ret_val, hdr_csum, csum;
2452 u8 i, len;
2453
2454 hw->mac.tx_pkt_filtering = true;
2455
2456 /* No manageability, no filtering */
2457 if (!e1000e_check_mng_mode(hw)) {
2458 hw->mac.tx_pkt_filtering = false;
2459 goto out;
2460 }
2461
2462 /*
2463 * If we can't read from the host interface for whatever
2464 * reason, disable filtering.
2465 */
2466 ret_val = e1000_mng_enable_host_if(hw);
2467 if (ret_val) {
2468 hw->mac.tx_pkt_filtering = false;
2469 goto out;
2470 }
2471
2472 /* Read in the header. Length and offset are in dwords. */
2473 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2474 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2475 for (i = 0; i < len; i++)
2476 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2477 hdr_csum = hdr->checksum;
2478 hdr->checksum = 0;
2479 csum = e1000_calculate_checksum((u8 *)hdr,
2480 E1000_MNG_DHCP_COOKIE_LENGTH);
2481 /*
2482 * If either the checksums or signature don't match, then
2483 * the cookie area isn't considered valid, in which case we
2484 * take the safe route of assuming Tx filtering is enabled.
2485 */
2486 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2487 hw->mac.tx_pkt_filtering = true;
2488 goto out;
2489 }
2490
2491 /* Cookie area is valid, make the final check for filtering. */
2492 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2493 hw->mac.tx_pkt_filtering = false;
2494 goto out;
2495 }
2496
2497 out:
2498 return hw->mac.tx_pkt_filtering;
2499 }
2500
2501 /**
2502 * e1000_mng_write_cmd_header - Writes manageability command header
2503 * @hw: pointer to the HW structure
2504 * @hdr: pointer to the host interface command header
2505 *
2506 * Writes the command header after does the checksum calculation.
2507 **/
2508 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2509 struct e1000_host_mng_command_header *hdr)
2510 {
2511 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2512
2513 /* Write the whole command header structure with new checksum. */
2514
2515 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2516
2517 length >>= 2;
2518 /* Write the relevant command block into the ram area. */
2519 for (i = 0; i < length; i++) {
2520 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2521 *((u32 *) hdr + i));
2522 e1e_flush();
2523 }
2524
2525 return 0;
2526 }
2527
2528 /**
2529 * e1000_mng_host_if_write - Write to the manageability host interface
2530 * @hw: pointer to the HW structure
2531 * @buffer: pointer to the host interface buffer
2532 * @length: size of the buffer
2533 * @offset: location in the buffer to write to
2534 * @sum: sum of the data (not checksum)
2535 *
2536 * This function writes the buffer content at the offset given on the host if.
2537 * It also does alignment considerations to do the writes in most efficient
2538 * way. Also fills up the sum of the buffer in *buffer parameter.
2539 **/
2540 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2541 u16 length, u16 offset, u8 *sum)
2542 {
2543 u8 *tmp;
2544 u8 *bufptr = buffer;
2545 u32 data = 0;
2546 u16 remaining, i, j, prev_bytes;
2547
2548 /* sum = only sum of the data and it is not checksum */
2549
2550 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2551 return -E1000_ERR_PARAM;
2552
2553 tmp = (u8 *)&data;
2554 prev_bytes = offset & 0x3;
2555 offset >>= 2;
2556
2557 if (prev_bytes) {
2558 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2559 for (j = prev_bytes; j < sizeof(u32); j++) {
2560 *(tmp + j) = *bufptr++;
2561 *sum += *(tmp + j);
2562 }
2563 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2564 length -= j - prev_bytes;
2565 offset++;
2566 }
2567
2568 remaining = length & 0x3;
2569 length -= remaining;
2570
2571 /* Calculate length in DWORDs */
2572 length >>= 2;
2573
2574 /*
2575 * The device driver writes the relevant command block into the
2576 * ram area.
2577 */
2578 for (i = 0; i < length; i++) {
2579 for (j = 0; j < sizeof(u32); j++) {
2580 *(tmp + j) = *bufptr++;
2581 *sum += *(tmp + j);
2582 }
2583
2584 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2585 }
2586 if (remaining) {
2587 for (j = 0; j < sizeof(u32); j++) {
2588 if (j < remaining)
2589 *(tmp + j) = *bufptr++;
2590 else
2591 *(tmp + j) = 0;
2592
2593 *sum += *(tmp + j);
2594 }
2595 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2596 }
2597
2598 return 0;
2599 }
2600
2601 /**
2602 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2603 * @hw: pointer to the HW structure
2604 * @buffer: pointer to the host interface
2605 * @length: size of the buffer
2606 *
2607 * Writes the DHCP information to the host interface.
2608 **/
2609 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2610 {
2611 struct e1000_host_mng_command_header hdr;
2612 s32 ret_val;
2613 u32 hicr;
2614
2615 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2616 hdr.command_length = length;
2617 hdr.reserved1 = 0;
2618 hdr.reserved2 = 0;
2619 hdr.checksum = 0;
2620
2621 /* Enable the host interface */
2622 ret_val = e1000_mng_enable_host_if(hw);
2623 if (ret_val)
2624 return ret_val;
2625
2626 /* Populate the host interface with the contents of "buffer". */
2627 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2628 sizeof(hdr), &(hdr.checksum));
2629 if (ret_val)
2630 return ret_val;
2631
2632 /* Write the manageability command header */
2633 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2634 if (ret_val)
2635 return ret_val;
2636
2637 /* Tell the ARC a new command is pending. */
2638 hicr = er32(HICR);
2639 ew32(HICR, hicr | E1000_HICR_C);
2640
2641 return 0;
2642 }
2643
2644 /**
2645 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
2646 * @hw: pointer to the HW structure
2647 *
2648 * Verifies the hardware needs to leave interface enabled so that frames can
2649 * be directed to and from the management interface.
2650 **/
2651 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2652 {
2653 u32 manc;
2654 u32 fwsm, factps;
2655 bool ret_val = false;
2656
2657 manc = er32(MANC);
2658
2659 if (!(manc & E1000_MANC_RCV_TCO_EN))
2660 goto out;
2661
2662 if (hw->mac.has_fwsm) {
2663 fwsm = er32(FWSM);
2664 factps = er32(FACTPS);
2665
2666 if (!(factps & E1000_FACTPS_MNGCG) &&
2667 ((fwsm & E1000_FWSM_MODE_MASK) ==
2668 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2669 ret_val = true;
2670 goto out;
2671 }
2672 } else if ((hw->mac.type == e1000_82574) ||
2673 (hw->mac.type == e1000_82583)) {
2674 u16 data;
2675
2676 factps = er32(FACTPS);
2677 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2678
2679 if (!(factps & E1000_FACTPS_MNGCG) &&
2680 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
2681 (e1000_mng_mode_pt << 13))) {
2682 ret_val = true;
2683 goto out;
2684 }
2685 } else if ((manc & E1000_MANC_SMBUS_EN) &&
2686 !(manc & E1000_MANC_ASF_EN)) {
2687 ret_val = true;
2688 goto out;
2689 }
2690
2691 out:
2692 return ret_val;
2693 }
linux-next