drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_MAX_TXD                      4096
  57 #define IXGBE_MIN_TXD                        64
  58
  59 #define IXGBE_DEFAULT_RXD                   512
  60 #define IXGBE_MAX_RXD                      4096
  61 #define IXGBE_MIN_RXD                        64
  62
  63 /* flow control */
  64 #define IXGBE_MIN_FCRTL                    0x40
  65 #define IXGBE_MAX_FCRTL                 0x7FF80
  66 #define IXGBE_MIN_FCRTH                   0x600
  67 #define IXGBE_MAX_FCRTH                 0x7FFF0
  68 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  69 #define IXGBE_MIN_FCPAUSE                     0
  70 #define IXGBE_MAX_FCPAUSE                0xFFFF
  71
  72 /* Supported Rx Buffer Sizes */
  73 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  74 #define IXGBE_RXBUFFER_2048  2048
  75 #define IXGBE_RXBUFFER_4096  4096
  76 #define IXGBE_RXBUFFER_8192  8192
  77 #define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */
  78
  79 /*
  80  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  81  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  82  * this adds up to 512 bytes of extra data meaning the smallest allocation
  83  * we could have is 1K.
  84  * i.e. RXBUFFER_512 --> size-1024 slab
  85  */
  86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  87
  88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  89
  90 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  91 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  92
  93 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  94 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  95 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  96 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  97 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 4)
  98 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 5)
  99 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
 101 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 102
 103 #define IXGBE_MAX_RSC_INT_RATE          162760
 104
 105 #define IXGBE_MAX_VF_MC_ENTRIES         30
 106 #define IXGBE_MAX_VF_FUNCTIONS          64
 107 #define IXGBE_MAX_VFTA_ENTRIES          128
 108 #define MAX_EMULATION_MAC_ADDRS         16
 109 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 110
 111 struct vf_data_storage {
 112         unsigned char vf_mac_addresses[ETH_ALEN];
 113         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 114         u16 num_vf_mc_hashes;
 115         u16 default_vf_vlan_id;
 116         u16 vlans_enabled;
 117         bool clear_to_send;
 118         bool pf_set_mac;
 119         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 120         u16 pf_qos;
 121 };
 122
 123 /* wrapper around a pointer to a socket buffer,
 124  * so a DMA handle can be stored along with the buffer */
 125 struct ixgbe_tx_buffer {
 126         struct sk_buff *skb;
 127         dma_addr_t dma;
 128         unsigned long time_stamp;
 129         u16 length;
 130         u16 next_to_watch;
 131         unsigned int bytecount;
 132         u16 gso_segs;
 133         u8 mapped_as_page;
 134 };
 135
 136 struct ixgbe_rx_buffer {
 137         struct sk_buff *skb;
 138         dma_addr_t dma;
 139         struct page *page;
 140         dma_addr_t page_dma;
 141         unsigned int page_offset;
 142 };
 143
 144 struct ixgbe_queue_stats {
 145         u64 packets;
 146         u64 bytes;
 147 };
 148
 149 struct ixgbe_tx_queue_stats {
 150         u64 restart_queue;
 151         u64 tx_busy;
 152         u64 completed;
 153         u64 tx_done_old;
 154 };
 155
 156 struct ixgbe_rx_queue_stats {
 157         u64 rsc_count;
 158         u64 rsc_flush;
 159         u64 non_eop_descs;
 160         u64 alloc_rx_page_failed;
 161         u64 alloc_rx_buff_failed;
 162 };
 163
 164 enum ixbge_ring_state_t {
 165         __IXGBE_TX_FDIR_INIT_DONE,
 166         __IXGBE_TX_DETECT_HANG,
 167         __IXGBE_HANG_CHECK_ARMED,
 168         __IXGBE_RX_PS_ENABLED,
 169         __IXGBE_RX_RSC_ENABLED,
 170 };
 171
 172 #define ring_is_ps_enabled(ring) \
 173         test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 174 #define set_ring_ps_enabled(ring) \
 175         set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 176 #define clear_ring_ps_enabled(ring) \
 177         clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 178 #define check_for_tx_hang(ring) \
 179         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 180 #define set_check_for_tx_hang(ring) \
 181         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 182 #define clear_check_for_tx_hang(ring) \
 183         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 184 #define ring_is_rsc_enabled(ring) \
 185         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 186 #define set_ring_rsc_enabled(ring) \
 187         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 188 #define clear_ring_rsc_enabled(ring) \
 189         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 190 struct ixgbe_ring {
 191         void *desc;                     /* descriptor ring memory */
 192         struct device *dev;             /* device for DMA mapping */
 193         struct net_device *netdev;      /* netdev ring belongs to */
 194         union {
 195                 struct ixgbe_tx_buffer *tx_buffer_info;
 196                 struct ixgbe_rx_buffer *rx_buffer_info;
 197         };
 198         unsigned long state;
 199         u8 atr_sample_rate;
 200         u8 atr_count;
 201         u16 count;                      /* amount of descriptors */
 202         u16 rx_buf_len;
 203         u16 next_to_use;
 204         u16 next_to_clean;
 205
 206         u8 queue_index; /* needed for multiqueue queue management */
 207         u8 reg_idx;                     /* holds the special value that gets
 208                                          * the hardware register offset
 209                                          * associated with this ring, which is
 210                                          * different for DCB and RSS modes
 211                                          */
 212
 213         u16 work_limit;                 /* max work per interrupt */
 214
 215         u8 __iomem *tail;
 216
 217         unsigned int total_bytes;
 218         unsigned int total_packets;
 219
 220         struct ixgbe_queue_stats stats;
 221         struct u64_stats_sync syncp;
 222         union {
 223                 struct ixgbe_tx_queue_stats tx_stats;
 224                 struct ixgbe_rx_queue_stats rx_stats;
 225         };
 226         int numa_node;
 227         unsigned int size;              /* length in bytes */
 228         dma_addr_t dma;                 /* phys. address of descriptor ring */
 229         struct rcu_head rcu;
 230         struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 231 } ____cacheline_internodealigned_in_smp;
 232
 233 enum ixgbe_ring_f_enum {
 234         RING_F_NONE = 0,
 235         RING_F_DCB,
 236         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 237         RING_F_RSS,
 238         RING_F_FDIR,
 239 #ifdef IXGBE_FCOE
 240         RING_F_FCOE,
 241 #endif /* IXGBE_FCOE */
 242
 243         RING_F_ARRAY_SIZE      /* must be last in enum set */
 244 };
 245
 246 #define IXGBE_MAX_DCB_INDICES   8
 247 #define IXGBE_MAX_RSS_INDICES  16
 248 #define IXGBE_MAX_VMDQ_INDICES 64
 249 #define IXGBE_MAX_FDIR_INDICES 64
 250 #ifdef IXGBE_FCOE
 251 #define IXGBE_MAX_FCOE_INDICES  8
 252 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 253 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 254 #else
 255 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 256 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 257 #endif /* IXGBE_FCOE */
 258 struct ixgbe_ring_feature {
 259         int indices;
 260         int mask;
 261 } ____cacheline_internodealigned_in_smp;
 262
 263
 264 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 265                               ? 8 : 1)
 266 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 267
 268 /* MAX_MSIX_Q_VECTORS of these are allocated,
 269  * but we only use one per queue-specific vector.
 270  */
 271 struct ixgbe_q_vector {
 272         struct ixgbe_adapter *adapter;
 273         unsigned int v_idx; /* index of q_vector within array, also used for
 274                              * finding the bit in EICR and friends that
 275                              * represents the vector for this ring */
 276 #ifdef CONFIG_IXGBE_DCA
 277         int cpu;            /* CPU for DCA */
 278 #endif
 279         struct napi_struct napi;
 280         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 281         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 282         u8 rxr_count;     /* Rx ring count assigned to this vector */
 283         u8 txr_count;     /* Tx ring count assigned to this vector */
 284         u8 tx_itr;
 285         u8 rx_itr;
 286         u32 eitr;
 287         cpumask_var_t affinity_mask;
 288         char name[IFNAMSIZ + 9];
 289 };
 290
 291 /* Helper macros to switch between ints/sec and what the register uses.
 292  * And yes, it's the same math going both ways.  The lowest value
 293  * supported by all of the ixgbe hardware is 8.
 294  */
 295 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 296         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
 297 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 298
 299 #define IXGBE_DESC_UNUSED(R) \
 300         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 301         (R)->next_to_clean - (R)->next_to_use - 1)
 302
 303 #define IXGBE_RX_DESC_ADV(R, i)     \
 304         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 305 #define IXGBE_TX_DESC_ADV(R, i)     \
 306         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 307 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 308         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 309
 310 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 311 #ifdef IXGBE_FCOE
 312 /* Use 3K as the baby jumbo frame size for FCoE */
 313 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 314 #endif /* IXGBE_FCOE */
 315
 316 #define OTHER_VECTOR 1
 317 #define NON_Q_VECTORS (OTHER_VECTOR)
 318
 319 #define MAX_MSIX_VECTORS_82599 64
 320 #define MAX_MSIX_Q_VECTORS_82599 64
 321 #define MAX_MSIX_VECTORS_82598 18
 322 #define MAX_MSIX_Q_VECTORS_82598 16
 323
 324 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 325 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 326
 327 #define MIN_MSIX_Q_VECTORS 2
 328 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 329
 330 /* board specific private data structure */
 331 struct ixgbe_adapter {
 332         struct timer_list watchdog_timer;
 333         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 334         u16 bd_number;
 335         struct work_struct reset_task;
 336         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 337         struct ixgbe_dcb_config dcb_cfg;
 338         struct ixgbe_dcb_config temp_dcb_cfg;
 339         u8 dcb_set_bitmap;
 340         enum ixgbe_fc_mode last_lfc_mode;
 341
 342         /* Interrupt Throttle Rate */
 343         u32 rx_itr_setting;
 344         u32 tx_itr_setting;
 345         u16 eitr_low;
 346         u16 eitr_high;
 347
 348         /* TX */
 349         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 350         int num_tx_queues;
 351         u32 tx_timeout_count;
 352         bool detect_tx_hung;
 353
 354         u64 restart_queue;
 355         u64 lsc_int;
 356
 357         /* RX */
 358         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
 359         int num_rx_queues;
 360         int num_rx_pools;               /* == num_rx_queues in 82598 */
 361         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 362         u64 hw_csum_rx_error;
 363         u64 hw_rx_no_dma_resources;
 364         u64 non_eop_descs;
 365         int num_msix_vectors;
 366         int max_msix_q_vectors;         /* true count of q_vectors for device */
 367         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 368         struct msix_entry *msix_entries;
 369
 370         u32 alloc_rx_page_failed;
 371         u32 alloc_rx_buff_failed;
 372
 373         /* Some features need tri-state capability,
 374          * thus the additional *_CAPABLE flags.
 375          */
 376         u32 flags;
 377 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 378 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 379 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 380 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 381 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 382 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 383 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 384 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 385 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 386 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 387 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 388 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 389 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 390 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 391 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 392 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 393 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 394 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 395 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 396 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 397 #define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 23)
 398 #define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 24)
 399 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 25)
 400 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 26)
 401 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 27)
 402 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 28)
 403 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 29)
 404 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 30)
 405
 406         u32 flags2;
 407 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 408 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 409 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 410 /* default to trying for four seconds */
 411 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 412
 413         /* OS defined structs */
 414         struct net_device *netdev;
 415         struct pci_dev *pdev;
 416
 417         u32 test_icr;
 418         struct ixgbe_ring test_tx_ring;
 419         struct ixgbe_ring test_rx_ring;
 420
 421         /* structs defined in ixgbe_hw.h */
 422         struct ixgbe_hw hw;
 423         u16 msg_enable;
 424         struct ixgbe_hw_stats stats;
 425
 426         /* Interrupt Throttle Rate */
 427         u32 rx_eitr_param;
 428         u32 tx_eitr_param;
 429
 430         unsigned long state;
 431         u64 tx_busy;
 432         unsigned int tx_ring_count;
 433         unsigned int rx_ring_count;
 434
 435         u32 link_speed;
 436         bool link_up;
 437         unsigned long link_check_timeout;
 438
 439         struct work_struct watchdog_task;
 440         struct work_struct sfp_task;
 441         struct timer_list sfp_timer;
 442         struct work_struct multispeed_fiber_task;
 443         struct work_struct sfp_config_module_task;
 444         u32 fdir_pballoc;
 445         u32 atr_sample_rate;
 446         spinlock_t fdir_perfect_lock;
 447         struct work_struct fdir_reinit_task;
 448 #ifdef IXGBE_FCOE
 449         struct ixgbe_fcoe fcoe;
 450 #endif /* IXGBE_FCOE */
 451         u64 rsc_total_count;
 452         u64 rsc_total_flush;
 453         u32 wol;
 454         u16 eeprom_version;
 455
 456         int node;
 457         struct work_struct check_overtemp_task;
 458         u32 interrupt_event;
 459         char lsc_int_name[IFNAMSIZ + 9];
 460
 461         /* SR-IOV */
 462         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 463         unsigned int num_vfs;
 464         struct vf_data_storage *vfinfo;
 465 };
 466
 467 enum ixbge_state_t {
 468         __IXGBE_TESTING,
 469         __IXGBE_RESETTING,
 470         __IXGBE_DOWN,
 471         __IXGBE_SFP_MODULE_NOT_FOUND
 472 };
 473
 474 struct ixgbe_rsc_cb {
 475         dma_addr_t dma;
 476         u16 skb_cnt;
 477         bool delay_unmap;
 478 };
 479 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
 480
 481 enum ixgbe_boards {
 482         board_82598,
 483         board_82599,
 484         board_X540,
 485 };
 486
 487 extern struct ixgbe_info ixgbe_82598_info;
 488 extern struct ixgbe_info ixgbe_82599_info;
 489 extern struct ixgbe_info ixgbe_X540_info;
 490 #ifdef CONFIG_IXGBE_DCB
 491 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 492 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 493                               struct ixgbe_dcb_config *dst_dcb_cfg,
 494                               int tc_max);
 495 #endif
 496
 497 extern char ixgbe_driver_name[];
 498 extern const char ixgbe_driver_version[];
 499
 500 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 501 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 502 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 503 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 504 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 505 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 506 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 507 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 508 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 509 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 510 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 511 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 512                                    struct ixgbe_ring *);
 513 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 514 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 515 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 516 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 517                                          struct ixgbe_adapter *,
 518                                          struct ixgbe_ring *);
 519 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 520                                              struct ixgbe_tx_buffer *);
 521 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 522 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 523 extern int ethtool_ioctl(struct ifreq *ifr);
 524 extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);
 525 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 526 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 527 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
 528 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 529                                                  union ixgbe_atr_hash_dword input,
 530                                                  union ixgbe_atr_hash_dword common,
 531                                                  u8 queue);
 532 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
 533                                       union ixgbe_atr_input *input,
 534                                       struct ixgbe_atr_input_masks *input_masks,
 535                                       u16 soft_id, u8 queue);
 536 extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
 537                                    struct ixgbe_ring *ring);
 538 extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
 539                                struct ixgbe_ring *ring);
 540 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 541 #ifdef IXGBE_FCOE
 542 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 543 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
 544                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 545                      u32 tx_flags, u8 *hdr_len);
 546 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 547 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 548                           union ixgbe_adv_rx_desc *rx_desc,
 549                           struct sk_buff *skb);
 550 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 551                               struct scatterlist *sgl, unsigned int sgc);
 552 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 553 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 554 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 555 #ifdef CONFIG_IXGBE_DCB
 556 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 557 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 558 #endif /* CONFIG_IXGBE_DCB */
 559 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 560 #endif /* IXGBE_FCOE */
 561
 562 #endif /* _IXGBE_H_ */