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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / ixgbe / ixgbe_82599.c
blob8d316d9cd29d40c0b59b0db9de2fff1ec1e76638
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
63 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
64
65 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
66 {
67 struct ixgbe_mac_info *mac = &hw->mac;
68
69 /* enable the laser control functions for SFP+ fiber */
70 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
71 mac->ops.disable_tx_laser =
72 &ixgbe_disable_tx_laser_multispeed_fiber;
73 mac->ops.enable_tx_laser =
74 &ixgbe_enable_tx_laser_multispeed_fiber;
75 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
76 } else {
77 mac->ops.disable_tx_laser = NULL;
78 mac->ops.enable_tx_laser = NULL;
79 mac->ops.flap_tx_laser = NULL;
80 }
81
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
85 } else {
86 if ((mac->ops.get_media_type(hw) ==
87 ixgbe_media_type_backplane) &&
88 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
89 hw->phy.smart_speed == ixgbe_smart_speed_on))
90 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
91 else
92 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
93 }
94 }
95
96 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97 {
98 s32 ret_val = 0;
99 u32 reg_anlp1 = 0;
100 u32 i = 0;
101 u16 list_offset, data_offset, data_value;
102
103 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
104 ixgbe_init_mac_link_ops_82599(hw);
105
106 hw->phy.ops.reset = NULL;
107
108 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
109 &data_offset);
110
111 if (ret_val != 0)
112 goto setup_sfp_out;
113
114 /* PHY config will finish before releasing the semaphore */
115 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
116 if (ret_val != 0) {
117 ret_val = IXGBE_ERR_SWFW_SYNC;
118 goto setup_sfp_out;
119 }
120
121 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
122 while (data_value != 0xffff) {
123 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
124 IXGBE_WRITE_FLUSH(hw);
125 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
126 }
127
128 /* Release the semaphore */
129 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
130 /* Delay obtaining semaphore again to allow FW access */
131 msleep(hw->eeprom.semaphore_delay);
132
133 /* Now restart DSP by setting Restart_AN and clearing LMS */
134 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
135 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
136 IXGBE_AUTOC_AN_RESTART));
137
138 /* Wait for AN to leave state 0 */
139 for (i = 0; i < 10; i++) {
140 msleep(4);
141 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
142 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
143 break;
144 }
145 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
146 hw_dbg(hw, "sfp module setup not complete\n");
147 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
148 goto setup_sfp_out;
149 }
150
151 /* Restart DSP by setting Restart_AN and return to SFI mode */
152 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
153 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
154 IXGBE_AUTOC_AN_RESTART));
155 }
156
157 setup_sfp_out:
158 return ret_val;
159 }
160
161 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
162 {
163 struct ixgbe_mac_info *mac = &hw->mac;
164
165 ixgbe_init_mac_link_ops_82599(hw);
166
167 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
168 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
169 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
170 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
171 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
172 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
173
174 return 0;
175 }
176
177 /**
178 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
179 * @hw: pointer to hardware structure
180 *
181 * Initialize any function pointers that were not able to be
182 * set during get_invariants because the PHY/SFP type was
183 * not known. Perform the SFP init if necessary.
184 *
185 **/
186 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
187 {
188 struct ixgbe_mac_info *mac = &hw->mac;
189 struct ixgbe_phy_info *phy = &hw->phy;
190 s32 ret_val = 0;
191
192 /* Identify the PHY or SFP module */
193 ret_val = phy->ops.identify(hw);
194
195 /* Setup function pointers based on detected SFP module and speeds */
196 ixgbe_init_mac_link_ops_82599(hw);
197
198 /* If copper media, overwrite with copper function pointers */
199 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
200 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
201 mac->ops.get_link_capabilities =
202 &ixgbe_get_copper_link_capabilities_generic;
203 }
204
205 /* Set necessary function pointers based on phy type */
206 switch (hw->phy.type) {
207 case ixgbe_phy_tn:
208 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
209 phy->ops.get_firmware_version =
210 &ixgbe_get_phy_firmware_version_tnx;
211 break;
212 case ixgbe_phy_aq:
213 phy->ops.get_firmware_version =
214 &ixgbe_get_phy_firmware_version_generic;
215 break;
216 default:
217 break;
218 }
219
220 return ret_val;
221 }
222
223 /**
224 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
225 * @hw: pointer to hardware structure
226 * @speed: pointer to link speed
227 * @negotiation: true when autoneg or autotry is enabled
228 *
229 * Determines the link capabilities by reading the AUTOC register.
230 **/
231 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
232 ixgbe_link_speed *speed,
233 bool *negotiation)
234 {
235 s32 status = 0;
236 u32 autoc = 0;
237
238 /* Determine 1G link capabilities off of SFP+ type */
239 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
240 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
241 *speed = IXGBE_LINK_SPEED_1GB_FULL;
242 *negotiation = true;
243 goto out;
244 }
245
246 /*
247 * Determine link capabilities based on the stored value of AUTOC,
248 * which represents EEPROM defaults. If AUTOC value has not been
249 * stored, use the current register value.
250 */
251 if (hw->mac.orig_link_settings_stored)
252 autoc = hw->mac.orig_autoc;
253 else
254 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
255
256 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
257 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
258 *speed = IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = false;
260 break;
261
262 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
263 *speed = IXGBE_LINK_SPEED_10GB_FULL;
264 *negotiation = false;
265 break;
266
267 case IXGBE_AUTOC_LMS_1G_AN:
268 *speed = IXGBE_LINK_SPEED_1GB_FULL;
269 *negotiation = true;
270 break;
271
272 case IXGBE_AUTOC_LMS_10G_SERIAL:
273 *speed = IXGBE_LINK_SPEED_10GB_FULL;
274 *negotiation = false;
275 break;
276
277 case IXGBE_AUTOC_LMS_KX4_KX_KR:
278 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
279 *speed = IXGBE_LINK_SPEED_UNKNOWN;
280 if (autoc & IXGBE_AUTOC_KR_SUPP)
281 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
282 if (autoc & IXGBE_AUTOC_KX4_SUPP)
283 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
284 if (autoc & IXGBE_AUTOC_KX_SUPP)
285 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
286 *negotiation = true;
287 break;
288
289 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
290 *speed = IXGBE_LINK_SPEED_100_FULL;
291 if (autoc & IXGBE_AUTOC_KR_SUPP)
292 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
293 if (autoc & IXGBE_AUTOC_KX4_SUPP)
294 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
295 if (autoc & IXGBE_AUTOC_KX_SUPP)
296 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
297 *negotiation = true;
298 break;
299
300 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
301 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
302 *negotiation = false;
303 break;
304
305 default:
306 status = IXGBE_ERR_LINK_SETUP;
307 goto out;
308 break;
309 }
310
311 if (hw->phy.multispeed_fiber) {
312 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
313 IXGBE_LINK_SPEED_1GB_FULL;
314 *negotiation = true;
315 }
316
317 out:
318 return status;
319 }
320
321 /**
322 * ixgbe_get_media_type_82599 - Get media type
323 * @hw: pointer to hardware structure
324 *
325 * Returns the media type (fiber, copper, backplane)
326 **/
327 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
328 {
329 enum ixgbe_media_type media_type;
330
331 /* Detect if there is a copper PHY attached. */
332 if (hw->phy.type == ixgbe_phy_cu_unknown ||
333 hw->phy.type == ixgbe_phy_tn ||
334 hw->phy.type == ixgbe_phy_aq) {
335 media_type = ixgbe_media_type_copper;
336 goto out;
337 }
338
339 switch (hw->device_id) {
340 case IXGBE_DEV_ID_82599_KX4:
341 case IXGBE_DEV_ID_82599_KX4_MEZZ:
342 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
343 case IXGBE_DEV_ID_82599_KR:
344 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
345 case IXGBE_DEV_ID_82599_XAUI_LOM:
346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane;
348 break;
349 case IXGBE_DEV_ID_82599_SFP:
350 case IXGBE_DEV_ID_82599_SFP_FCOE:
351 case IXGBE_DEV_ID_82599_SFP_EM:
352 media_type = ixgbe_media_type_fiber;
353 break;
354 case IXGBE_DEV_ID_82599_CX4:
355 media_type = ixgbe_media_type_cx4;
356 break;
357 default:
358 media_type = ixgbe_media_type_unknown;
359 break;
360 }
361 out:
362 return media_type;
363 }
364
365 /**
366 * ixgbe_start_mac_link_82599 - Setup MAC link settings
367 * @hw: pointer to hardware structure
368 * @autoneg_wait_to_complete: true when waiting for completion is needed
369 *
370 * Configures link settings based on values in the ixgbe_hw struct.
371 * Restarts the link. Performs autonegotiation if needed.
372 **/
373 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
374 bool autoneg_wait_to_complete)
375 {
376 u32 autoc_reg;
377 u32 links_reg;
378 u32 i;
379 s32 status = 0;
380
381 /* Restart link */
382 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
383 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
384 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
385
386 /* Only poll for autoneg to complete if specified to do so */
387 if (autoneg_wait_to_complete) {
388 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
389 IXGBE_AUTOC_LMS_KX4_KX_KR ||
390 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
391 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
392 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
393 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
394 links_reg = 0; /* Just in case Autoneg time = 0 */
395 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
396 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
397 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
398 break;
399 msleep(100);
400 }
401 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
402 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
403 hw_dbg(hw, "Autoneg did not complete.\n");
404 }
405 }
406 }
407
408 /* Add delay to filter out noises during initial link setup */
409 msleep(50);
410
411 return status;
412 }
413
414 /**
415 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
416 * @hw: pointer to hardware structure
417 *
418 * The base drivers may require better control over SFP+ module
419 * PHY states. This includes selectively shutting down the Tx
420 * laser on the PHY, effectively halting physical link.
421 **/
422 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
423 {
424 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
425
426 /* Disable tx laser; allow 100us to go dark per spec */
427 esdp_reg |= IXGBE_ESDP_SDP3;
428 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
429 IXGBE_WRITE_FLUSH(hw);
430 udelay(100);
431 }
432
433 /**
434 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
435 * @hw: pointer to hardware structure
436 *
437 * The base drivers may require better control over SFP+ module
438 * PHY states. This includes selectively turning on the Tx
439 * laser on the PHY, effectively starting physical link.
440 **/
441 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
442 {
443 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
444
445 /* Enable tx laser; allow 100ms to light up */
446 esdp_reg &= ~IXGBE_ESDP_SDP3;
447 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
448 IXGBE_WRITE_FLUSH(hw);
449 msleep(100);
450 }
451
452 /**
453 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
454 * @hw: pointer to hardware structure
455 *
456 * When the driver changes the link speeds that it can support,
457 * it sets autotry_restart to true to indicate that we need to
458 * initiate a new autotry session with the link partner. To do
459 * so, we set the speed then disable and re-enable the tx laser, to
460 * alert the link partner that it also needs to restart autotry on its
461 * end. This is consistent with true clause 37 autoneg, which also
462 * involves a loss of signal.
463 **/
464 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
465 {
466 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
467
468 if (hw->mac.autotry_restart) {
469 ixgbe_disable_tx_laser_multispeed_fiber(hw);
470 ixgbe_enable_tx_laser_multispeed_fiber(hw);
471 hw->mac.autotry_restart = false;
472 }
473 }
474
475 /**
476 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
477 * @hw: pointer to hardware structure
478 * @speed: new link speed
479 * @autoneg: true if autonegotiation enabled
480 * @autoneg_wait_to_complete: true when waiting for completion is needed
481 *
482 * Set the link speed in the AUTOC register and restarts link.
483 **/
484 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
485 ixgbe_link_speed speed,
486 bool autoneg,
487 bool autoneg_wait_to_complete)
488 {
489 s32 status = 0;
490 ixgbe_link_speed phy_link_speed;
491 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
492 u32 speedcnt = 0;
493 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
494 bool link_up = false;
495 bool negotiation;
496 int i;
497
498 /* Mask off requested but non-supported speeds */
499 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
500 speed &= phy_link_speed;
501
502 /*
503 * Try each speed one by one, highest priority first. We do this in
504 * software because 10gb fiber doesn't support speed autonegotiation.
505 */
506 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
507 speedcnt++;
508 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
509
510 /* If we already have link at this speed, just jump out */
511 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
512
513 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
514 goto out;
515
516 /* Set the module link speed */
517 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
518 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
519 IXGBE_WRITE_FLUSH(hw);
520
521 /* Allow module to change analog characteristics (1G->10G) */
522 msleep(40);
523
524 status = ixgbe_setup_mac_link_82599(hw,
525 IXGBE_LINK_SPEED_10GB_FULL,
526 autoneg,
527 autoneg_wait_to_complete);
528 if (status != 0)
529 return status;
530
531 /* Flap the tx laser if it has not already been done */
532 hw->mac.ops.flap_tx_laser(hw);
533
534 /*
535 * Wait for the controller to acquire link. Per IEEE 802.3ap,
536 * Section 73.10.2, we may have to wait up to 500ms if KR is
537 * attempted. 82599 uses the same timing for 10g SFI.
538 */
539
540 for (i = 0; i < 5; i++) {
541 /* Wait for the link partner to also set speed */
542 msleep(100);
543
544 /* If we have link, just jump out */
545 hw->mac.ops.check_link(hw, &phy_link_speed,
546 &link_up, false);
547 if (link_up)
548 goto out;
549 }
550 }
551
552 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
553 speedcnt++;
554 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
555 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
556
557 /* If we already have link at this speed, just jump out */
558 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
559
560 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
561 goto out;
562
563 /* Set the module link speed */
564 esdp_reg &= ~IXGBE_ESDP_SDP5;
565 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
566 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
567 IXGBE_WRITE_FLUSH(hw);
568
569 /* Allow module to change analog characteristics (10G->1G) */
570 msleep(40);
571
572 status = ixgbe_setup_mac_link_82599(hw,
573 IXGBE_LINK_SPEED_1GB_FULL,
574 autoneg,
575 autoneg_wait_to_complete);
576 if (status != 0)
577 return status;
578
579 /* Flap the tx laser if it has not already been done */
580 hw->mac.ops.flap_tx_laser(hw);
581
582 /* Wait for the link partner to also set speed */
583 msleep(100);
584
585 /* If we have link, just jump out */
586 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
587 if (link_up)
588 goto out;
589 }
590
591 /*
592 * We didn't get link. Configure back to the highest speed we tried,
593 * (if there was more than one). We call ourselves back with just the
594 * single highest speed that the user requested.
595 */
596 if (speedcnt > 1)
597 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
598 highest_link_speed,
599 autoneg,
600 autoneg_wait_to_complete);
601
602 out:
603 /* Set autoneg_advertised value based on input link speed */
604 hw->phy.autoneg_advertised = 0;
605
606 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
607 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
608
609 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
610 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
611
612 return status;
613 }
614
615 /**
616 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
617 * @hw: pointer to hardware structure
618 * @speed: new link speed
619 * @autoneg: true if autonegotiation enabled
620 * @autoneg_wait_to_complete: true when waiting for completion is needed
621 *
622 * Implements the Intel SmartSpeed algorithm.
623 **/
624 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
625 ixgbe_link_speed speed, bool autoneg,
626 bool autoneg_wait_to_complete)
627 {
628 s32 status = 0;
629 ixgbe_link_speed link_speed;
630 s32 i, j;
631 bool link_up = false;
632 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
633 struct ixgbe_adapter *adapter = hw->back;
634
635 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
636
637 /* Set autoneg_advertised value based on input link speed */
638 hw->phy.autoneg_advertised = 0;
639
640 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
641 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
642
643 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
644 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
645
646 if (speed & IXGBE_LINK_SPEED_100_FULL)
647 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
648
649 /*
650 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
651 * autoneg advertisement if link is unable to be established at the
652 * highest negotiated rate. This can sometimes happen due to integrity
653 * issues with the physical media connection.
654 */
655
656 /* First, try to get link with full advertisement */
657 hw->phy.smart_speed_active = false;
658 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
659 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
660 autoneg_wait_to_complete);
661 if (status)
662 goto out;
663
664 /*
665 * Wait for the controller to acquire link. Per IEEE 802.3ap,
666 * Section 73.10.2, we may have to wait up to 500ms if KR is
667 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
668 * Table 9 in the AN MAS.
669 */
670 for (i = 0; i < 5; i++) {
671 mdelay(100);
672
673 /* If we have link, just jump out */
674 hw->mac.ops.check_link(hw, &link_speed,
675 &link_up, false);
676 if (link_up)
677 goto out;
678 }
679 }
680
681 /*
682 * We didn't get link. If we advertised KR plus one of KX4/KX
683 * (or BX4/BX), then disable KR and try again.
684 */
685 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
686 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
687 goto out;
688
689 /* Turn SmartSpeed on to disable KR support */
690 hw->phy.smart_speed_active = true;
691 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
692 autoneg_wait_to_complete);
693 if (status)
694 goto out;
695
696 /*
697 * Wait for the controller to acquire link. 600ms will allow for
698 * the AN link_fail_inhibit_timer as well for multiple cycles of
699 * parallel detect, both 10g and 1g. This allows for the maximum
700 * connect attempts as defined in the AN MAS table 73-7.
701 */
702 for (i = 0; i < 6; i++) {
703 mdelay(100);
704
705 /* If we have link, just jump out */
706 hw->mac.ops.check_link(hw, &link_speed,
707 &link_up, false);
708 if (link_up)
709 goto out;
710 }
711
712 /* We didn't get link. Turn SmartSpeed back off. */
713 hw->phy.smart_speed_active = false;
714 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
715 autoneg_wait_to_complete);
716
717 out:
718 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
719 e_info(hw, "Smartspeed has downgraded the link speed from "
720 "the maximum advertised\n");
721 return status;
722 }
723
724 /**
725 * ixgbe_setup_mac_link_82599 - Set MAC link speed
726 * @hw: pointer to hardware structure
727 * @speed: new link speed
728 * @autoneg: true if autonegotiation enabled
729 * @autoneg_wait_to_complete: true when waiting for completion is needed
730 *
731 * Set the link speed in the AUTOC register and restarts link.
732 **/
733 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
734 ixgbe_link_speed speed, bool autoneg,
735 bool autoneg_wait_to_complete)
736 {
737 s32 status = 0;
738 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
739 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
740 u32 start_autoc = autoc;
741 u32 orig_autoc = 0;
742 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
743 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
744 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
745 u32 links_reg;
746 u32 i;
747 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
748
749 /* Check to see if speed passed in is supported. */
750 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
751 speed &= link_capabilities;
752
753 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
754 status = IXGBE_ERR_LINK_SETUP;
755 goto out;
756 }
757
758 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
759 if (hw->mac.orig_link_settings_stored)
760 orig_autoc = hw->mac.orig_autoc;
761 else
762 orig_autoc = autoc;
763
764
765 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
766 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
767 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
768 /* Set KX4/KX/KR support according to speed requested */
769 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
770 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
771 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
772 autoc |= IXGBE_AUTOC_KX4_SUPP;
773 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
774 (hw->phy.smart_speed_active == false))
775 autoc |= IXGBE_AUTOC_KR_SUPP;
776 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
777 autoc |= IXGBE_AUTOC_KX_SUPP;
778 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
779 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
780 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
781 /* Switch from 1G SFI to 10G SFI if requested */
782 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
783 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
784 autoc &= ~IXGBE_AUTOC_LMS_MASK;
785 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
786 }
787 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
788 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
789 /* Switch from 10G SFI to 1G SFI if requested */
790 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
791 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
792 autoc &= ~IXGBE_AUTOC_LMS_MASK;
793 if (autoneg)
794 autoc |= IXGBE_AUTOC_LMS_1G_AN;
795 else
796 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
797 }
798 }
799
800 if (autoc != start_autoc) {
801 /* Restart link */
802 autoc |= IXGBE_AUTOC_AN_RESTART;
803 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
804
805 /* Only poll for autoneg to complete if specified to do so */
806 if (autoneg_wait_to_complete) {
807 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
808 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
809 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
810 links_reg = 0; /*Just in case Autoneg time=0*/
811 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
812 links_reg =
813 IXGBE_READ_REG(hw, IXGBE_LINKS);
814 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
815 break;
816 msleep(100);
817 }
818 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
819 status =
820 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
821 hw_dbg(hw, "Autoneg did not "
822 "complete.\n");
823 }
824 }
825 }
826
827 /* Add delay to filter out noises during initial link setup */
828 msleep(50);
829 }
830
831 out:
832 return status;
833 }
834
835 /**
836 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
837 * @hw: pointer to hardware structure
838 * @speed: new link speed
839 * @autoneg: true if autonegotiation enabled
840 * @autoneg_wait_to_complete: true if waiting is needed to complete
841 *
842 * Restarts link on PHY and MAC based on settings passed in.
843 **/
844 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
845 ixgbe_link_speed speed,
846 bool autoneg,
847 bool autoneg_wait_to_complete)
848 {
849 s32 status;
850
851 /* Setup the PHY according to input speed */
852 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
853 autoneg_wait_to_complete);
854 /* Set up MAC */
855 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
856
857 return status;
858 }
859
860 /**
861 * ixgbe_reset_hw_82599 - Perform hardware reset
862 * @hw: pointer to hardware structure
863 *
864 * Resets the hardware by resetting the transmit and receive units, masks
865 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
866 * reset.
867 **/
868 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
869 {
870 s32 status = 0;
871 u32 ctrl;
872 u32 i;
873 u32 autoc;
874 u32 autoc2;
875
876 /* Call adapter stop to disable tx/rx and clear interrupts */
877 hw->mac.ops.stop_adapter(hw);
878
879 /* PHY ops must be identified and initialized prior to reset */
880
881 /* Init PHY and function pointers, perform SFP setup */
882 status = hw->phy.ops.init(hw);
883
884 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
885 goto reset_hw_out;
886
887 /* Setup SFP module if there is one present. */
888 if (hw->phy.sfp_setup_needed) {
889 status = hw->mac.ops.setup_sfp(hw);
890 hw->phy.sfp_setup_needed = false;
891 }
892
893 /* Reset PHY */
894 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
895 hw->phy.ops.reset(hw);
896
897 /*
898 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
899 * access and verify no pending requests before reset
900 */
901 status = ixgbe_disable_pcie_master(hw);
902 if (status != 0) {
903 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
904 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
905 }
906
907 /*
908 * Issue global reset to the MAC. This needs to be a SW reset.
909 * If link reset is used, it might reset the MAC when mng is using it
910 */
911 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
912 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
913 IXGBE_WRITE_FLUSH(hw);
914
915 /* Poll for reset bit to self-clear indicating reset is complete */
916 for (i = 0; i < 10; i++) {
917 udelay(1);
918 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
919 if (!(ctrl & IXGBE_CTRL_RST))
920 break;
921 }
922 if (ctrl & IXGBE_CTRL_RST) {
923 status = IXGBE_ERR_RESET_FAILED;
924 hw_dbg(hw, "Reset polling failed to complete.\n");
925 }
926
927 msleep(50);
928
929 /*
930 * Store the original AUTOC/AUTOC2 values if they have not been
931 * stored off yet. Otherwise restore the stored original
932 * values since the reset operation sets back to defaults.
933 */
934 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
935 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
936 if (hw->mac.orig_link_settings_stored == false) {
937 hw->mac.orig_autoc = autoc;
938 hw->mac.orig_autoc2 = autoc2;
939 hw->mac.orig_link_settings_stored = true;
940 } else {
941 if (autoc != hw->mac.orig_autoc)
942 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
943 IXGBE_AUTOC_AN_RESTART));
944
945 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
946 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
947 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
948 autoc2 |= (hw->mac.orig_autoc2 &
949 IXGBE_AUTOC2_UPPER_MASK);
950 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
951 }
952 }
953
954 /*
955 * Store MAC address from RAR0, clear receive address registers, and
956 * clear the multicast table. Also reset num_rar_entries to 128,
957 * since we modify this value when programming the SAN MAC address.
958 */
959 hw->mac.num_rar_entries = 128;
960 hw->mac.ops.init_rx_addrs(hw);
961
962 /* Store the permanent mac address */
963 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
964
965 /* Store the permanent SAN mac address */
966 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
967
968 /* Add the SAN MAC address to the RAR only if it's a valid address */
969 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
970 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
971 hw->mac.san_addr, 0, IXGBE_RAH_AV);
972
973 /* Reserve the last RAR for the SAN MAC address */
974 hw->mac.num_rar_entries--;
975 }
976
977 /* Store the alternative WWNN/WWPN prefix */
978 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
979 &hw->mac.wwpn_prefix);
980
981 reset_hw_out:
982 return status;
983 }
984
985 /**
986 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
987 * @hw: pointer to hardware structure
988 **/
989 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
990 {
991 int i;
992 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
993 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
994
995 /*
996 * Before starting reinitialization process,
997 * FDIRCMD.CMD must be zero.
998 */
999 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1000 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1001 IXGBE_FDIRCMD_CMD_MASK))
1002 break;
1003 udelay(10);
1004 }
1005 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1006 hw_dbg(hw, "Flow Director previous command isn't complete, "
1007 "aborting table re-initialization.\n");
1008 return IXGBE_ERR_FDIR_REINIT_FAILED;
1009 }
1010
1011 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1012 IXGBE_WRITE_FLUSH(hw);
1013 /*
1014 * 82599 adapters flow director init flow cannot be restarted,
1015 * Workaround 82599 silicon errata by performing the following steps
1016 * before re-writing the FDIRCTRL control register with the same value.
1017 * - write 1 to bit 8 of FDIRCMD register &
1018 * - write 0 to bit 8 of FDIRCMD register
1019 */
1020 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1021 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1022 IXGBE_FDIRCMD_CLEARHT));
1023 IXGBE_WRITE_FLUSH(hw);
1024 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1025 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1026 ~IXGBE_FDIRCMD_CLEARHT));
1027 IXGBE_WRITE_FLUSH(hw);
1028 /*
1029 * Clear FDIR Hash register to clear any leftover hashes
1030 * waiting to be programmed.
1031 */
1032 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1033 IXGBE_WRITE_FLUSH(hw);
1034
1035 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1036 IXGBE_WRITE_FLUSH(hw);
1037
1038 /* Poll init-done after we write FDIRCTRL register */
1039 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1040 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1041 IXGBE_FDIRCTRL_INIT_DONE)
1042 break;
1043 udelay(10);
1044 }
1045 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1046 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1047 return IXGBE_ERR_FDIR_REINIT_FAILED;
1048 }
1049
1050 /* Clear FDIR statistics registers (read to clear) */
1051 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1052 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1053 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1054 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1055 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1056
1057 return 0;
1058 }
1059
1060 /**
1061 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1062 * @hw: pointer to hardware structure
1063 * @pballoc: which mode to allocate filters with
1064 **/
1065 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1066 {
1067 u32 fdirctrl = 0;
1068 u32 pbsize;
1069 int i;
1070
1071 /*
1072 * Before enabling Flow Director, the Rx Packet Buffer size
1073 * must be reduced. The new value is the current size minus
1074 * flow director memory usage size.
1075 */
1076 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1077 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1078 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1079
1080 /*
1081 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1082 * intialized to zero for non DCB mode otherwise actual total RX PB
1083 * would be bigger than programmed and filter space would run into
1084 * the PB 0 region.
1085 */
1086 for (i = 1; i < 8; i++)
1087 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1088
1089 /* Send interrupt when 64 filters are left */
1090 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1091
1092 /* Set the maximum length per hash bucket to 0xA filters */
1093 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1094
1095 switch (pballoc) {
1096 case IXGBE_FDIR_PBALLOC_64K:
1097 /* 8k - 1 signature filters */
1098 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1099 break;
1100 case IXGBE_FDIR_PBALLOC_128K:
1101 /* 16k - 1 signature filters */
1102 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1103 break;
1104 case IXGBE_FDIR_PBALLOC_256K:
1105 /* 32k - 1 signature filters */
1106 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1107 break;
1108 default:
1109 /* bad value */
1110 return IXGBE_ERR_CONFIG;
1111 };
1112
1113 /* Move the flexible bytes to use the ethertype - shift 6 words */
1114 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1115
1116
1117 /* Prime the keys for hashing */
1118 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1119 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1120
1121 /*
1122 * Poll init-done after we write the register. Estimated times:
1123 * 10G: PBALLOC = 11b, timing is 60us
1124 * 1G: PBALLOC = 11b, timing is 600us
1125 * 100M: PBALLOC = 11b, timing is 6ms
1126 *
1127 * Multiple these timings by 4 if under full Rx load
1128 *
1129 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1130 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1131 * this might not finish in our poll time, but we can live with that
1132 * for now.
1133 */
1134 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1135 IXGBE_WRITE_FLUSH(hw);
1136 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1137 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1138 IXGBE_FDIRCTRL_INIT_DONE)
1139 break;
1140 msleep(1);
1141 }
1142 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1143 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1144
1145 return 0;
1146 }
1147
1148 /**
1149 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1150 * @hw: pointer to hardware structure
1151 * @pballoc: which mode to allocate filters with
1152 **/
1153 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1154 {
1155 u32 fdirctrl = 0;
1156 u32 pbsize;
1157 int i;
1158
1159 /*
1160 * Before enabling Flow Director, the Rx Packet Buffer size
1161 * must be reduced. The new value is the current size minus
1162 * flow director memory usage size.
1163 */
1164 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1165 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1166 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1167
1168 /*
1169 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1170 * intialized to zero for non DCB mode otherwise actual total RX PB
1171 * would be bigger than programmed and filter space would run into
1172 * the PB 0 region.
1173 */
1174 for (i = 1; i < 8; i++)
1175 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1176
1177 /* Send interrupt when 64 filters are left */
1178 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1179
1180 /* Initialize the drop queue to Rx queue 127 */
1181 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1182
1183 switch (pballoc) {
1184 case IXGBE_FDIR_PBALLOC_64K:
1185 /* 2k - 1 perfect filters */
1186 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1187 break;
1188 case IXGBE_FDIR_PBALLOC_128K:
1189 /* 4k - 1 perfect filters */
1190 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1191 break;
1192 case IXGBE_FDIR_PBALLOC_256K:
1193 /* 8k - 1 perfect filters */
1194 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1195 break;
1196 default:
1197 /* bad value */
1198 return IXGBE_ERR_CONFIG;
1199 };
1200
1201 /* Turn perfect match filtering on */
1202 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1203 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1204
1205 /* Move the flexible bytes to use the ethertype - shift 6 words */
1206 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1207
1208 /* Prime the keys for hashing */
1209 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1210 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1211
1212 /*
1213 * Poll init-done after we write the register. Estimated times:
1214 * 10G: PBALLOC = 11b, timing is 60us
1215 * 1G: PBALLOC = 11b, timing is 600us
1216 * 100M: PBALLOC = 11b, timing is 6ms
1217 *
1218 * Multiple these timings by 4 if under full Rx load
1219 *
1220 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1221 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1222 * this might not finish in our poll time, but we can live with that
1223 * for now.
1224 */
1225
1226 /* Set the maximum length per hash bucket to 0xA filters */
1227 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1228
1229 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1230 IXGBE_WRITE_FLUSH(hw);
1231 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1232 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1233 IXGBE_FDIRCTRL_INIT_DONE)
1234 break;
1235 msleep(1);
1236 }
1237 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1238 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1239
1240 return 0;
1241 }
1242
1243
1244 /**
1245 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1246 * @stream: input bitstream to compute the hash on
1247 * @key: 32-bit hash key
1248 **/
1249 static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1250 u32 key)
1251 {
1252 /*
1253 * The algorithm is as follows:
1254 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1255 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1256 * and A[n] x B[n] is bitwise AND between same length strings
1257 *
1258 * K[n] is 16 bits, defined as:
1259 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1260 * for n modulo 32 < 15, K[n] =
1261 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1262 *
1263 * S[n] is 16 bits, defined as:
1264 * for n >= 15, S[n] = S[n:n - 15]
1265 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1266 *
1267 * To simplify for programming, the algorithm is implemented
1268 * in software this way:
1269 *
1270 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1271 *
1272 * for (i = 0; i < 352; i+=32)
1273 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1274 *
1275 * lo_hash_dword[15:0] ^= Stream[15:0];
1276 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1277 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1278 *
1279 * hi_hash_dword[31:0] ^= Stream[351:320];
1280 *
1281 * if(key[0])
1282 * hash[15:0] ^= Stream[15:0];
1283 *
1284 * for (i = 0; i < 16; i++) {
1285 * if (key[i])
1286 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1287 * if (key[i + 16])
1288 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1289 * }
1290 *
1291 */
1292 __be32 common_hash_dword = 0;
1293 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1294 u32 hash_result = 0;
1295 u8 i;
1296
1297 /* record the flow_vm_vlan bits as they are a key part to the hash */
1298 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
1299
1300 /* generate common hash dword */
1301 for (i = 10; i; i -= 2)
1302 common_hash_dword ^= atr_input->dword_stream[i] ^
1303 atr_input->dword_stream[i - 1];
1304
1305 hi_hash_dword = ntohl(common_hash_dword);
1306
1307 /* low dword is word swapped version of common */
1308 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1309
1310 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1311 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1312
1313 /* Process bits 0 and 16 */
1314 if (key & 0x0001) hash_result ^= lo_hash_dword;
1315 if (key & 0x00010000) hash_result ^= hi_hash_dword;
1316
1317 /*
1318 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1319 * delay this because bit 0 of the stream should not be processed
1320 * so we do not add the vlan until after bit 0 was processed
1321 */
1322 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1323
1324
1325 /* process the remaining 30 bits in the key 2 bits at a time */
1326 for (i = 15; i; i-- ) {
1327 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1328 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
1329 }
1330
1331 return hash_result & IXGBE_ATR_HASH_MASK;
1332 }
1333
1334 /*
1335 * These defines allow us to quickly generate all of the necessary instructions
1336 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1337 * for values 0 through 15
1338 */
1339 #define IXGBE_ATR_COMMON_HASH_KEY \
1340 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1341 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1342 do { \
1343 u32 n = (_n); \
1344 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1345 common_hash ^= lo_hash_dword >> n; \
1346 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1347 bucket_hash ^= lo_hash_dword >> n; \
1348 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1349 sig_hash ^= lo_hash_dword << (16 - n); \
1350 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1351 common_hash ^= hi_hash_dword >> n; \
1352 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1353 bucket_hash ^= hi_hash_dword >> n; \
1354 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1355 sig_hash ^= hi_hash_dword << (16 - n); \
1356 } while (0);
1357
1358 /**
1359 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1360 * @stream: input bitstream to compute the hash on
1361 *
1362 * This function is almost identical to the function above but contains
1363 * several optomizations such as unwinding all of the loops, letting the
1364 * compiler work out all of the conditional ifs since the keys are static
1365 * defines, and computing two keys at once since the hashed dword stream
1366 * will be the same for both keys.
1367 **/
1368 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1369 union ixgbe_atr_hash_dword common)
1370 {
1371 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1372 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1373
1374 /* record the flow_vm_vlan bits as they are a key part to the hash */
1375 flow_vm_vlan = ntohl(input.dword);
1376
1377 /* generate common hash dword */
1378 hi_hash_dword = ntohl(common.dword);
1379
1380 /* low dword is word swapped version of common */
1381 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1382
1383 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1384 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1385
1386 /* Process bits 0 and 16 */
1387 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1388
1389 /*
1390 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1391 * delay this because bit 0 of the stream should not be processed
1392 * so we do not add the vlan until after bit 0 was processed
1393 */
1394 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1395
1396 /* Process remaining 30 bit of the key */
1397 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1398 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1399 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1400 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1401 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1402 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1403 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1404 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1405 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1406 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1407 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1408 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1409 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1410 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1411 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1412
1413 /* combine common_hash result with signature and bucket hashes */
1414 bucket_hash ^= common_hash;
1415 bucket_hash &= IXGBE_ATR_HASH_MASK;
1416
1417 sig_hash ^= common_hash << 16;
1418 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1419
1420 /* return completed signature hash */
1421 return sig_hash ^ bucket_hash;
1422 }
1423
1424 /**
1425 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1426 * @hw: pointer to hardware structure
1427 * @input: unique input dword
1428 * @common: compressed common input dword
1429 * @queue: queue index to direct traffic to
1430 **/
1431 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1432 union ixgbe_atr_hash_dword input,
1433 union ixgbe_atr_hash_dword common,
1434 u8 queue)
1435 {
1436 u64 fdirhashcmd;
1437 u32 fdircmd;
1438
1439 /*
1440 * Get the flow_type in order to program FDIRCMD properly
1441 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1442 */
1443 switch (input.formatted.flow_type) {
1444 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1445 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1446 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1447 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1448 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1449 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1450 break;
1451 default:
1452 hw_dbg(hw, " Error on flow type input\n");
1453 return IXGBE_ERR_CONFIG;
1454 }
1455
1456 /* configure FDIRCMD register */
1457 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1458 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1459 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1460 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1461
1462 /*
1463 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1464 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1465 */
1466 fdirhashcmd = (u64)fdircmd << 32;
1467 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1468
1469 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1470
1471 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1472
1473 return 0;
1474 }
1475
1476 /**
1477 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1478 * @input_mask: mask to be bit swapped
1479 *
1480 * The source and destination port masks for flow director are bit swapped
1481 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1482 * generate a correctly swapped value we need to bit swap the mask and that
1483 * is what is accomplished by this function.
1484 **/
1485 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1486 {
1487 u32 mask = ntohs(input_masks->dst_port_mask);
1488 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1489 mask |= ntohs(input_masks->src_port_mask);
1490 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1491 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1492 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1493 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1494 }
1495
1496 /*
1497 * These two macros are meant to address the fact that we have registers
1498 * that are either all or in part big-endian. As a result on big-endian
1499 * systems we will end up byte swapping the value to little-endian before
1500 * it is byte swapped again and written to the hardware in the original
1501 * big-endian format.
1502 */
1503 #define IXGBE_STORE_AS_BE32(_value) \
1504 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1505 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1506
1507 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1508 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1509
1510 #define IXGBE_STORE_AS_BE16(_value) \
1511 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1512
1513 /**
1514 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1515 * @hw: pointer to hardware structure
1516 * @input: input bitstream
1517 * @input_masks: bitwise masks for relevant fields
1518 * @soft_id: software index into the silicon hash tables for filter storage
1519 * @queue: queue index to direct traffic to
1520 *
1521 * Note that the caller to this function must lock before calling, since the
1522 * hardware writes must be protected from one another.
1523 **/
1524 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1525 union ixgbe_atr_input *input,
1526 struct ixgbe_atr_input_masks *input_masks,
1527 u16 soft_id, u8 queue)
1528 {
1529 u32 fdirhash;
1530 u32 fdircmd;
1531 u32 fdirport, fdirtcpm;
1532 u32 fdirvlan;
1533 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1534 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1535 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
1536
1537 /*
1538 * Check flow_type formatting, and bail out before we touch the hardware
1539 * if there's a configuration issue
1540 */
1541 switch (input->formatted.flow_type) {
1542 case IXGBE_ATR_FLOW_TYPE_IPV4:
1543 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1544 fdirm |= IXGBE_FDIRM_L4P;
1545 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1546 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1547 hw_dbg(hw, " Error on src/dst port mask\n");
1548 return IXGBE_ERR_CONFIG;
1549 }
1550 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1551 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1552 break;
1553 default:
1554 hw_dbg(hw, " Error on flow type input\n");
1555 return IXGBE_ERR_CONFIG;
1556 }
1557
1558 /*
1559 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1560 * are zero, then assume a full mask for that field. Also assume that
1561 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1562 * cannot be masked out in this implementation.
1563 *
1564 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1565 * point in time.
1566 */
1567
1568 /* Program FDIRM */
1569 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1570 case 0xEFFF:
1571 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1572 fdirm &= ~IXGBE_FDIRM_VLANID;
1573 case 0xE000:
1574 /* Unmask VLAN prio - bit 1 */
1575 fdirm &= ~IXGBE_FDIRM_VLANP;
1576 break;
1577 case 0x0FFF:
1578 /* Unmask VLAN ID - bit 0 */
1579 fdirm &= ~IXGBE_FDIRM_VLANID;
1580 break;
1581 case 0x0000:
1582 /* do nothing, vlans already masked */
1583 break;
1584 default:
1585 hw_dbg(hw, " Error on VLAN mask\n");
1586 return IXGBE_ERR_CONFIG;
1587 }
1588
1589 if (input_masks->flex_mask & 0xFFFF) {
1590 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1591 hw_dbg(hw, " Error on flexible byte mask\n");
1592 return IXGBE_ERR_CONFIG;
1593 }
1594 /* Unmask Flex Bytes - bit 4 */
1595 fdirm &= ~IXGBE_FDIRM_FLEX;
1596 }
1597
1598 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1599 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1600
1601 /* store the TCP/UDP port masks, bit reversed from port layout */
1602 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1603
1604 /* write both the same so that UDP and TCP use the same mask */
1605 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1606 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1607
1608 /* store source and destination IP masks (big-enian) */
1609 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1610 ~input_masks->src_ip_mask[0]);
1611 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1612 ~input_masks->dst_ip_mask[0]);
1613
1614 /* Apply masks to input data */
1615 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1616 input->formatted.flex_bytes &= input_masks->flex_mask;
1617 input->formatted.src_port &= input_masks->src_port_mask;
1618 input->formatted.dst_port &= input_masks->dst_port_mask;
1619 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1620 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1621
1622 /* record vlan (little-endian) and flex_bytes(big-endian) */
1623 fdirvlan =
1624 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1625 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1626 fdirvlan |= ntohs(input->formatted.vlan_id);
1627 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1628
1629 /* record source and destination port (little-endian)*/
1630 fdirport = ntohs(input->formatted.dst_port);
1631 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1632 fdirport |= ntohs(input->formatted.src_port);
1633 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1634
1635 /* record the first 32 bits of the destination address (big-endian) */
1636 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1637
1638 /* record the source address (big-endian) */
1639 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1640
1641 /* configure FDIRCMD register */
1642 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1643 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1644 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1645 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1646
1647 /* we only want the bucket hash so drop the upper 16 bits */
1648 fdirhash = ixgbe_atr_compute_hash_82599(input,
1649 IXGBE_ATR_BUCKET_HASH_KEY);
1650 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1651
1652 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1653 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1654
1655 return 0;
1656 }
1657
1658 /**
1659 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1660 * @hw: pointer to hardware structure
1661 * @reg: analog register to read
1662 * @val: read value
1663 *
1664 * Performs read operation to Omer analog register specified.
1665 **/
1666 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1667 {
1668 u32 core_ctl;
1669
1670 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1671 (reg << 8));
1672 IXGBE_WRITE_FLUSH(hw);
1673 udelay(10);
1674 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1675 *val = (u8)core_ctl;
1676
1677 return 0;
1678 }
1679
1680 /**
1681 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1682 * @hw: pointer to hardware structure
1683 * @reg: atlas register to write
1684 * @val: value to write
1685 *
1686 * Performs write operation to Omer analog register specified.
1687 **/
1688 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1689 {
1690 u32 core_ctl;
1691
1692 core_ctl = (reg << 8) | val;
1693 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1694 IXGBE_WRITE_FLUSH(hw);
1695 udelay(10);
1696
1697 return 0;
1698 }
1699
1700 /**
1701 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1702 * @hw: pointer to hardware structure
1703 *
1704 * Starts the hardware using the generic start_hw function.
1705 * Then performs device-specific:
1706 * Clears the rate limiter registers.
1707 **/
1708 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1709 {
1710 u32 q_num;
1711 s32 ret_val;
1712
1713 ret_val = ixgbe_start_hw_generic(hw);
1714
1715 /* Clear the rate limiters */
1716 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1717 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1718 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1719 }
1720 IXGBE_WRITE_FLUSH(hw);
1721
1722 /* We need to run link autotry after the driver loads */
1723 hw->mac.autotry_restart = true;
1724
1725 if (ret_val == 0)
1726 ret_val = ixgbe_verify_fw_version_82599(hw);
1727
1728 return ret_val;
1729 }
1730
1731 /**
1732 * ixgbe_identify_phy_82599 - Get physical layer module
1733 * @hw: pointer to hardware structure
1734 *
1735 * Determines the physical layer module found on the current adapter.
1736 **/
1737 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1738 {
1739 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1740 status = ixgbe_identify_phy_generic(hw);
1741 if (status != 0)
1742 status = ixgbe_identify_sfp_module_generic(hw);
1743 return status;
1744 }
1745
1746 /**
1747 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1748 * @hw: pointer to hardware structure
1749 *
1750 * Determines physical layer capabilities of the current configuration.
1751 **/
1752 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1753 {
1754 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1755 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1756 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1757 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1758 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1759 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1760 u16 ext_ability = 0;
1761 u8 comp_codes_10g = 0;
1762 u8 comp_codes_1g = 0;
1763
1764 hw->phy.ops.identify(hw);
1765
1766 if (hw->phy.type == ixgbe_phy_tn ||
1767 hw->phy.type == ixgbe_phy_aq ||
1768 hw->phy.type == ixgbe_phy_cu_unknown) {
1769 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1770 &ext_ability);
1771 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1772 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1773 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1774 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1775 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1776 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1777 goto out;
1778 }
1779
1780 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1781 case IXGBE_AUTOC_LMS_1G_AN:
1782 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1783 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1784 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1785 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1786 goto out;
1787 } else
1788 /* SFI mode so read SFP module */
1789 goto sfp_check;
1790 break;
1791 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1792 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1793 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1794 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1795 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1796 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1797 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1798 goto out;
1799 break;
1800 case IXGBE_AUTOC_LMS_10G_SERIAL:
1801 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1802 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1803 goto out;
1804 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1805 goto sfp_check;
1806 break;
1807 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1808 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1809 if (autoc & IXGBE_AUTOC_KX_SUPP)
1810 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1811 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1812 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1813 if (autoc & IXGBE_AUTOC_KR_SUPP)
1814 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1815 goto out;
1816 break;
1817 default:
1818 goto out;
1819 break;
1820 }
1821
1822 sfp_check:
1823 /* SFP check must be done last since DA modules are sometimes used to
1824 * test KR mode - we need to id KR mode correctly before SFP module.
1825 * Call identify_sfp because the pluggable module may have changed */
1826 hw->phy.ops.identify_sfp(hw);
1827 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1828 goto out;
1829
1830 switch (hw->phy.type) {
1831 case ixgbe_phy_sfp_passive_tyco:
1832 case ixgbe_phy_sfp_passive_unknown:
1833 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1834 break;
1835 case ixgbe_phy_sfp_ftl_active:
1836 case ixgbe_phy_sfp_active_unknown:
1837 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1838 break;
1839 case ixgbe_phy_sfp_avago:
1840 case ixgbe_phy_sfp_ftl:
1841 case ixgbe_phy_sfp_intel:
1842 case ixgbe_phy_sfp_unknown:
1843 hw->phy.ops.read_i2c_eeprom(hw,
1844 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1845 hw->phy.ops.read_i2c_eeprom(hw,
1846 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1847 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1848 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1849 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1850 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1851 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1852 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1853 break;
1854 default:
1855 break;
1856 }
1857
1858 out:
1859 return physical_layer;
1860 }
1861
1862 /**
1863 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1864 * @hw: pointer to hardware structure
1865 * @regval: register value to write to RXCTRL
1866 *
1867 * Enables the Rx DMA unit for 82599
1868 **/
1869 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1870 {
1871 #define IXGBE_MAX_SECRX_POLL 30
1872 int i;
1873 int secrxreg;
1874
1875 /*
1876 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1877 * If traffic is incoming before we enable the Rx unit, it could hang
1878 * the Rx DMA unit. Therefore, make sure the security engine is
1879 * completely disabled prior to enabling the Rx unit.
1880 */
1881 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1882 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1883 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1884 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1885 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1886 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1887 break;
1888 else
1889 udelay(10);
1890 }
1891
1892 /* For informational purposes only */
1893 if (i >= IXGBE_MAX_SECRX_POLL)
1894 hw_dbg(hw, "Rx unit being enabled before security "
1895 "path fully disabled. Continuing with init.\n");
1896
1897 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1898 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1899 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1900 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1901 IXGBE_WRITE_FLUSH(hw);
1902
1903 return 0;
1904 }
1905
1906 /**
1907 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1908 * @hw: pointer to hardware structure
1909 * @device_caps: the EEPROM word with the extra device capabilities
1910 *
1911 * This function will read the EEPROM location for the device capabilities,
1912 * and return the word through device_caps.
1913 **/
1914 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1915 {
1916 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1917
1918 return 0;
1919 }
1920
1921 /**
1922 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1923 * @hw: pointer to hardware structure
1924 *
1925 * Verifies that installed the firmware version is 0.6 or higher
1926 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1927 *
1928 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1929 * if the FW version is not supported.
1930 **/
1931 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1932 {
1933 s32 status = IXGBE_ERR_EEPROM_VERSION;
1934 u16 fw_offset, fw_ptp_cfg_offset;
1935 u16 fw_version = 0;
1936
1937 /* firmware check is only necessary for SFI devices */
1938 if (hw->phy.media_type != ixgbe_media_type_fiber) {
1939 status = 0;
1940 goto fw_version_out;
1941 }
1942
1943 /* get the offset to the Firmware Module block */
1944 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1945
1946 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
1947 goto fw_version_out;
1948
1949 /* get the offset to the Pass Through Patch Configuration block */
1950 hw->eeprom.ops.read(hw, (fw_offset +
1951 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
1952 &fw_ptp_cfg_offset);
1953
1954 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
1955 goto fw_version_out;
1956
1957 /* get the firmware version */
1958 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
1959 IXGBE_FW_PATCH_VERSION_4),
1960 &fw_version);
1961
1962 if (fw_version > 0x5)
1963 status = 0;
1964
1965 fw_version_out:
1966 return status;
1967 }
1968
1969 static struct ixgbe_mac_operations mac_ops_82599 = {
1970 .init_hw = &ixgbe_init_hw_generic,
1971 .reset_hw = &ixgbe_reset_hw_82599,
1972 .start_hw = &ixgbe_start_hw_82599,
1973 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1974 .get_media_type = &ixgbe_get_media_type_82599,
1975 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1976 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1977 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1978 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
1979 .get_device_caps = &ixgbe_get_device_caps_82599,
1980 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
1981 .stop_adapter = &ixgbe_stop_adapter_generic,
1982 .get_bus_info = &ixgbe_get_bus_info_generic,
1983 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1984 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1985 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1986 .setup_link = &ixgbe_setup_mac_link_82599,
1987 .check_link = &ixgbe_check_mac_link_generic,
1988 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1989 .led_on = &ixgbe_led_on_generic,
1990 .led_off = &ixgbe_led_off_generic,
1991 .blink_led_start = &ixgbe_blink_led_start_generic,
1992 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1993 .set_rar = &ixgbe_set_rar_generic,
1994 .clear_rar = &ixgbe_clear_rar_generic,
1995 .set_vmdq = &ixgbe_set_vmdq_generic,
1996 .clear_vmdq = &ixgbe_clear_vmdq_generic,
1997 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1998 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1999 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2000 .enable_mc = &ixgbe_enable_mc_generic,
2001 .disable_mc = &ixgbe_disable_mc_generic,
2002 .clear_vfta = &ixgbe_clear_vfta_generic,
2003 .set_vfta = &ixgbe_set_vfta_generic,
2004 .fc_enable = &ixgbe_fc_enable_generic,
2005 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2006 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2007 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2008 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2009 };
2010
2011 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2012 .init_params = &ixgbe_init_eeprom_params_generic,
2013 .read = &ixgbe_read_eerd_generic,
2014 .write = &ixgbe_write_eeprom_generic,
2015 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2016 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2017 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2018 };
2019
2020 static struct ixgbe_phy_operations phy_ops_82599 = {
2021 .identify = &ixgbe_identify_phy_82599,
2022 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2023 .init = &ixgbe_init_phy_ops_82599,
2024 .reset = &ixgbe_reset_phy_generic,
2025 .read_reg = &ixgbe_read_phy_reg_generic,
2026 .write_reg = &ixgbe_write_phy_reg_generic,
2027 .setup_link = &ixgbe_setup_phy_link_generic,
2028 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2029 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2030 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2031 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2032 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2033 .check_overtemp = &ixgbe_tn_check_overtemp,
2034 };
2035
2036 struct ixgbe_info ixgbe_82599_info = {
2037 .mac = ixgbe_mac_82599EB,
2038 .get_invariants = &ixgbe_get_invariants_82599,
2039 .mac_ops = &mac_ops_82599,
2040 .eeprom_ops = &eeprom_ops_82599,
2041 .phy_ops = &phy_ops_82599,
2042 .mbx_ops = &mbx_ops_generic,
2043 };
linux-next