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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / qlcnic / qlcnic.h
blob44e316fd67b85917b6bb3af2abd48501507d3b5b
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32
33 #include "qlcnic_hdr.h"
34
35 #define _QLCNIC_LINUX_MAJOR 5
36 #define _QLCNIC_LINUX_MINOR 0
37 #define _QLCNIC_LINUX_SUBVERSION 15
38 #define QLCNIC_LINUX_VERSIONID "5.0.15"
39 #define QLCNIC_DRV_IDC_VER 0x01
40 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
41 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
42
43 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
44 #define _major(v) (((v) >> 24) & 0xff)
45 #define _minor(v) (((v) >> 16) & 0xff)
46 #define _build(v) ((v) & 0xffff)
47
48 /* version in image has weird encoding:
49 * 7:0 - major
50 * 15:8 - minor
51 * 31:16 - build (little endian)
52 */
53 #define QLCNIC_DECODE_VERSION(v) \
54 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
55
56 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
57 #define QLCNIC_NUM_FLASH_SECTORS (64)
58 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
59 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
60 * QLCNIC_FLASH_SECTOR_SIZE)
61
62 #define RCV_DESC_RINGSIZE(rds_ring) \
63 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
64 #define RCV_BUFF_RINGSIZE(rds_ring) \
65 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
66 #define STATUS_DESC_RINGSIZE(sds_ring) \
67 (sizeof(struct status_desc) * (sds_ring)->num_desc)
68 #define TX_BUFF_RINGSIZE(tx_ring) \
69 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
70 #define TX_DESC_RINGSIZE(tx_ring) \
71 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
72
73 #define QLCNIC_P3P_A0 0x50
74
75 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
76
77 #define FIRST_PAGE_GROUP_START 0
78 #define FIRST_PAGE_GROUP_END 0x100000
79
80 #define P3P_MAX_MTU (9600)
81 #define P3P_MIN_MTU (68)
82 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
83
84 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
85 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
86 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
87 #define QLCNIC_LRO_BUFFER_EXTRA 2048
88
89 /* Opcodes to be used with the commands */
90 #define TX_ETHER_PKT 0x01
91 #define TX_TCP_PKT 0x02
92 #define TX_UDP_PKT 0x03
93 #define TX_IP_PKT 0x04
94 #define TX_TCP_LSO 0x05
95 #define TX_TCP_LSO6 0x06
96 #define TX_IPSEC 0x07
97 #define TX_IPSEC_CMD 0x0a
98 #define TX_TCPV6_PKT 0x0b
99 #define TX_UDPV6_PKT 0x0c
100
101 /* Tx defines */
102 #define MAX_TSO_HEADER_DESC 2
103 #define MGMT_CMD_DESC_RESV 4
104 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
105 + MGMT_CMD_DESC_RESV)
106 #define QLCNIC_MAX_TX_TIMEOUTS 2
107
108 /*
109 * Following are the states of the Phantom. Phantom will set them and
110 * Host will read to check if the fields are correct.
111 */
112 #define PHAN_INITIALIZE_FAILED 0xffff
113 #define PHAN_INITIALIZE_COMPLETE 0xff01
114
115 /* Host writes the following to notify that it has done the init-handshake */
116 #define PHAN_INITIALIZE_ACK 0xf00f
117 #define PHAN_PEG_RCV_INITIALIZED 0xff01
118
119 #define NUM_RCV_DESC_RINGS 3
120 #define NUM_STS_DESC_RINGS 4
121
122 #define RCV_RING_NORMAL 0
123 #define RCV_RING_JUMBO 1
124
125 #define MIN_CMD_DESCRIPTORS 64
126 #define MIN_RCV_DESCRIPTORS 64
127 #define MIN_JUMBO_DESCRIPTORS 32
128
129 #define MAX_CMD_DESCRIPTORS 1024
130 #define MAX_RCV_DESCRIPTORS_1G 4096
131 #define MAX_RCV_DESCRIPTORS_10G 8192
132 #define MAX_RCV_DESCRIPTORS_VF 2048
133 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
134 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
135
136 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
137 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
138 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
139 #define MAX_RDS_RINGS 2
140
141 #define get_next_index(index, length) \
142 (((index) + 1) & ((length) - 1))
143
144 /*
145 * Following data structures describe the descriptors that will be used.
146 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
147 * we are doing LSO (above the 1500 size packet) only.
148 */
149
150 #define FLAGS_VLAN_TAGGED 0x10
151 #define FLAGS_VLAN_OOB 0x40
152
153 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
154 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
155 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
156 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
157 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
158 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
159
160 #define qlcnic_set_tx_port(_desc, _port) \
161 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
162
163 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
164 ((_desc)->flags_opcode |= \
165 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
166
167 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
168 ((_desc)->nfrags__length = \
169 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
170
171 struct cmd_desc_type0 {
172 u8 tcp_hdr_offset; /* For LSO only */
173 u8 ip_hdr_offset; /* For LSO only */
174 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
175 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
176
177 __le64 addr_buffer2;
178
179 __le16 reference_handle;
180 __le16 mss;
181 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
182 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
183 __le16 conn_id; /* IPSec offoad only */
184
185 __le64 addr_buffer3;
186 __le64 addr_buffer1;
187
188 __le16 buffer_length[4];
189
190 __le64 addr_buffer4;
191
192 u8 eth_addr[ETH_ALEN];
193 __le16 vlan_TCI;
194
195 } __attribute__ ((aligned(64)));
196
197 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
198 struct rcv_desc {
199 __le16 reference_handle;
200 __le16 reserved;
201 __le32 buffer_length; /* allocated buffer length (usually 2K) */
202 __le64 addr_buffer;
203 };
204
205 /* opcode field in status_desc */
206 #define QLCNIC_SYN_OFFLOAD 0x03
207 #define QLCNIC_RXPKT_DESC 0x04
208 #define QLCNIC_OLD_RXPKT_DESC 0x3f
209 #define QLCNIC_RESPONSE_DESC 0x05
210 #define QLCNIC_LRO_DESC 0x12
211
212 /* for status field in status_desc */
213 #define STATUS_CKSUM_LOOP 0
214 #define STATUS_CKSUM_OK 2
215
216 /* owner bits of status_desc */
217 #define STATUS_OWNER_HOST (0x1ULL << 56)
218 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
219
220 /* Status descriptor:
221 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
222 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
223 53-55 desc_cnt, 56-57 owner, 58-63 opcode
224 */
225 #define qlcnic_get_sts_port(sts_data) \
226 ((sts_data) & 0x0F)
227 #define qlcnic_get_sts_status(sts_data) \
228 (((sts_data) >> 4) & 0x0F)
229 #define qlcnic_get_sts_type(sts_data) \
230 (((sts_data) >> 8) & 0x0F)
231 #define qlcnic_get_sts_totallength(sts_data) \
232 (((sts_data) >> 12) & 0xFFFF)
233 #define qlcnic_get_sts_refhandle(sts_data) \
234 (((sts_data) >> 28) & 0xFFFF)
235 #define qlcnic_get_sts_prot(sts_data) \
236 (((sts_data) >> 44) & 0x0F)
237 #define qlcnic_get_sts_pkt_offset(sts_data) \
238 (((sts_data) >> 48) & 0x1F)
239 #define qlcnic_get_sts_desc_cnt(sts_data) \
240 (((sts_data) >> 53) & 0x7)
241 #define qlcnic_get_sts_opcode(sts_data) \
242 (((sts_data) >> 58) & 0x03F)
243
244 #define qlcnic_get_lro_sts_refhandle(sts_data) \
245 ((sts_data) & 0x0FFFF)
246 #define qlcnic_get_lro_sts_length(sts_data) \
247 (((sts_data) >> 16) & 0x0FFFF)
248 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
249 (((sts_data) >> 32) & 0x0FF)
250 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
251 (((sts_data) >> 40) & 0x0FF)
252 #define qlcnic_get_lro_sts_timestamp(sts_data) \
253 (((sts_data) >> 48) & 0x1)
254 #define qlcnic_get_lro_sts_type(sts_data) \
255 (((sts_data) >> 49) & 0x7)
256 #define qlcnic_get_lro_sts_push_flag(sts_data) \
257 (((sts_data) >> 52) & 0x1)
258 #define qlcnic_get_lro_sts_seq_number(sts_data) \
259 ((sts_data) & 0x0FFFFFFFF)
260
261
262 struct status_desc {
263 __le64 status_desc_data[2];
264 } __attribute__ ((aligned(16)));
265
266 /* UNIFIED ROMIMAGE */
267 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
268 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
269 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
270 #define QLCNIC_UNI_DIR_SECT_FW 0x7
271
272 /*Offsets */
273 #define QLCNIC_UNI_CHIP_REV_OFF 10
274 #define QLCNIC_UNI_FLAGS_OFF 11
275 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
276 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
277 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
278
279 struct uni_table_desc{
280 u32 findex;
281 u32 num_entries;
282 u32 entry_size;
283 u32 reserved[5];
284 };
285
286 struct uni_data_desc{
287 u32 findex;
288 u32 size;
289 u32 reserved[5];
290 };
291
292 /* Flash Defines and Structures */
293 #define QLCNIC_FLT_LOCATION 0x3F1000
294 #define QLCNIC_FW_IMAGE_REGION 0x74
295 struct qlcnic_flt_header {
296 u16 version;
297 u16 len;
298 u16 checksum;
299 u16 reserved;
300 };
301
302 struct qlcnic_flt_entry {
303 u8 region;
304 u8 reserved0;
305 u8 attrib;
306 u8 reserved1;
307 u32 size;
308 u32 start_addr;
309 u32 end_add;
310 };
311
312 /* Magic number to let user know flash is programmed */
313 #define QLCNIC_BDINFO_MAGIC 0x12345678
314
315 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
316 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
317 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
318 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
319 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
320 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
321 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
322 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
323 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
324 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
325 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
326 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
327 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
328 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
329
330 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
331
332 /* Flash memory map */
333 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
334 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
335 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
336 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
337
338 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
339 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
340 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
341 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
342
343 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
344 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
345
346 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
347 #define QLCNIC_UNIFIED_ROMIMAGE 0
348 #define QLCNIC_FLASH_ROMIMAGE 1
349 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
350
351 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
352 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
353
354 extern char qlcnic_driver_name[];
355
356 /* Number of status descriptors to handle per interrupt */
357 #define MAX_STATUS_HANDLE (64)
358
359 /*
360 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
361 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
362 */
363 struct qlcnic_skb_frag {
364 u64 dma;
365 u64 length;
366 };
367
368 struct qlcnic_recv_crb {
369 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
370 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
371 u32 sw_int_mask[NUM_STS_DESC_RINGS];
372 };
373
374 /* Following defines are for the state of the buffers */
375 #define QLCNIC_BUFFER_FREE 0
376 #define QLCNIC_BUFFER_BUSY 1
377
378 /*
379 * There will be one qlcnic_buffer per skb packet. These will be
380 * used to save the dma info for pci_unmap_page()
381 */
382 struct qlcnic_cmd_buffer {
383 struct sk_buff *skb;
384 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
385 u32 frag_count;
386 };
387
388 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
389 struct qlcnic_rx_buffer {
390 struct list_head list;
391 struct sk_buff *skb;
392 u64 dma;
393 u16 ref_handle;
394 };
395
396 /* Board types */
397 #define QLCNIC_GBE 0x01
398 #define QLCNIC_XGBE 0x02
399
400 /*
401 * One hardware_context{} per adapter
402 * contains interrupt info as well shared hardware info.
403 */
404 struct qlcnic_hardware_context {
405 void __iomem *pci_base0;
406 void __iomem *ocm_win_crb;
407
408 unsigned long pci_len0;
409
410 rwlock_t crb_lock;
411 struct mutex mem_lock;
412
413 u8 revision_id;
414 u8 pci_func;
415 u8 linkup;
416 u16 port_type;
417 u16 board_type;
418 };
419
420 struct qlcnic_adapter_stats {
421 u64 xmitcalled;
422 u64 xmitfinished;
423 u64 rxdropped;
424 u64 txdropped;
425 u64 csummed;
426 u64 rx_pkts;
427 u64 lro_pkts;
428 u64 rxbytes;
429 u64 txbytes;
430 u64 lrobytes;
431 u64 lso_frames;
432 u64 xmit_on;
433 u64 xmit_off;
434 u64 skb_alloc_failure;
435 u64 null_rxbuf;
436 u64 rx_dma_map_error;
437 u64 tx_dma_map_error;
438 };
439
440 /*
441 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
442 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
443 */
444 struct qlcnic_host_rds_ring {
445 u32 producer;
446 u32 num_desc;
447 u32 dma_size;
448 u32 skb_size;
449 u32 flags;
450 void __iomem *crb_rcv_producer;
451 struct rcv_desc *desc_head;
452 struct qlcnic_rx_buffer *rx_buf_arr;
453 struct list_head free_list;
454 spinlock_t lock;
455 dma_addr_t phys_addr;
456 };
457
458 struct qlcnic_host_sds_ring {
459 u32 consumer;
460 u32 num_desc;
461 void __iomem *crb_sts_consumer;
462 void __iomem *crb_intr_mask;
463
464 struct status_desc *desc_head;
465 struct qlcnic_adapter *adapter;
466 struct napi_struct napi;
467 struct list_head free_list[NUM_RCV_DESC_RINGS];
468
469 int irq;
470
471 dma_addr_t phys_addr;
472 char name[IFNAMSIZ+4];
473 };
474
475 struct qlcnic_host_tx_ring {
476 u32 producer;
477 __le32 *hw_consumer;
478 u32 sw_consumer;
479 void __iomem *crb_cmd_producer;
480 u32 num_desc;
481
482 struct netdev_queue *txq;
483
484 struct qlcnic_cmd_buffer *cmd_buf_arr;
485 struct cmd_desc_type0 *desc_head;
486 dma_addr_t phys_addr;
487 dma_addr_t hw_cons_phys_addr;
488 };
489
490 /*
491 * Receive context. There is one such structure per instance of the
492 * receive processing. Any state information that is relevant to
493 * the receive, and is must be in this structure. The global data may be
494 * present elsewhere.
495 */
496 struct qlcnic_recv_context {
497 u32 state;
498 u16 context_id;
499 u16 virt_port;
500
501 struct qlcnic_host_rds_ring *rds_rings;
502 struct qlcnic_host_sds_ring *sds_rings;
503 };
504
505 /* HW context creation */
506
507 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
508 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
509 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
510
511 #define QLCNIC_CDRP_CMD_BIT 0x80000000
512
513 /*
514 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
515 * in the crb QLCNIC_CDRP_CRB_OFFSET.
516 */
517 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
518 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
519
520 #define QLCNIC_CDRP_RSP_OK 0x00000001
521 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
522 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
523
524 /*
525 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
526 * the crb QLCNIC_CDRP_CRB_OFFSET.
527 */
528 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
529 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
530
531 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
532 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
533 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
534 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
535 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
536 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
537 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
538 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
539 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
540 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
541 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
542 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
543 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
544 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
545 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
546 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
547 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
548 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
549 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
550 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
551 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
552 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
553 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
554 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
555 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
556 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
557 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
558
559 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
560 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
561 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
562 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
563 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
564 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
565 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
566 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
567 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
568 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
569 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
570
571 #define QLCNIC_RCODE_SUCCESS 0
572 #define QLCNIC_RCODE_TIMEOUT 17
573 #define QLCNIC_DESTROY_CTX_RESET 0
574
575 /*
576 * Capabilities Announced
577 */
578 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
579 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
580 #define QLCNIC_CAP0_LSO (1 << 6)
581 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
582 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
583 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
584
585 /*
586 * Context state
587 */
588 #define QLCNIC_HOST_CTX_STATE_FREED 0
589 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
590
591 /*
592 * Rx context
593 */
594
595 struct qlcnic_hostrq_sds_ring {
596 __le64 host_phys_addr; /* Ring base addr */
597 __le32 ring_size; /* Ring entries */
598 __le16 msi_index;
599 __le16 rsvd; /* Padding */
600 };
601
602 struct qlcnic_hostrq_rds_ring {
603 __le64 host_phys_addr; /* Ring base addr */
604 __le64 buff_size; /* Packet buffer size */
605 __le32 ring_size; /* Ring entries */
606 __le32 ring_kind; /* Class of ring */
607 };
608
609 struct qlcnic_hostrq_rx_ctx {
610 __le64 host_rsp_dma_addr; /* Response dma'd here */
611 __le32 capabilities[4]; /* Flag bit vector */
612 __le32 host_int_crb_mode; /* Interrupt crb usage */
613 __le32 host_rds_crb_mode; /* RDS crb usage */
614 /* These ring offsets are relative to data[0] below */
615 __le32 rds_ring_offset; /* Offset to RDS config */
616 __le32 sds_ring_offset; /* Offset to SDS config */
617 __le16 num_rds_rings; /* Count of RDS rings */
618 __le16 num_sds_rings; /* Count of SDS rings */
619 __le16 valid_field_offset;
620 u8 txrx_sds_binding;
621 u8 msix_handler;
622 u8 reserved[128]; /* reserve space for future expansion*/
623 /* MUST BE 64-bit aligned.
624 The following is packed:
625 - N hostrq_rds_rings
626 - N hostrq_sds_rings */
627 char data[0];
628 };
629
630 struct qlcnic_cardrsp_rds_ring{
631 __le32 host_producer_crb; /* Crb to use */
632 __le32 rsvd1; /* Padding */
633 };
634
635 struct qlcnic_cardrsp_sds_ring {
636 __le32 host_consumer_crb; /* Crb to use */
637 __le32 interrupt_crb; /* Crb to use */
638 };
639
640 struct qlcnic_cardrsp_rx_ctx {
641 /* These ring offsets are relative to data[0] below */
642 __le32 rds_ring_offset; /* Offset to RDS config */
643 __le32 sds_ring_offset; /* Offset to SDS config */
644 __le32 host_ctx_state; /* Starting State */
645 __le32 num_fn_per_port; /* How many PCI fn share the port */
646 __le16 num_rds_rings; /* Count of RDS rings */
647 __le16 num_sds_rings; /* Count of SDS rings */
648 __le16 context_id; /* Handle for context */
649 u8 phys_port; /* Physical id of port */
650 u8 virt_port; /* Virtual/Logical id of port */
651 u8 reserved[128]; /* save space for future expansion */
652 /* MUST BE 64-bit aligned.
653 The following is packed:
654 - N cardrsp_rds_rings
655 - N cardrs_sds_rings */
656 char data[0];
657 };
658
659 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
660 (sizeof(HOSTRQ_RX) + \
661 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
662 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
663
664 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
665 (sizeof(CARDRSP_RX) + \
666 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
667 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
668
669 /*
670 * Tx context
671 */
672
673 struct qlcnic_hostrq_cds_ring {
674 __le64 host_phys_addr; /* Ring base addr */
675 __le32 ring_size; /* Ring entries */
676 __le32 rsvd; /* Padding */
677 };
678
679 struct qlcnic_hostrq_tx_ctx {
680 __le64 host_rsp_dma_addr; /* Response dma'd here */
681 __le64 cmd_cons_dma_addr; /* */
682 __le64 dummy_dma_addr; /* */
683 __le32 capabilities[4]; /* Flag bit vector */
684 __le32 host_int_crb_mode; /* Interrupt crb usage */
685 __le32 rsvd1; /* Padding */
686 __le16 rsvd2; /* Padding */
687 __le16 interrupt_ctl;
688 __le16 msi_index;
689 __le16 rsvd3; /* Padding */
690 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
691 u8 reserved[128]; /* future expansion */
692 };
693
694 struct qlcnic_cardrsp_cds_ring {
695 __le32 host_producer_crb; /* Crb to use */
696 __le32 interrupt_crb; /* Crb to use */
697 };
698
699 struct qlcnic_cardrsp_tx_ctx {
700 __le32 host_ctx_state; /* Starting state */
701 __le16 context_id; /* Handle for context */
702 u8 phys_port; /* Physical id of port */
703 u8 virt_port; /* Virtual/Logical id of port */
704 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
705 u8 reserved[128]; /* future expansion */
706 };
707
708 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
709 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
710
711 /* CRB */
712
713 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
714 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
715 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
716 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
717
718 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
719 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
720 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
721 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
722 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
723
724
725 /* MAC */
726
727 #define MC_COUNT_P3P 38
728
729 #define QLCNIC_MAC_NOOP 0
730 #define QLCNIC_MAC_ADD 1
731 #define QLCNIC_MAC_DEL 2
732 #define QLCNIC_MAC_VLAN_ADD 3
733 #define QLCNIC_MAC_VLAN_DEL 4
734
735 struct qlcnic_mac_list_s {
736 struct list_head list;
737 uint8_t mac_addr[ETH_ALEN+2];
738 };
739
740 /*
741 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
742 * adjusted based on configured MTU.
743 */
744 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
745 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
746 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
747 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
748
749 #define QLCNIC_INTR_DEFAULT 0x04
750
751 union qlcnic_nic_intr_coalesce_data {
752 struct {
753 u16 rx_packets;
754 u16 rx_time_us;
755 u16 tx_packets;
756 u16 tx_time_us;
757 } data;
758 u64 word;
759 };
760
761 struct qlcnic_nic_intr_coalesce {
762 u16 stats_time_us;
763 u16 rate_sample_time;
764 u16 flags;
765 u16 rsvd_1;
766 u32 low_threshold;
767 u32 high_threshold;
768 union qlcnic_nic_intr_coalesce_data normal;
769 union qlcnic_nic_intr_coalesce_data low;
770 union qlcnic_nic_intr_coalesce_data high;
771 union qlcnic_nic_intr_coalesce_data irq;
772 };
773
774 #define QLCNIC_HOST_REQUEST 0x13
775 #define QLCNIC_REQUEST 0x14
776
777 #define QLCNIC_MAC_EVENT 0x1
778
779 #define QLCNIC_IP_UP 2
780 #define QLCNIC_IP_DOWN 3
781
782 /*
783 * Driver --> Firmware
784 */
785 #define QLCNIC_H2C_OPCODE_START 0
786 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
787 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
788 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
789 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
790 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
791 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
792 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
793 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
794 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
795 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
796 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
797 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
798 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
799 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
800 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
801 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
802 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
803 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
804 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
805 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
806 #define QLCNIC_C2C_OPCODE 22
807 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
808 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
809 #define QLCNIC_H2C_OPCODE_LAST 25
810 /*
811 * Firmware --> Driver
812 */
813
814 #define QLCNIC_C2H_OPCODE_START 128
815 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
816 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
817 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
818 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
819 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
820 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
821 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
822 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
823 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
824 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
825 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
826 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
827 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
828 #define QLCNIC_C2H_OPCODE_LAST 142
829
830 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
831 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
832 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
833
834 #define QLCNIC_LRO_REQUEST_CLEANUP 4
835
836 /* Capabilites received */
837 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
838 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
839 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
840 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
841
842 /* module types */
843 #define LINKEVENT_MODULE_NOT_PRESENT 1
844 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
845 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
846 #define LINKEVENT_MODULE_OPTICAL_LRM 4
847 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
848 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
849 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
850 #define LINKEVENT_MODULE_TWINAX 8
851
852 #define LINKSPEED_10GBPS 10000
853 #define LINKSPEED_1GBPS 1000
854 #define LINKSPEED_100MBPS 100
855 #define LINKSPEED_10MBPS 10
856
857 #define LINKSPEED_ENCODED_10MBPS 0
858 #define LINKSPEED_ENCODED_100MBPS 1
859 #define LINKSPEED_ENCODED_1GBPS 2
860
861 #define LINKEVENT_AUTONEG_DISABLED 0
862 #define LINKEVENT_AUTONEG_ENABLED 1
863
864 #define LINKEVENT_HALF_DUPLEX 0
865 #define LINKEVENT_FULL_DUPLEX 1
866
867 #define LINKEVENT_LINKSPEED_MBPS 0
868 #define LINKEVENT_LINKSPEED_ENCODED 1
869
870 #define AUTO_FW_RESET_ENABLED 0x01
871 /* firmware response header:
872 * 63:58 - message type
873 * 57:56 - owner
874 * 55:53 - desc count
875 * 52:48 - reserved
876 * 47:40 - completion id
877 * 39:32 - opcode
878 * 31:16 - error code
879 * 15:00 - reserved
880 */
881 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
882 ((msg_hdr >> 32) & 0xFF)
883
884 struct qlcnic_fw_msg {
885 union {
886 struct {
887 u64 hdr;
888 u64 body[7];
889 };
890 u64 words[8];
891 };
892 };
893
894 struct qlcnic_nic_req {
895 __le64 qhdr;
896 __le64 req_hdr;
897 __le64 words[6];
898 };
899
900 struct qlcnic_mac_req {
901 u8 op;
902 u8 tag;
903 u8 mac_addr[6];
904 };
905
906 struct qlcnic_vlan_req {
907 __le16 vlan_id;
908 __le16 rsvd[3];
909 };
910
911 struct qlcnic_ipaddr {
912 __be32 ipv4;
913 __be32 ipv6[4];
914 };
915
916 #define QLCNIC_MSI_ENABLED 0x02
917 #define QLCNIC_MSIX_ENABLED 0x04
918 #define QLCNIC_LRO_ENABLED 0x08
919 #define QLCNIC_LRO_DISABLED 0x00
920 #define QLCNIC_BRIDGE_ENABLED 0X10
921 #define QLCNIC_DIAG_ENABLED 0x20
922 #define QLCNIC_ESWITCH_ENABLED 0x40
923 #define QLCNIC_ADAPTER_INITIALIZED 0x80
924 #define QLCNIC_TAGGING_ENABLED 0x100
925 #define QLCNIC_MACSPOOF 0x200
926 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
927 #define QLCNIC_PROMISC_DISABLED 0x800
928 #define QLCNIC_NEED_FLR 0x1000
929 #define QLCNIC_IS_MSI_FAMILY(adapter) \
930 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
931
932 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
933 #define QLCNIC_MSIX_TBL_SPACE 8192
934 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
935 #define QLCNIC_MSIX_TBL_PGSIZE 4096
936
937 #define QLCNIC_NETDEV_WEIGHT 128
938 #define QLCNIC_ADAPTER_UP_MAGIC 777
939
940 #define __QLCNIC_FW_ATTACHED 0
941 #define __QLCNIC_DEV_UP 1
942 #define __QLCNIC_RESETTING 2
943 #define __QLCNIC_START_FW 4
944 #define __QLCNIC_AER 5
945
946 #define QLCNIC_INTERRUPT_TEST 1
947 #define QLCNIC_LOOPBACK_TEST 2
948 #define QLCNIC_LED_TEST 3
949
950 #define QLCNIC_FILTER_AGE 80
951 #define QLCNIC_READD_AGE 20
952 #define QLCNIC_LB_MAX_FILTERS 64
953
954 struct qlcnic_filter {
955 struct hlist_node fnode;
956 u8 faddr[ETH_ALEN];
957 __le16 vlan_id;
958 unsigned long ftime;
959 };
960
961 struct qlcnic_filter_hash {
962 struct hlist_head *fhead;
963 u8 fnum;
964 u8 fmax;
965 };
966
967 struct qlcnic_adapter {
968 struct qlcnic_hardware_context ahw;
969
970 struct net_device *netdev;
971 struct pci_dev *pdev;
972 struct list_head mac_list;
973
974 spinlock_t tx_clean_lock;
975 spinlock_t mac_learn_lock;
976
977 u16 num_txd;
978 u16 num_rxd;
979 u16 num_jumbo_rxd;
980 u16 max_rxd;
981 u16 max_jumbo_rxd;
982
983 u8 max_rds_rings;
984 u8 max_sds_rings;
985 u8 msix_supported;
986 u8 rx_csum;
987 u8 portnum;
988 u8 physical_port;
989 u8 reset_context;
990
991 u8 mc_enabled;
992 u8 max_mc_count;
993 u8 rss_supported;
994 u8 fw_wait_cnt;
995 u8 fw_fail_cnt;
996 u8 tx_timeo_cnt;
997 u8 need_fw_reset;
998
999 u8 has_link_events;
1000 u8 fw_type;
1001 u16 tx_context_id;
1002 u16 is_up;
1003
1004 u16 link_speed;
1005 u16 link_duplex;
1006 u16 link_autoneg;
1007 u16 module_type;
1008
1009 u16 op_mode;
1010 u16 switch_mode;
1011 u16 max_tx_ques;
1012 u16 max_rx_ques;
1013 u16 max_mtu;
1014 u16 pvid;
1015
1016 u32 fw_hal_version;
1017 u32 capabilities;
1018 u32 flags;
1019 u32 irq;
1020 u32 temp;
1021
1022 u32 int_vec_bit;
1023 u32 heartbeat;
1024
1025 u8 max_mac_filters;
1026 u8 dev_state;
1027 u8 diag_test;
1028 u8 diag_cnt;
1029 u8 reset_ack_timeo;
1030 u8 dev_init_timeo;
1031 u16 msg_enable;
1032
1033 u8 mac_addr[ETH_ALEN];
1034
1035 u64 dev_rst_time;
1036
1037 struct vlan_group *vlgrp;
1038 struct qlcnic_npar_info *npars;
1039 struct qlcnic_eswitch *eswitch;
1040 struct qlcnic_nic_template *nic_ops;
1041
1042 struct qlcnic_adapter_stats stats;
1043
1044 struct qlcnic_recv_context recv_ctx;
1045 struct qlcnic_host_tx_ring *tx_ring;
1046
1047 void __iomem *tgt_mask_reg;
1048 void __iomem *tgt_status_reg;
1049 void __iomem *crb_int_state_reg;
1050 void __iomem *isr_int_vec;
1051
1052 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1053
1054 struct delayed_work fw_work;
1055
1056 struct qlcnic_nic_intr_coalesce coal;
1057
1058 struct qlcnic_filter_hash fhash;
1059
1060 unsigned long state;
1061 __le32 file_prd_off; /*File fw product offset*/
1062 u32 fw_version;
1063 const struct firmware *fw;
1064 };
1065
1066 struct qlcnic_info {
1067 __le16 pci_func;
1068 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1069 __le16 phys_port;
1070 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1071
1072 __le32 capabilities;
1073 u8 max_mac_filters;
1074 u8 reserved1;
1075 __le16 max_mtu;
1076
1077 __le16 max_tx_ques;
1078 __le16 max_rx_ques;
1079 __le16 min_tx_bw;
1080 __le16 max_tx_bw;
1081 u8 reserved2[104];
1082 };
1083
1084 struct qlcnic_pci_info {
1085 __le16 id; /* pci function id */
1086 __le16 active; /* 1 = Enabled */
1087 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1088 __le16 default_port; /* default port number */
1089
1090 __le16 tx_min_bw; /* Multiple of 100mbpc */
1091 __le16 tx_max_bw;
1092 __le16 reserved1[2];
1093
1094 u8 mac[ETH_ALEN];
1095 u8 reserved2[106];
1096 };
1097
1098 struct qlcnic_npar_info {
1099 u16 pvid;
1100 u16 min_bw;
1101 u16 max_bw;
1102 u8 phy_port;
1103 u8 type;
1104 u8 active;
1105 u8 enable_pm;
1106 u8 dest_npar;
1107 u8 discard_tagged;
1108 u8 mac_override;
1109 u8 mac_anti_spoof;
1110 u8 promisc_mode;
1111 u8 offload_flags;
1112 };
1113
1114 struct qlcnic_eswitch {
1115 u8 port;
1116 u8 active_vports;
1117 u8 active_vlans;
1118 u8 active_ucast_filters;
1119 u8 max_ucast_filters;
1120 u8 max_active_vlans;
1121
1122 u32 flags;
1123 #define QLCNIC_SWITCH_ENABLE BIT_1
1124 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1125 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1126 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1127 };
1128
1129
1130 /* Return codes for Error handling */
1131 #define QL_STATUS_INVALID_PARAM -1
1132
1133 #define MAX_BW 100 /* % of link speed */
1134 #define MAX_VLAN_ID 4095
1135 #define MIN_VLAN_ID 2
1136 #define MAX_TX_QUEUES 1
1137 #define MAX_RX_QUEUES 4
1138 #define DEFAULT_MAC_LEARN 1
1139
1140 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1141 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1142 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
1143 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
1144
1145 struct qlcnic_pci_func_cfg {
1146 u16 func_type;
1147 u16 min_bw;
1148 u16 max_bw;
1149 u16 port_num;
1150 u8 pci_func;
1151 u8 func_state;
1152 u8 def_mac_addr[6];
1153 };
1154
1155 struct qlcnic_npar_func_cfg {
1156 u32 fw_capab;
1157 u16 port_num;
1158 u16 min_bw;
1159 u16 max_bw;
1160 u16 max_tx_queues;
1161 u16 max_rx_queues;
1162 u8 pci_func;
1163 u8 op_mode;
1164 };
1165
1166 struct qlcnic_pm_func_cfg {
1167 u8 pci_func;
1168 u8 action;
1169 u8 dest_npar;
1170 u8 reserved[5];
1171 };
1172
1173 struct qlcnic_esw_func_cfg {
1174 u16 vlan_id;
1175 u8 op_mode;
1176 u8 op_type;
1177 u8 pci_func;
1178 u8 host_vlan_tag;
1179 u8 promisc_mode;
1180 u8 discard_tagged;
1181 u8 mac_override;
1182 u8 mac_anti_spoof;
1183 u8 offload_flags;
1184 u8 reserved[5];
1185 };
1186
1187 #define QLCNIC_STATS_VERSION 1
1188 #define QLCNIC_STATS_PORT 1
1189 #define QLCNIC_STATS_ESWITCH 2
1190 #define QLCNIC_QUERY_RX_COUNTER 0
1191 #define QLCNIC_QUERY_TX_COUNTER 1
1192 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1193
1194 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1195 do { \
1196 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1197 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1198 (VAL1) = (VAL2); \
1199 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1200 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1201 (VAL1) += (VAL2); \
1202 } while (0)
1203
1204 struct __qlcnic_esw_statistics {
1205 __le16 context_id;
1206 __le16 version;
1207 __le16 size;
1208 __le16 unused;
1209 __le64 unicast_frames;
1210 __le64 multicast_frames;
1211 __le64 broadcast_frames;
1212 __le64 dropped_frames;
1213 __le64 errors;
1214 __le64 local_frames;
1215 __le64 numbytes;
1216 __le64 rsvd[3];
1217 };
1218
1219 struct qlcnic_esw_statistics {
1220 struct __qlcnic_esw_statistics rx;
1221 struct __qlcnic_esw_statistics tx;
1222 };
1223
1224 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1225 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1226
1227 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1228 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1229 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1230 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1231 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1232 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1233
1234 #define ADDR_IN_RANGE(addr, low, high) \
1235 (((addr) < (high)) && ((addr) >= (low)))
1236
1237 #define QLCRD32(adapter, off) \
1238 (qlcnic_hw_read_wx_2M(adapter, off))
1239 #define QLCWR32(adapter, off, val) \
1240 (qlcnic_hw_write_wx_2M(adapter, off, val))
1241
1242 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1243 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1244
1245 #define qlcnic_rom_lock(a) \
1246 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1247 #define qlcnic_rom_unlock(a) \
1248 qlcnic_pcie_sem_unlock((a), 2)
1249 #define qlcnic_phy_lock(a) \
1250 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1251 #define qlcnic_phy_unlock(a) \
1252 qlcnic_pcie_sem_unlock((a), 3)
1253 #define qlcnic_api_lock(a) \
1254 qlcnic_pcie_sem_lock((a), 5, 0)
1255 #define qlcnic_api_unlock(a) \
1256 qlcnic_pcie_sem_unlock((a), 5)
1257 #define qlcnic_sw_lock(a) \
1258 qlcnic_pcie_sem_lock((a), 6, 0)
1259 #define qlcnic_sw_unlock(a) \
1260 qlcnic_pcie_sem_unlock((a), 6)
1261 #define crb_win_lock(a) \
1262 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1263 #define crb_win_unlock(a) \
1264 qlcnic_pcie_sem_unlock((a), 7)
1265
1266 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1267 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1268 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1269 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1270 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1271
1272 /* Functions from qlcnic_init.c */
1273 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1274 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1275 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1276 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1277 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1278 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1279 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1280
1281 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1282 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1283 u8 *bytes, size_t size);
1284 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1285 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1286
1287 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1288
1289 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1290 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1291
1292 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1293 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1294
1295 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1296 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1297 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1298
1299 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1300 void qlcnic_watchdog_task(struct work_struct *work);
1301 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1302 struct qlcnic_host_rds_ring *rds_ring);
1303 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1304 void qlcnic_set_multi(struct net_device *netdev);
1305 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1306 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1307 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1308 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1309 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1310 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1311 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1312
1313 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1314 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1315 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1316 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1317 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1318 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1319 struct qlcnic_host_tx_ring *tx_ring);
1320 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1321
1322 /* Functions from qlcnic_main.c */
1323 int qlcnic_reset_context(struct qlcnic_adapter *);
1324 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1325 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1326 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1327 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1328 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1329
1330 /* Management functions */
1331 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1332 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1333 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1334 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1335
1336 /* eSwitch management functions */
1337 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1338 struct qlcnic_esw_func_cfg *);
1339 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1340 struct qlcnic_esw_func_cfg *);
1341 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1342 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1343 struct __qlcnic_esw_statistics *);
1344 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1345 struct __qlcnic_esw_statistics *);
1346 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1347 extern int qlcnic_config_tso;
1348
1349 /*
1350 * QLOGIC Board information
1351 */
1352
1353 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1354 struct qlcnic_brdinfo {
1355 unsigned short vendor;
1356 unsigned short device;
1357 unsigned short sub_vendor;
1358 unsigned short sub_device;
1359 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1360 };
1361
1362 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1363 {0x1077, 0x8020, 0x1077, 0x203,
1364 "8200 Series Single Port 10GbE Converged Network Adapter "
1365 "(TCP/IP Networking)"},
1366 {0x1077, 0x8020, 0x1077, 0x207,
1367 "8200 Series Dual Port 10GbE Converged Network Adapter "
1368 "(TCP/IP Networking)"},
1369 {0x1077, 0x8020, 0x1077, 0x20b,
1370 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1371 {0x1077, 0x8020, 0x1077, 0x20c,
1372 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1373 {0x1077, 0x8020, 0x1077, 0x20f,
1374 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1375 {0x1077, 0x8020, 0x103c, 0x3733,
1376 "NC523SFP 10Gb 2-port Server Adapter"},
1377 {0x1077, 0x8020, 0x103c, 0x3346,
1378 "CN1000Q Dual Port Converged Network Adapter"},
1379 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1380 };
1381
1382 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1383
1384 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1385 {
1386 smp_mb();
1387 if (tx_ring->producer < tx_ring->sw_consumer)
1388 return tx_ring->sw_consumer - tx_ring->producer;
1389 else
1390 return tx_ring->sw_consumer + tx_ring->num_desc -
1391 tx_ring->producer;
1392 }
1393
1394 extern const struct ethtool_ops qlcnic_ethtool_ops;
1395
1396 struct qlcnic_nic_template {
1397 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1398 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1399 int (*start_firmware) (struct qlcnic_adapter *);
1400 };
1401
1402 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1403 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1404 printk(KERN_INFO "%s: %s: " _fmt, \
1405 dev_name(&adapter->pdev->dev), \
1406 __func__, ##_args); \
1407 } while (0)
1408
1409 #endif /* __QLCNIC_H_ */
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