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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / typhoon.c
bloba3c46f6a15e7c5b02a91542406208928cdb23a6d
1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2 /*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
28 issue. Hopefully 3Com will fix it.
29 *) Waiting for a command response takes 8ms due to non-preemptable
30 polling. Only significant for getting stats and creating
31 SAs, but an ugly wart never the less.
32
33 TODO:
34 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
35 *) Add more support for ethtool (especially for NIC stats)
36 *) Allow disabling of RX checksum offloading
37 *) Fix MAC changing to work while the interface is up
38 (Need to put commands on the TX ring, which changes
39 the locking)
40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
42 */
43
44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 * Setting to > 1518 effectively disables this feature.
46 */
47 static int rx_copybreak = 200;
48
49 /* Should we use MMIO or Port IO?
50 * 0: Port IO
51 * 1: MMIO
52 * 2: Try MMIO, fallback to Port IO
53 */
54 static unsigned int use_mmio = 2;
55
56 /* end user-configurable values */
57
58 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
59 */
60 static const int multicast_filter_limit = 32;
61
62 /* Operational parameters that are set at compile time. */
63
64 /* Keep the ring sizes a power of two for compile efficiency.
65 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
66 * Making the Tx ring too large decreases the effectiveness of channel
67 * bonding and packet priority.
68 * There are no ill effects from too-large receive rings.
69 *
70 * We don't currently use the Hi Tx ring so, don't make it very big.
71 *
72 * Beware that if we start using the Hi Tx ring, we will need to change
73 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
74 */
75 #define TXHI_ENTRIES 2
76 #define TXLO_ENTRIES 128
77 #define RX_ENTRIES 32
78 #define COMMAND_ENTRIES 16
79 #define RESPONSE_ENTRIES 32
80
81 #define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
82 #define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
83
84 /* The 3XP will preload and remove 64 entries from the free buffer
85 * list, and we need one entry to keep the ring from wrapping, so
86 * to keep this a power of two, we use 128 entries.
87 */
88 #define RXFREE_ENTRIES 128
89 #define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
90
91 /* Operational parameters that usually are not changed. */
92
93 /* Time in jiffies before concluding the transmitter is hung. */
94 #define TX_TIMEOUT (2*HZ)
95
96 #define PKT_BUF_SZ 1536
97 #define FIRMWARE_NAME "3com/typhoon.bin"
98
99 #define pr_fmt(fmt) KBUILD_MODNAME " " fmt
100
101 #include <linux/module.h>
102 #include <linux/kernel.h>
103 #include <linux/sched.h>
104 #include <linux/string.h>
105 #include <linux/timer.h>
106 #include <linux/errno.h>
107 #include <linux/ioport.h>
108 #include <linux/interrupt.h>
109 #include <linux/pci.h>
110 #include <linux/netdevice.h>
111 #include <linux/etherdevice.h>
112 #include <linux/skbuff.h>
113 #include <linux/mm.h>
114 #include <linux/init.h>
115 #include <linux/delay.h>
116 #include <linux/ethtool.h>
117 #include <linux/if_vlan.h>
118 #include <linux/crc32.h>
119 #include <linux/bitops.h>
120 #include <asm/processor.h>
121 #include <asm/io.h>
122 #include <asm/uaccess.h>
123 #include <linux/in6.h>
124 #include <linux/dma-mapping.h>
125 #include <linux/firmware.h>
126 #include <generated/utsrelease.h>
127
128 #include "typhoon.h"
129
130 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
131 MODULE_VERSION(UTS_RELEASE);
132 MODULE_LICENSE("GPL");
133 MODULE_FIRMWARE(FIRMWARE_NAME);
134 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
135 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
136 "the buffer given back to the NIC. Default "
137 "is 200.");
138 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
139 "Default is to try MMIO and fallback to PIO.");
140 module_param(rx_copybreak, int, 0);
141 module_param(use_mmio, int, 0);
142
143 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
144 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
145 #undef NETIF_F_TSO
146 #endif
147
148 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
149 #error TX ring too small!
150 #endif
151
152 struct typhoon_card_info {
153 const char *name;
154 const int capabilities;
155 };
156
157 #define TYPHOON_CRYPTO_NONE 0x00
158 #define TYPHOON_CRYPTO_DES 0x01
159 #define TYPHOON_CRYPTO_3DES 0x02
160 #define TYPHOON_CRYPTO_VARIABLE 0x04
161 #define TYPHOON_FIBER 0x08
162 #define TYPHOON_WAKEUP_NEEDS_RESET 0x10
163
164 enum typhoon_cards {
165 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
166 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
167 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
168 TYPHOON_FXM,
169 };
170
171 /* directly indexed by enum typhoon_cards, above */
172 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
173 { "3Com Typhoon (3C990-TX)",
174 TYPHOON_CRYPTO_NONE},
175 { "3Com Typhoon (3CR990-TX-95)",
176 TYPHOON_CRYPTO_DES},
177 { "3Com Typhoon (3CR990-TX-97)",
178 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
179 { "3Com Typhoon (3C990SVR)",
180 TYPHOON_CRYPTO_NONE},
181 { "3Com Typhoon (3CR990SVR95)",
182 TYPHOON_CRYPTO_DES},
183 { "3Com Typhoon (3CR990SVR97)",
184 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
185 { "3Com Typhoon2 (3C990B-TX-M)",
186 TYPHOON_CRYPTO_VARIABLE},
187 { "3Com Typhoon2 (3C990BSVR)",
188 TYPHOON_CRYPTO_VARIABLE},
189 { "3Com Typhoon (3CR990-FX-95)",
190 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
191 { "3Com Typhoon (3CR990-FX-97)",
192 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
193 { "3Com Typhoon (3CR990-FX-95 Server)",
194 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
195 { "3Com Typhoon (3CR990-FX-97 Server)",
196 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
197 { "3Com Typhoon2 (3C990B-FX-97)",
198 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
199 };
200
201 /* Notes on the new subsystem numbering scheme:
202 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
203 * bit 4 indicates if this card has secured firmware (we don't support it)
204 * bit 8 indicates if this is a (0) copper or (1) fiber card
205 * bits 12-16 indicate card type: (0) client and (1) server
206 */
207 static DEFINE_PCI_DEVICE_TABLE(typhoon_pci_tbl) = {
208 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
210 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
212 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
214 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
215 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
216 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
217 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
218 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
219 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
220 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
221 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
222 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
223 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
224 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
225 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
226 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
227 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
228 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
230 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
232 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
234 { 0, }
235 };
236 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
237
238 /* Define the shared memory area
239 * Align everything the 3XP will normally be using.
240 * We'll need to move/align txHi if we start using that ring.
241 */
242 #define __3xp_aligned ____cacheline_aligned
243 struct typhoon_shared {
244 struct typhoon_interface iface;
245 struct typhoon_indexes indexes __3xp_aligned;
246 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
247 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
248 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
249 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
250 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
251 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
252 u32 zeroWord;
253 struct tx_desc txHi[TXHI_ENTRIES];
254 } __packed;
255
256 struct rxbuff_ent {
257 struct sk_buff *skb;
258 dma_addr_t dma_addr;
259 };
260
261 struct typhoon {
262 /* Tx cache line section */
263 struct transmit_ring txLoRing ____cacheline_aligned;
264 struct pci_dev * tx_pdev;
265 void __iomem *tx_ioaddr;
266 u32 txlo_dma_addr;
267
268 /* Irq/Rx cache line section */
269 void __iomem *ioaddr ____cacheline_aligned;
270 struct typhoon_indexes *indexes;
271 u8 awaiting_resp;
272 u8 duplex;
273 u8 speed;
274 u8 card_state;
275 struct basic_ring rxLoRing;
276 struct pci_dev * pdev;
277 struct net_device * dev;
278 struct napi_struct napi;
279 struct basic_ring rxHiRing;
280 struct basic_ring rxBuffRing;
281 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
282
283 /* general section */
284 spinlock_t command_lock ____cacheline_aligned;
285 struct basic_ring cmdRing;
286 struct basic_ring respRing;
287 struct net_device_stats stats;
288 struct net_device_stats stats_saved;
289 struct typhoon_shared * shared;
290 dma_addr_t shared_dma;
291 __le16 xcvr_select;
292 __le16 wol_events;
293 __le32 offload;
294
295 /* unused stuff (future use) */
296 int capabilities;
297 struct transmit_ring txHiRing;
298 };
299
300 enum completion_wait_values {
301 NoWait = 0, WaitNoSleep, WaitSleep,
302 };
303
304 /* These are the values for the typhoon.card_state variable.
305 * These determine where the statistics will come from in get_stats().
306 * The sleep image does not support the statistics we need.
307 */
308 enum state_values {
309 Sleeping = 0, Running,
310 };
311
312 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
313 * cannot pass a read, so this forces current writes to post.
314 */
315 #define typhoon_post_pci_writes(x) \
316 do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
317
318 /* We'll wait up to six seconds for a reset, and half a second normally.
319 */
320 #define TYPHOON_UDELAY 50
321 #define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
322 #define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
323 #define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
324
325 #if defined(NETIF_F_TSO)
326 #define skb_tso_size(x) (skb_shinfo(x)->gso_size)
327 #define TSO_NUM_DESCRIPTORS 2
328 #define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
329 #else
330 #define NETIF_F_TSO 0
331 #define skb_tso_size(x) 0
332 #define TSO_NUM_DESCRIPTORS 0
333 #define TSO_OFFLOAD_ON 0
334 #endif
335
336 static inline void
337 typhoon_inc_index(u32 *index, const int count, const int num_entries)
338 {
339 /* Increment a ring index -- we can use this for all rings execept
340 * the Rx rings, as they use different size descriptors
341 * otherwise, everything is the same size as a cmd_desc
342 */
343 *index += count * sizeof(struct cmd_desc);
344 *index %= num_entries * sizeof(struct cmd_desc);
345 }
346
347 static inline void
348 typhoon_inc_cmd_index(u32 *index, const int count)
349 {
350 typhoon_inc_index(index, count, COMMAND_ENTRIES);
351 }
352
353 static inline void
354 typhoon_inc_resp_index(u32 *index, const int count)
355 {
356 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
357 }
358
359 static inline void
360 typhoon_inc_rxfree_index(u32 *index, const int count)
361 {
362 typhoon_inc_index(index, count, RXFREE_ENTRIES);
363 }
364
365 static inline void
366 typhoon_inc_tx_index(u32 *index, const int count)
367 {
368 /* if we start using the Hi Tx ring, this needs updateing */
369 typhoon_inc_index(index, count, TXLO_ENTRIES);
370 }
371
372 static inline void
373 typhoon_inc_rx_index(u32 *index, const int count)
374 {
375 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
376 *index += count * sizeof(struct rx_desc);
377 *index %= RX_ENTRIES * sizeof(struct rx_desc);
378 }
379
380 static int
381 typhoon_reset(void __iomem *ioaddr, int wait_type)
382 {
383 int i, err = 0;
384 int timeout;
385
386 if(wait_type == WaitNoSleep)
387 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
388 else
389 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
390
391 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
392 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
393
394 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
395 typhoon_post_pci_writes(ioaddr);
396 udelay(1);
397 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
398
399 if(wait_type != NoWait) {
400 for(i = 0; i < timeout; i++) {
401 if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
402 TYPHOON_STATUS_WAITING_FOR_HOST)
403 goto out;
404
405 if(wait_type == WaitSleep)
406 schedule_timeout_uninterruptible(1);
407 else
408 udelay(TYPHOON_UDELAY);
409 }
410
411 err = -ETIMEDOUT;
412 }
413
414 out:
415 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
416 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
417
418 /* The 3XP seems to need a little extra time to complete the load
419 * of the sleep image before we can reliably boot it. Failure to
420 * do this occasionally results in a hung adapter after boot in
421 * typhoon_init_one() while trying to read the MAC address or
422 * putting the card to sleep. 3Com's driver waits 5ms, but
423 * that seems to be overkill. However, if we can sleep, we might
424 * as well give it that much time. Otherwise, we'll give it 500us,
425 * which should be enough (I've see it work well at 100us, but still
426 * saw occasional problems.)
427 */
428 if(wait_type == WaitSleep)
429 msleep(5);
430 else
431 udelay(500);
432 return err;
433 }
434
435 static int
436 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
437 {
438 int i, err = 0;
439
440 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
441 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
442 goto out;
443 udelay(TYPHOON_UDELAY);
444 }
445
446 err = -ETIMEDOUT;
447
448 out:
449 return err;
450 }
451
452 static inline void
453 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
454 {
455 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
456 netif_carrier_off(dev);
457 else
458 netif_carrier_on(dev);
459 }
460
461 static inline void
462 typhoon_hello(struct typhoon *tp)
463 {
464 struct basic_ring *ring = &tp->cmdRing;
465 struct cmd_desc *cmd;
466
467 /* We only get a hello request if we've not sent anything to the
468 * card in a long while. If the lock is held, then we're in the
469 * process of issuing a command, so we don't need to respond.
470 */
471 if(spin_trylock(&tp->command_lock)) {
472 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
473 typhoon_inc_cmd_index(&ring->lastWrite, 1);
474
475 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
476 wmb();
477 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
478 spin_unlock(&tp->command_lock);
479 }
480 }
481
482 static int
483 typhoon_process_response(struct typhoon *tp, int resp_size,
484 struct resp_desc *resp_save)
485 {
486 struct typhoon_indexes *indexes = tp->indexes;
487 struct resp_desc *resp;
488 u8 *base = tp->respRing.ringBase;
489 int count, len, wrap_len;
490 u32 cleared;
491 u32 ready;
492
493 cleared = le32_to_cpu(indexes->respCleared);
494 ready = le32_to_cpu(indexes->respReady);
495 while(cleared != ready) {
496 resp = (struct resp_desc *)(base + cleared);
497 count = resp->numDesc + 1;
498 if(resp_save && resp->seqNo) {
499 if(count > resp_size) {
500 resp_save->flags = TYPHOON_RESP_ERROR;
501 goto cleanup;
502 }
503
504 wrap_len = 0;
505 len = count * sizeof(*resp);
506 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
507 wrap_len = cleared + len - RESPONSE_RING_SIZE;
508 len = RESPONSE_RING_SIZE - cleared;
509 }
510
511 memcpy(resp_save, resp, len);
512 if(unlikely(wrap_len)) {
513 resp_save += len / sizeof(*resp);
514 memcpy(resp_save, base, wrap_len);
515 }
516
517 resp_save = NULL;
518 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
519 typhoon_media_status(tp->dev, resp);
520 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
521 typhoon_hello(tp);
522 } else {
523 netdev_err(tp->dev,
524 "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
525 le16_to_cpu(resp->cmd),
526 resp->numDesc, resp->flags,
527 le16_to_cpu(resp->parm1),
528 le32_to_cpu(resp->parm2),
529 le32_to_cpu(resp->parm3));
530 }
531
532 cleanup:
533 typhoon_inc_resp_index(&cleared, count);
534 }
535
536 indexes->respCleared = cpu_to_le32(cleared);
537 wmb();
538 return resp_save == NULL;
539 }
540
541 static inline int
542 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
543 {
544 /* this works for all descriptors but rx_desc, as they are a
545 * different size than the cmd_desc -- everyone else is the same
546 */
547 lastWrite /= sizeof(struct cmd_desc);
548 lastRead /= sizeof(struct cmd_desc);
549 return (ringSize + lastRead - lastWrite - 1) % ringSize;
550 }
551
552 static inline int
553 typhoon_num_free_cmd(struct typhoon *tp)
554 {
555 int lastWrite = tp->cmdRing.lastWrite;
556 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
557
558 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
559 }
560
561 static inline int
562 typhoon_num_free_resp(struct typhoon *tp)
563 {
564 int respReady = le32_to_cpu(tp->indexes->respReady);
565 int respCleared = le32_to_cpu(tp->indexes->respCleared);
566
567 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
568 }
569
570 static inline int
571 typhoon_num_free_tx(struct transmit_ring *ring)
572 {
573 /* if we start using the Hi Tx ring, this needs updating */
574 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
575 }
576
577 static int
578 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
579 int num_resp, struct resp_desc *resp)
580 {
581 struct typhoon_indexes *indexes = tp->indexes;
582 struct basic_ring *ring = &tp->cmdRing;
583 struct resp_desc local_resp;
584 int i, err = 0;
585 int got_resp;
586 int freeCmd, freeResp;
587 int len, wrap_len;
588
589 spin_lock(&tp->command_lock);
590
591 freeCmd = typhoon_num_free_cmd(tp);
592 freeResp = typhoon_num_free_resp(tp);
593
594 if(freeCmd < num_cmd || freeResp < num_resp) {
595 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
596 freeCmd, num_cmd, freeResp, num_resp);
597 err = -ENOMEM;
598 goto out;
599 }
600
601 if(cmd->flags & TYPHOON_CMD_RESPOND) {
602 /* If we're expecting a response, but the caller hasn't given
603 * us a place to put it, we'll provide one.
604 */
605 tp->awaiting_resp = 1;
606 if(resp == NULL) {
607 resp = &local_resp;
608 num_resp = 1;
609 }
610 }
611
612 wrap_len = 0;
613 len = num_cmd * sizeof(*cmd);
614 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
615 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
616 len = COMMAND_RING_SIZE - ring->lastWrite;
617 }
618
619 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
620 if(unlikely(wrap_len)) {
621 struct cmd_desc *wrap_ptr = cmd;
622 wrap_ptr += len / sizeof(*cmd);
623 memcpy(ring->ringBase, wrap_ptr, wrap_len);
624 }
625
626 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
627
628 /* "I feel a presence... another warrior is on the mesa."
629 */
630 wmb();
631 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
632 typhoon_post_pci_writes(tp->ioaddr);
633
634 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
635 goto out;
636
637 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
638 * preempt or do anything other than take interrupts. So, don't
639 * wait for a response unless you have to.
640 *
641 * I've thought about trying to sleep here, but we're called
642 * from many contexts that don't allow that. Also, given the way
643 * 3Com has implemented irq coalescing, we would likely timeout --
644 * this has been observed in real life!
645 *
646 * The big killer is we have to wait to get stats from the card,
647 * though we could go to a periodic refresh of those if we don't
648 * mind them getting somewhat stale. The rest of the waiting
649 * commands occur during open/close/suspend/resume, so they aren't
650 * time critical. Creating SAs in the future will also have to
651 * wait here.
652 */
653 got_resp = 0;
654 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
655 if(indexes->respCleared != indexes->respReady)
656 got_resp = typhoon_process_response(tp, num_resp,
657 resp);
658 udelay(TYPHOON_UDELAY);
659 }
660
661 if(!got_resp) {
662 err = -ETIMEDOUT;
663 goto out;
664 }
665
666 /* Collect the error response even if we don't care about the
667 * rest of the response
668 */
669 if(resp->flags & TYPHOON_RESP_ERROR)
670 err = -EIO;
671
672 out:
673 if(tp->awaiting_resp) {
674 tp->awaiting_resp = 0;
675 smp_wmb();
676
677 /* Ugh. If a response was added to the ring between
678 * the call to typhoon_process_response() and the clearing
679 * of tp->awaiting_resp, we could have missed the interrupt
680 * and it could hang in the ring an indeterminate amount of
681 * time. So, check for it, and interrupt ourselves if this
682 * is the case.
683 */
684 if(indexes->respCleared != indexes->respReady)
685 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
686 }
687
688 spin_unlock(&tp->command_lock);
689 return err;
690 }
691
692 static inline void
693 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
694 u32 ring_dma)
695 {
696 struct tcpopt_desc *tcpd;
697 u32 tcpd_offset = ring_dma;
698
699 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
700 tcpd_offset += txRing->lastWrite;
701 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
702 typhoon_inc_tx_index(&txRing->lastWrite, 1);
703
704 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
705 tcpd->numDesc = 1;
706 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
707 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
708 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
709 tcpd->bytesTx = cpu_to_le32(skb->len);
710 tcpd->status = 0;
711 }
712
713 static netdev_tx_t
714 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
715 {
716 struct typhoon *tp = netdev_priv(dev);
717 struct transmit_ring *txRing;
718 struct tx_desc *txd, *first_txd;
719 dma_addr_t skb_dma;
720 int numDesc;
721
722 /* we have two rings to choose from, but we only use txLo for now
723 * If we start using the Hi ring as well, we'll need to update
724 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
725 * and TXHI_ENTRIES to match, as well as update the TSO code below
726 * to get the right DMA address
727 */
728 txRing = &tp->txLoRing;
729
730 /* We need one descriptor for each fragment of the sk_buff, plus the
731 * one for the ->data area of it.
732 *
733 * The docs say a maximum of 16 fragment descriptors per TCP option
734 * descriptor, then make a new packet descriptor and option descriptor
735 * for the next 16 fragments. The engineers say just an option
736 * descriptor is needed. I've tested up to 26 fragments with a single
737 * packet descriptor/option descriptor combo, so I use that for now.
738 *
739 * If problems develop with TSO, check this first.
740 */
741 numDesc = skb_shinfo(skb)->nr_frags + 1;
742 if (skb_is_gso(skb))
743 numDesc++;
744
745 /* When checking for free space in the ring, we need to also
746 * account for the initial Tx descriptor, and we always must leave
747 * at least one descriptor unused in the ring so that it doesn't
748 * wrap and look empty.
749 *
750 * The only time we should loop here is when we hit the race
751 * between marking the queue awake and updating the cleared index.
752 * Just loop and it will appear. This comes from the acenic driver.
753 */
754 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
755 smp_rmb();
756
757 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
758 typhoon_inc_tx_index(&txRing->lastWrite, 1);
759
760 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
761 first_txd->numDesc = 0;
762 first_txd->len = 0;
763 first_txd->tx_addr = (u64)((unsigned long) skb);
764 first_txd->processFlags = 0;
765
766 if(skb->ip_summed == CHECKSUM_PARTIAL) {
767 /* The 3XP will figure out if this is UDP/TCP */
768 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
769 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
770 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
771 }
772
773 if(vlan_tx_tag_present(skb)) {
774 first_txd->processFlags |=
775 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
776 first_txd->processFlags |=
777 cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
778 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
779 }
780
781 if (skb_is_gso(skb)) {
782 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
783 first_txd->numDesc++;
784
785 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
786 }
787
788 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
789 typhoon_inc_tx_index(&txRing->lastWrite, 1);
790
791 /* No need to worry about padding packet -- the firmware pads
792 * it with zeros to ETH_ZLEN for us.
793 */
794 if(skb_shinfo(skb)->nr_frags == 0) {
795 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
796 PCI_DMA_TODEVICE);
797 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
798 txd->len = cpu_to_le16(skb->len);
799 txd->frag.addr = cpu_to_le32(skb_dma);
800 txd->frag.addrHi = 0;
801 first_txd->numDesc++;
802 } else {
803 int i, len;
804
805 len = skb_headlen(skb);
806 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
807 PCI_DMA_TODEVICE);
808 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
809 txd->len = cpu_to_le16(len);
810 txd->frag.addr = cpu_to_le32(skb_dma);
811 txd->frag.addrHi = 0;
812 first_txd->numDesc++;
813
814 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
815 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
816 void *frag_addr;
817
818 txd = (struct tx_desc *) (txRing->ringBase +
819 txRing->lastWrite);
820 typhoon_inc_tx_index(&txRing->lastWrite, 1);
821
822 len = frag->size;
823 frag_addr = (void *) page_address(frag->page) +
824 frag->page_offset;
825 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
826 PCI_DMA_TODEVICE);
827 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
828 txd->len = cpu_to_le16(len);
829 txd->frag.addr = cpu_to_le32(skb_dma);
830 txd->frag.addrHi = 0;
831 first_txd->numDesc++;
832 }
833 }
834
835 /* Kick the 3XP
836 */
837 wmb();
838 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
839
840 /* If we don't have room to put the worst case packet on the
841 * queue, then we must stop the queue. We need 2 extra
842 * descriptors -- one to prevent ring wrap, and one for the
843 * Tx header.
844 */
845 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
846
847 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
848 netif_stop_queue(dev);
849
850 /* A Tx complete IRQ could have gotten inbetween, making
851 * the ring free again. Only need to recheck here, since
852 * Tx is serialized.
853 */
854 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
855 netif_wake_queue(dev);
856 }
857
858 return NETDEV_TX_OK;
859 }
860
861 static void
862 typhoon_set_rx_mode(struct net_device *dev)
863 {
864 struct typhoon *tp = netdev_priv(dev);
865 struct cmd_desc xp_cmd;
866 u32 mc_filter[2];
867 __le16 filter;
868
869 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
870 if(dev->flags & IFF_PROMISC) {
871 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
872 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
873 (dev->flags & IFF_ALLMULTI)) {
874 /* Too many to match, or accept all multicasts. */
875 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
876 } else if (!netdev_mc_empty(dev)) {
877 struct netdev_hw_addr *ha;
878
879 memset(mc_filter, 0, sizeof(mc_filter));
880 netdev_for_each_mc_addr(ha, dev) {
881 int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
882 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
883 }
884
885 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
886 TYPHOON_CMD_SET_MULTICAST_HASH);
887 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
888 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
889 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
890 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
891
892 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
893 }
894
895 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
896 xp_cmd.parm1 = filter;
897 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
898 }
899
900 static int
901 typhoon_do_get_stats(struct typhoon *tp)
902 {
903 struct net_device_stats *stats = &tp->stats;
904 struct net_device_stats *saved = &tp->stats_saved;
905 struct cmd_desc xp_cmd;
906 struct resp_desc xp_resp[7];
907 struct stats_resp *s = (struct stats_resp *) xp_resp;
908 int err;
909
910 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
911 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
912 if(err < 0)
913 return err;
914
915 /* 3Com's Linux driver uses txMultipleCollisions as it's
916 * collisions value, but there is some other collision info as well...
917 *
918 * The extra status reported would be a good candidate for
919 * ethtool_ops->get_{strings,stats}()
920 */
921 stats->tx_packets = le32_to_cpu(s->txPackets) +
922 saved->tx_packets;
923 stats->tx_bytes = le64_to_cpu(s->txBytes) +
924 saved->tx_bytes;
925 stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
926 saved->tx_errors;
927 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
928 saved->tx_carrier_errors;
929 stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
930 saved->collisions;
931 stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
932 saved->rx_packets;
933 stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
934 saved->rx_bytes;
935 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
936 saved->rx_fifo_errors;
937 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
938 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
939 saved->rx_errors;
940 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
941 saved->rx_crc_errors;
942 stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
943 saved->rx_length_errors;
944 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
945 SPEED_100 : SPEED_10;
946 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
947 DUPLEX_FULL : DUPLEX_HALF;
948
949 return 0;
950 }
951
952 static struct net_device_stats *
953 typhoon_get_stats(struct net_device *dev)
954 {
955 struct typhoon *tp = netdev_priv(dev);
956 struct net_device_stats *stats = &tp->stats;
957 struct net_device_stats *saved = &tp->stats_saved;
958
959 smp_rmb();
960 if(tp->card_state == Sleeping)
961 return saved;
962
963 if(typhoon_do_get_stats(tp) < 0) {
964 netdev_err(dev, "error getting stats\n");
965 return saved;
966 }
967
968 return stats;
969 }
970
971 static int
972 typhoon_set_mac_address(struct net_device *dev, void *addr)
973 {
974 struct sockaddr *saddr = (struct sockaddr *) addr;
975
976 if(netif_running(dev))
977 return -EBUSY;
978
979 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
980 return 0;
981 }
982
983 static void
984 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
985 {
986 struct typhoon *tp = netdev_priv(dev);
987 struct pci_dev *pci_dev = tp->pdev;
988 struct cmd_desc xp_cmd;
989 struct resp_desc xp_resp[3];
990
991 smp_rmb();
992 if(tp->card_state == Sleeping) {
993 strcpy(info->fw_version, "Sleep image");
994 } else {
995 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
996 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
997 strcpy(info->fw_version, "Unknown runtime");
998 } else {
999 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
1000 snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1001 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1002 sleep_ver & 0xfff);
1003 }
1004 }
1005
1006 strcpy(info->driver, KBUILD_MODNAME);
1007 strcpy(info->bus_info, pci_name(pci_dev));
1008 }
1009
1010 static int
1011 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1012 {
1013 struct typhoon *tp = netdev_priv(dev);
1014
1015 cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1016 SUPPORTED_Autoneg;
1017
1018 switch (tp->xcvr_select) {
1019 case TYPHOON_XCVR_10HALF:
1020 cmd->advertising = ADVERTISED_10baseT_Half;
1021 break;
1022 case TYPHOON_XCVR_10FULL:
1023 cmd->advertising = ADVERTISED_10baseT_Full;
1024 break;
1025 case TYPHOON_XCVR_100HALF:
1026 cmd->advertising = ADVERTISED_100baseT_Half;
1027 break;
1028 case TYPHOON_XCVR_100FULL:
1029 cmd->advertising = ADVERTISED_100baseT_Full;
1030 break;
1031 case TYPHOON_XCVR_AUTONEG:
1032 cmd->advertising = ADVERTISED_10baseT_Half |
1033 ADVERTISED_10baseT_Full |
1034 ADVERTISED_100baseT_Half |
1035 ADVERTISED_100baseT_Full |
1036 ADVERTISED_Autoneg;
1037 break;
1038 }
1039
1040 if(tp->capabilities & TYPHOON_FIBER) {
1041 cmd->supported |= SUPPORTED_FIBRE;
1042 cmd->advertising |= ADVERTISED_FIBRE;
1043 cmd->port = PORT_FIBRE;
1044 } else {
1045 cmd->supported |= SUPPORTED_10baseT_Half |
1046 SUPPORTED_10baseT_Full |
1047 SUPPORTED_TP;
1048 cmd->advertising |= ADVERTISED_TP;
1049 cmd->port = PORT_TP;
1050 }
1051
1052 /* need to get stats to make these link speed/duplex valid */
1053 typhoon_do_get_stats(tp);
1054 cmd->speed = tp->speed;
1055 cmd->duplex = tp->duplex;
1056 cmd->phy_address = 0;
1057 cmd->transceiver = XCVR_INTERNAL;
1058 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1059 cmd->autoneg = AUTONEG_ENABLE;
1060 else
1061 cmd->autoneg = AUTONEG_DISABLE;
1062 cmd->maxtxpkt = 1;
1063 cmd->maxrxpkt = 1;
1064
1065 return 0;
1066 }
1067
1068 static int
1069 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1070 {
1071 struct typhoon *tp = netdev_priv(dev);
1072 struct cmd_desc xp_cmd;
1073 __le16 xcvr;
1074 int err;
1075
1076 err = -EINVAL;
1077 if(cmd->autoneg == AUTONEG_ENABLE) {
1078 xcvr = TYPHOON_XCVR_AUTONEG;
1079 } else {
1080 if(cmd->duplex == DUPLEX_HALF) {
1081 if(cmd->speed == SPEED_10)
1082 xcvr = TYPHOON_XCVR_10HALF;
1083 else if(cmd->speed == SPEED_100)
1084 xcvr = TYPHOON_XCVR_100HALF;
1085 else
1086 goto out;
1087 } else if(cmd->duplex == DUPLEX_FULL) {
1088 if(cmd->speed == SPEED_10)
1089 xcvr = TYPHOON_XCVR_10FULL;
1090 else if(cmd->speed == SPEED_100)
1091 xcvr = TYPHOON_XCVR_100FULL;
1092 else
1093 goto out;
1094 } else
1095 goto out;
1096 }
1097
1098 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1099 xp_cmd.parm1 = xcvr;
1100 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1101 if(err < 0)
1102 goto out;
1103
1104 tp->xcvr_select = xcvr;
1105 if(cmd->autoneg == AUTONEG_ENABLE) {
1106 tp->speed = 0xff; /* invalid */
1107 tp->duplex = 0xff; /* invalid */
1108 } else {
1109 tp->speed = cmd->speed;
1110 tp->duplex = cmd->duplex;
1111 }
1112
1113 out:
1114 return err;
1115 }
1116
1117 static void
1118 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1119 {
1120 struct typhoon *tp = netdev_priv(dev);
1121
1122 wol->supported = WAKE_PHY | WAKE_MAGIC;
1123 wol->wolopts = 0;
1124 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1125 wol->wolopts |= WAKE_PHY;
1126 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1127 wol->wolopts |= WAKE_MAGIC;
1128 memset(&wol->sopass, 0, sizeof(wol->sopass));
1129 }
1130
1131 static int
1132 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1133 {
1134 struct typhoon *tp = netdev_priv(dev);
1135
1136 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1137 return -EINVAL;
1138
1139 tp->wol_events = 0;
1140 if(wol->wolopts & WAKE_PHY)
1141 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1142 if(wol->wolopts & WAKE_MAGIC)
1143 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1144
1145 return 0;
1146 }
1147
1148 static u32
1149 typhoon_get_rx_csum(struct net_device *dev)
1150 {
1151 /* For now, we don't allow turning off RX checksums.
1152 */
1153 return 1;
1154 }
1155
1156 static int
1157 typhoon_set_flags(struct net_device *dev, u32 data)
1158 {
1159 /* There's no way to turn off the RX VLAN offloading and stripping
1160 * on the current 3XP firmware -- it does not respect the offload
1161 * settings -- so we only allow the user to toggle the TX processing.
1162 */
1163 if (!(data & ETH_FLAG_RXVLAN))
1164 return -EINVAL;
1165
1166 return ethtool_op_set_flags(dev, data,
1167 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN);
1168 }
1169
1170 static void
1171 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1172 {
1173 ering->rx_max_pending = RXENT_ENTRIES;
1174 ering->rx_mini_max_pending = 0;
1175 ering->rx_jumbo_max_pending = 0;
1176 ering->tx_max_pending = TXLO_ENTRIES - 1;
1177
1178 ering->rx_pending = RXENT_ENTRIES;
1179 ering->rx_mini_pending = 0;
1180 ering->rx_jumbo_pending = 0;
1181 ering->tx_pending = TXLO_ENTRIES - 1;
1182 }
1183
1184 static const struct ethtool_ops typhoon_ethtool_ops = {
1185 .get_settings = typhoon_get_settings,
1186 .set_settings = typhoon_set_settings,
1187 .get_drvinfo = typhoon_get_drvinfo,
1188 .get_wol = typhoon_get_wol,
1189 .set_wol = typhoon_set_wol,
1190 .get_link = ethtool_op_get_link,
1191 .get_rx_csum = typhoon_get_rx_csum,
1192 .set_tx_csum = ethtool_op_set_tx_csum,
1193 .set_sg = ethtool_op_set_sg,
1194 .set_tso = ethtool_op_set_tso,
1195 .get_ringparam = typhoon_get_ringparam,
1196 .set_flags = typhoon_set_flags,
1197 .get_flags = ethtool_op_get_flags,
1198 };
1199
1200 static int
1201 typhoon_wait_interrupt(void __iomem *ioaddr)
1202 {
1203 int i, err = 0;
1204
1205 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1206 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1207 TYPHOON_INTR_BOOTCMD)
1208 goto out;
1209 udelay(TYPHOON_UDELAY);
1210 }
1211
1212 err = -ETIMEDOUT;
1213
1214 out:
1215 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1216 return err;
1217 }
1218
1219 #define shared_offset(x) offsetof(struct typhoon_shared, x)
1220
1221 static void
1222 typhoon_init_interface(struct typhoon *tp)
1223 {
1224 struct typhoon_interface *iface = &tp->shared->iface;
1225 dma_addr_t shared_dma;
1226
1227 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1228
1229 /* The *Hi members of iface are all init'd to zero by the memset().
1230 */
1231 shared_dma = tp->shared_dma + shared_offset(indexes);
1232 iface->ringIndex = cpu_to_le32(shared_dma);
1233
1234 shared_dma = tp->shared_dma + shared_offset(txLo);
1235 iface->txLoAddr = cpu_to_le32(shared_dma);
1236 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1237
1238 shared_dma = tp->shared_dma + shared_offset(txHi);
1239 iface->txHiAddr = cpu_to_le32(shared_dma);
1240 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1241
1242 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1243 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1244 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1245 sizeof(struct rx_free));
1246
1247 shared_dma = tp->shared_dma + shared_offset(rxLo);
1248 iface->rxLoAddr = cpu_to_le32(shared_dma);
1249 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1250
1251 shared_dma = tp->shared_dma + shared_offset(rxHi);
1252 iface->rxHiAddr = cpu_to_le32(shared_dma);
1253 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1254
1255 shared_dma = tp->shared_dma + shared_offset(cmd);
1256 iface->cmdAddr = cpu_to_le32(shared_dma);
1257 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1258
1259 shared_dma = tp->shared_dma + shared_offset(resp);
1260 iface->respAddr = cpu_to_le32(shared_dma);
1261 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1262
1263 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1264 iface->zeroAddr = cpu_to_le32(shared_dma);
1265
1266 tp->indexes = &tp->shared->indexes;
1267 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1268 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1269 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1270 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1271 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1272 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1273 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1274
1275 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1276 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1277
1278 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1279 tp->card_state = Sleeping;
1280
1281 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1282 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1283 tp->offload |= TYPHOON_OFFLOAD_VLAN;
1284
1285 spin_lock_init(&tp->command_lock);
1286
1287 /* Force the writes to the shared memory area out before continuing. */
1288 wmb();
1289 }
1290
1291 static void
1292 typhoon_init_rings(struct typhoon *tp)
1293 {
1294 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1295
1296 tp->txLoRing.lastWrite = 0;
1297 tp->txHiRing.lastWrite = 0;
1298 tp->rxLoRing.lastWrite = 0;
1299 tp->rxHiRing.lastWrite = 0;
1300 tp->rxBuffRing.lastWrite = 0;
1301 tp->cmdRing.lastWrite = 0;
1302 tp->respRing.lastWrite = 0;
1303
1304 tp->txLoRing.lastRead = 0;
1305 tp->txHiRing.lastRead = 0;
1306 }
1307
1308 static const struct firmware *typhoon_fw;
1309
1310 static int
1311 typhoon_request_firmware(struct typhoon *tp)
1312 {
1313 const struct typhoon_file_header *fHdr;
1314 const struct typhoon_section_header *sHdr;
1315 const u8 *image_data;
1316 u32 numSections;
1317 u32 section_len;
1318 u32 remaining;
1319 int err;
1320
1321 if (typhoon_fw)
1322 return 0;
1323
1324 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1325 if (err) {
1326 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1327 FIRMWARE_NAME);
1328 return err;
1329 }
1330
1331 image_data = (u8 *) typhoon_fw->data;
1332 remaining = typhoon_fw->size;
1333 if (remaining < sizeof(struct typhoon_file_header))
1334 goto invalid_fw;
1335
1336 fHdr = (struct typhoon_file_header *) image_data;
1337 if (memcmp(fHdr->tag, "TYPHOON", 8))
1338 goto invalid_fw;
1339
1340 numSections = le32_to_cpu(fHdr->numSections);
1341 image_data += sizeof(struct typhoon_file_header);
1342 remaining -= sizeof(struct typhoon_file_header);
1343
1344 while (numSections--) {
1345 if (remaining < sizeof(struct typhoon_section_header))
1346 goto invalid_fw;
1347
1348 sHdr = (struct typhoon_section_header *) image_data;
1349 image_data += sizeof(struct typhoon_section_header);
1350 section_len = le32_to_cpu(sHdr->len);
1351
1352 if (remaining < section_len)
1353 goto invalid_fw;
1354
1355 image_data += section_len;
1356 remaining -= section_len;
1357 }
1358
1359 return 0;
1360
1361 invalid_fw:
1362 netdev_err(tp->dev, "Invalid firmware image\n");
1363 release_firmware(typhoon_fw);
1364 typhoon_fw = NULL;
1365 return -EINVAL;
1366 }
1367
1368 static int
1369 typhoon_download_firmware(struct typhoon *tp)
1370 {
1371 void __iomem *ioaddr = tp->ioaddr;
1372 struct pci_dev *pdev = tp->pdev;
1373 const struct typhoon_file_header *fHdr;
1374 const struct typhoon_section_header *sHdr;
1375 const u8 *image_data;
1376 void *dpage;
1377 dma_addr_t dpage_dma;
1378 __sum16 csum;
1379 u32 irqEnabled;
1380 u32 irqMasked;
1381 u32 numSections;
1382 u32 section_len;
1383 u32 len;
1384 u32 load_addr;
1385 u32 hmac;
1386 int i;
1387 int err;
1388
1389 image_data = (u8 *) typhoon_fw->data;
1390 fHdr = (struct typhoon_file_header *) image_data;
1391
1392 /* Cannot just map the firmware image using pci_map_single() as
1393 * the firmware is vmalloc()'d and may not be physically contiguous,
1394 * so we allocate some consistent memory to copy the sections into.
1395 */
1396 err = -ENOMEM;
1397 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1398 if(!dpage) {
1399 netdev_err(tp->dev, "no DMA mem for firmware\n");
1400 goto err_out;
1401 }
1402
1403 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1404 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1405 ioaddr + TYPHOON_REG_INTR_ENABLE);
1406 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1407 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1408 ioaddr + TYPHOON_REG_INTR_MASK);
1409
1410 err = -ETIMEDOUT;
1411 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1412 netdev_err(tp->dev, "card ready timeout\n");
1413 goto err_out_irq;
1414 }
1415
1416 numSections = le32_to_cpu(fHdr->numSections);
1417 load_addr = le32_to_cpu(fHdr->startAddr);
1418
1419 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1420 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1421 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1422 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1423 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1424 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1425 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1426 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1427 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1428 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1429 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1430 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1431 typhoon_post_pci_writes(ioaddr);
1432 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1433
1434 image_data += sizeof(struct typhoon_file_header);
1435
1436 /* The ioread32() in typhoon_wait_interrupt() will force the
1437 * last write to the command register to post, so
1438 * we don't need a typhoon_post_pci_writes() after it.
1439 */
1440 for(i = 0; i < numSections; i++) {
1441 sHdr = (struct typhoon_section_header *) image_data;
1442 image_data += sizeof(struct typhoon_section_header);
1443 load_addr = le32_to_cpu(sHdr->startAddr);
1444 section_len = le32_to_cpu(sHdr->len);
1445
1446 while(section_len) {
1447 len = min_t(u32, section_len, PAGE_SIZE);
1448
1449 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1450 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1451 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1452 netdev_err(tp->dev, "segment ready timeout\n");
1453 goto err_out_irq;
1454 }
1455
1456 /* Do an pseudo IPv4 checksum on the data -- first
1457 * need to convert each u16 to cpu order before
1458 * summing. Fortunately, due to the properties of
1459 * the checksum, we can do this once, at the end.
1460 */
1461 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1462 dpage, len,
1463 0));
1464
1465 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1466 iowrite32(le16_to_cpu((__force __le16)csum),
1467 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1468 iowrite32(load_addr,
1469 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1470 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1471 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1472 typhoon_post_pci_writes(ioaddr);
1473 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1474 ioaddr + TYPHOON_REG_COMMAND);
1475
1476 image_data += len;
1477 load_addr += len;
1478 section_len -= len;
1479 }
1480 }
1481
1482 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1483 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1484 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1485 netdev_err(tp->dev, "final segment ready timeout\n");
1486 goto err_out_irq;
1487 }
1488
1489 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1490
1491 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1492 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1493 ioread32(ioaddr + TYPHOON_REG_STATUS));
1494 goto err_out_irq;
1495 }
1496
1497 err = 0;
1498
1499 err_out_irq:
1500 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1501 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1502
1503 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1504
1505 err_out:
1506 return err;
1507 }
1508
1509 static int
1510 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1511 {
1512 void __iomem *ioaddr = tp->ioaddr;
1513
1514 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1515 netdev_err(tp->dev, "boot ready timeout\n");
1516 goto out_timeout;
1517 }
1518
1519 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1520 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1521 typhoon_post_pci_writes(ioaddr);
1522 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1523 ioaddr + TYPHOON_REG_COMMAND);
1524
1525 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1526 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1527 ioread32(ioaddr + TYPHOON_REG_STATUS));
1528 goto out_timeout;
1529 }
1530
1531 /* Clear the Transmit and Command ready registers
1532 */
1533 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1534 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1535 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1536 typhoon_post_pci_writes(ioaddr);
1537 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1538
1539 return 0;
1540
1541 out_timeout:
1542 return -ETIMEDOUT;
1543 }
1544
1545 static u32
1546 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1547 volatile __le32 * index)
1548 {
1549 u32 lastRead = txRing->lastRead;
1550 struct tx_desc *tx;
1551 dma_addr_t skb_dma;
1552 int dma_len;
1553 int type;
1554
1555 while(lastRead != le32_to_cpu(*index)) {
1556 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1557 type = tx->flags & TYPHOON_TYPE_MASK;
1558
1559 if(type == TYPHOON_TX_DESC) {
1560 /* This tx_desc describes a packet.
1561 */
1562 unsigned long ptr = tx->tx_addr;
1563 struct sk_buff *skb = (struct sk_buff *) ptr;
1564 dev_kfree_skb_irq(skb);
1565 } else if(type == TYPHOON_FRAG_DESC) {
1566 /* This tx_desc describes a memory mapping. Free it.
1567 */
1568 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1569 dma_len = le16_to_cpu(tx->len);
1570 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1571 PCI_DMA_TODEVICE);
1572 }
1573
1574 tx->flags = 0;
1575 typhoon_inc_tx_index(&lastRead, 1);
1576 }
1577
1578 return lastRead;
1579 }
1580
1581 static void
1582 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1583 volatile __le32 * index)
1584 {
1585 u32 lastRead;
1586 int numDesc = MAX_SKB_FRAGS + 1;
1587
1588 /* This will need changing if we start to use the Hi Tx ring. */
1589 lastRead = typhoon_clean_tx(tp, txRing, index);
1590 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1591 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1592 netif_wake_queue(tp->dev);
1593
1594 txRing->lastRead = lastRead;
1595 smp_wmb();
1596 }
1597
1598 static void
1599 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1600 {
1601 struct typhoon_indexes *indexes = tp->indexes;
1602 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1603 struct basic_ring *ring = &tp->rxBuffRing;
1604 struct rx_free *r;
1605
1606 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1607 le32_to_cpu(indexes->rxBuffCleared)) {
1608 /* no room in ring, just drop the skb
1609 */
1610 dev_kfree_skb_any(rxb->skb);
1611 rxb->skb = NULL;
1612 return;
1613 }
1614
1615 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1616 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1617 r->virtAddr = idx;
1618 r->physAddr = cpu_to_le32(rxb->dma_addr);
1619
1620 /* Tell the card about it */
1621 wmb();
1622 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1623 }
1624
1625 static int
1626 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1627 {
1628 struct typhoon_indexes *indexes = tp->indexes;
1629 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1630 struct basic_ring *ring = &tp->rxBuffRing;
1631 struct rx_free *r;
1632 struct sk_buff *skb;
1633 dma_addr_t dma_addr;
1634
1635 rxb->skb = NULL;
1636
1637 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1638 le32_to_cpu(indexes->rxBuffCleared))
1639 return -ENOMEM;
1640
1641 skb = dev_alloc_skb(PKT_BUF_SZ);
1642 if(!skb)
1643 return -ENOMEM;
1644
1645 #if 0
1646 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1647 * address! Pretty please?
1648 */
1649 skb_reserve(skb, 2);
1650 #endif
1651
1652 skb->dev = tp->dev;
1653 dma_addr = pci_map_single(tp->pdev, skb->data,
1654 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1655
1656 /* Since no card does 64 bit DAC, the high bits will never
1657 * change from zero.
1658 */
1659 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1660 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1661 r->virtAddr = idx;
1662 r->physAddr = cpu_to_le32(dma_addr);
1663 rxb->skb = skb;
1664 rxb->dma_addr = dma_addr;
1665
1666 /* Tell the card about it */
1667 wmb();
1668 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1669 return 0;
1670 }
1671
1672 static int
1673 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1674 volatile __le32 * cleared, int budget)
1675 {
1676 struct rx_desc *rx;
1677 struct sk_buff *skb, *new_skb;
1678 struct rxbuff_ent *rxb;
1679 dma_addr_t dma_addr;
1680 u32 local_ready;
1681 u32 rxaddr;
1682 int pkt_len;
1683 u32 idx;
1684 __le32 csum_bits;
1685 int received;
1686
1687 received = 0;
1688 local_ready = le32_to_cpu(*ready);
1689 rxaddr = le32_to_cpu(*cleared);
1690 while(rxaddr != local_ready && budget > 0) {
1691 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1692 idx = rx->addr;
1693 rxb = &tp->rxbuffers[idx];
1694 skb = rxb->skb;
1695 dma_addr = rxb->dma_addr;
1696
1697 typhoon_inc_rx_index(&rxaddr, 1);
1698
1699 if(rx->flags & TYPHOON_RX_ERROR) {
1700 typhoon_recycle_rx_skb(tp, idx);
1701 continue;
1702 }
1703
1704 pkt_len = le16_to_cpu(rx->frameLen);
1705
1706 if(pkt_len < rx_copybreak &&
1707 (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1708 skb_reserve(new_skb, 2);
1709 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1710 PKT_BUF_SZ,
1711 PCI_DMA_FROMDEVICE);
1712 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1713 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1714 PKT_BUF_SZ,
1715 PCI_DMA_FROMDEVICE);
1716 skb_put(new_skb, pkt_len);
1717 typhoon_recycle_rx_skb(tp, idx);
1718 } else {
1719 new_skb = skb;
1720 skb_put(new_skb, pkt_len);
1721 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1722 PCI_DMA_FROMDEVICE);
1723 typhoon_alloc_rx_skb(tp, idx);
1724 }
1725 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1726 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1727 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1728 if(csum_bits ==
1729 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1730 csum_bits ==
1731 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1732 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1733 } else
1734 skb_checksum_none_assert(new_skb);
1735
1736 if (rx->rxStatus & TYPHOON_RX_VLAN)
1737 __vlan_hwaccel_put_tag(new_skb,
1738 ntohl(rx->vlanTag) & 0xffff);
1739 netif_receive_skb(new_skb);
1740
1741 received++;
1742 budget--;
1743 }
1744 *cleared = cpu_to_le32(rxaddr);
1745
1746 return received;
1747 }
1748
1749 static void
1750 typhoon_fill_free_ring(struct typhoon *tp)
1751 {
1752 u32 i;
1753
1754 for(i = 0; i < RXENT_ENTRIES; i++) {
1755 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1756 if(rxb->skb)
1757 continue;
1758 if(typhoon_alloc_rx_skb(tp, i) < 0)
1759 break;
1760 }
1761 }
1762
1763 static int
1764 typhoon_poll(struct napi_struct *napi, int budget)
1765 {
1766 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1767 struct typhoon_indexes *indexes = tp->indexes;
1768 int work_done;
1769
1770 rmb();
1771 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1772 typhoon_process_response(tp, 0, NULL);
1773
1774 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1775 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1776
1777 work_done = 0;
1778
1779 if(indexes->rxHiCleared != indexes->rxHiReady) {
1780 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1781 &indexes->rxHiCleared, budget);
1782 }
1783
1784 if(indexes->rxLoCleared != indexes->rxLoReady) {
1785 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1786 &indexes->rxLoCleared, budget - work_done);
1787 }
1788
1789 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1790 /* rxBuff ring is empty, try to fill it. */
1791 typhoon_fill_free_ring(tp);
1792 }
1793
1794 if (work_done < budget) {
1795 napi_complete(napi);
1796 iowrite32(TYPHOON_INTR_NONE,
1797 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1798 typhoon_post_pci_writes(tp->ioaddr);
1799 }
1800
1801 return work_done;
1802 }
1803
1804 static irqreturn_t
1805 typhoon_interrupt(int irq, void *dev_instance)
1806 {
1807 struct net_device *dev = dev_instance;
1808 struct typhoon *tp = netdev_priv(dev);
1809 void __iomem *ioaddr = tp->ioaddr;
1810 u32 intr_status;
1811
1812 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1813 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1814 return IRQ_NONE;
1815
1816 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1817
1818 if (napi_schedule_prep(&tp->napi)) {
1819 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1820 typhoon_post_pci_writes(ioaddr);
1821 __napi_schedule(&tp->napi);
1822 } else {
1823 netdev_err(dev, "Error, poll already scheduled\n");
1824 }
1825 return IRQ_HANDLED;
1826 }
1827
1828 static void
1829 typhoon_free_rx_rings(struct typhoon *tp)
1830 {
1831 u32 i;
1832
1833 for(i = 0; i < RXENT_ENTRIES; i++) {
1834 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1835 if(rxb->skb) {
1836 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1837 PCI_DMA_FROMDEVICE);
1838 dev_kfree_skb(rxb->skb);
1839 rxb->skb = NULL;
1840 }
1841 }
1842 }
1843
1844 static int
1845 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1846 {
1847 struct pci_dev *pdev = tp->pdev;
1848 void __iomem *ioaddr = tp->ioaddr;
1849 struct cmd_desc xp_cmd;
1850 int err;
1851
1852 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1853 xp_cmd.parm1 = events;
1854 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1855 if(err < 0) {
1856 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1857 err);
1858 return err;
1859 }
1860
1861 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1862 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1863 if(err < 0) {
1864 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1865 return err;
1866 }
1867
1868 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1869 return -ETIMEDOUT;
1870
1871 /* Since we cannot monitor the status of the link while sleeping,
1872 * tell the world it went away.
1873 */
1874 netif_carrier_off(tp->dev);
1875
1876 pci_enable_wake(tp->pdev, state, 1);
1877 pci_disable_device(pdev);
1878 return pci_set_power_state(pdev, state);
1879 }
1880
1881 static int
1882 typhoon_wakeup(struct typhoon *tp, int wait_type)
1883 {
1884 struct pci_dev *pdev = tp->pdev;
1885 void __iomem *ioaddr = tp->ioaddr;
1886
1887 pci_set_power_state(pdev, PCI_D0);
1888 pci_restore_state(pdev);
1889
1890 /* Post 2.x.x versions of the Sleep Image require a reset before
1891 * we can download the Runtime Image. But let's not make users of
1892 * the old firmware pay for the reset.
1893 */
1894 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1895 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1896 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1897 return typhoon_reset(ioaddr, wait_type);
1898
1899 return 0;
1900 }
1901
1902 static int
1903 typhoon_start_runtime(struct typhoon *tp)
1904 {
1905 struct net_device *dev = tp->dev;
1906 void __iomem *ioaddr = tp->ioaddr;
1907 struct cmd_desc xp_cmd;
1908 int err;
1909
1910 typhoon_init_rings(tp);
1911 typhoon_fill_free_ring(tp);
1912
1913 err = typhoon_download_firmware(tp);
1914 if(err < 0) {
1915 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1916 goto error_out;
1917 }
1918
1919 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1920 netdev_err(tp->dev, "cannot boot 3XP\n");
1921 err = -EIO;
1922 goto error_out;
1923 }
1924
1925 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1926 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1927 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1928 if(err < 0)
1929 goto error_out;
1930
1931 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1932 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1933 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1934 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1935 if(err < 0)
1936 goto error_out;
1937
1938 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1939 * us some more information on how to control it.
1940 */
1941 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1942 xp_cmd.parm1 = 0;
1943 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1944 if(err < 0)
1945 goto error_out;
1946
1947 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1948 xp_cmd.parm1 = tp->xcvr_select;
1949 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1950 if(err < 0)
1951 goto error_out;
1952
1953 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1954 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1955 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1956 if(err < 0)
1957 goto error_out;
1958
1959 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1960 xp_cmd.parm2 = tp->offload;
1961 xp_cmd.parm3 = tp->offload;
1962 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1963 if(err < 0)
1964 goto error_out;
1965
1966 typhoon_set_rx_mode(dev);
1967
1968 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1969 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1970 if(err < 0)
1971 goto error_out;
1972
1973 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1974 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1975 if(err < 0)
1976 goto error_out;
1977
1978 tp->card_state = Running;
1979 smp_wmb();
1980
1981 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1982 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1983 typhoon_post_pci_writes(ioaddr);
1984
1985 return 0;
1986
1987 error_out:
1988 typhoon_reset(ioaddr, WaitNoSleep);
1989 typhoon_free_rx_rings(tp);
1990 typhoon_init_rings(tp);
1991 return err;
1992 }
1993
1994 static int
1995 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1996 {
1997 struct typhoon_indexes *indexes = tp->indexes;
1998 struct transmit_ring *txLo = &tp->txLoRing;
1999 void __iomem *ioaddr = tp->ioaddr;
2000 struct cmd_desc xp_cmd;
2001 int i;
2002
2003 /* Disable interrupts early, since we can't schedule a poll
2004 * when called with !netif_running(). This will be posted
2005 * when we force the posting of the command.
2006 */
2007 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2008
2009 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2010 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2011
2012 /* Wait 1/2 sec for any outstanding transmits to occur
2013 * We'll cleanup after the reset if this times out.
2014 */
2015 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2016 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2017 break;
2018 udelay(TYPHOON_UDELAY);
2019 }
2020
2021 if(i == TYPHOON_WAIT_TIMEOUT)
2022 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
2023
2024 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2025 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2026
2027 /* save the statistics so when we bring the interface up again,
2028 * the values reported to userspace are correct.
2029 */
2030 tp->card_state = Sleeping;
2031 smp_wmb();
2032 typhoon_do_get_stats(tp);
2033 memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2034
2035 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2036 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2037
2038 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2039 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2040
2041 if(typhoon_reset(ioaddr, wait_type) < 0) {
2042 netdev_err(tp->dev, "unable to reset 3XP\n");
2043 return -ETIMEDOUT;
2044 }
2045
2046 /* cleanup any outstanding Tx packets */
2047 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2048 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2049 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2050 }
2051
2052 return 0;
2053 }
2054
2055 static void
2056 typhoon_tx_timeout(struct net_device *dev)
2057 {
2058 struct typhoon *tp = netdev_priv(dev);
2059
2060 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2061 netdev_warn(dev, "could not reset in tx timeout\n");
2062 goto truly_dead;
2063 }
2064
2065 /* If we ever start using the Hi ring, it will need cleaning too */
2066 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2067 typhoon_free_rx_rings(tp);
2068
2069 if(typhoon_start_runtime(tp) < 0) {
2070 netdev_err(dev, "could not start runtime in tx timeout\n");
2071 goto truly_dead;
2072 }
2073
2074 netif_wake_queue(dev);
2075 return;
2076
2077 truly_dead:
2078 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2079 typhoon_reset(tp->ioaddr, NoWait);
2080 netif_carrier_off(dev);
2081 }
2082
2083 static int
2084 typhoon_open(struct net_device *dev)
2085 {
2086 struct typhoon *tp = netdev_priv(dev);
2087 int err;
2088
2089 err = typhoon_request_firmware(tp);
2090 if (err)
2091 goto out;
2092
2093 err = typhoon_wakeup(tp, WaitSleep);
2094 if(err < 0) {
2095 netdev_err(dev, "unable to wakeup device\n");
2096 goto out_sleep;
2097 }
2098
2099 err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2100 dev->name, dev);
2101 if(err < 0)
2102 goto out_sleep;
2103
2104 napi_enable(&tp->napi);
2105
2106 err = typhoon_start_runtime(tp);
2107 if(err < 0) {
2108 napi_disable(&tp->napi);
2109 goto out_irq;
2110 }
2111
2112 netif_start_queue(dev);
2113 return 0;
2114
2115 out_irq:
2116 free_irq(dev->irq, dev);
2117
2118 out_sleep:
2119 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2120 netdev_err(dev, "unable to reboot into sleep img\n");
2121 typhoon_reset(tp->ioaddr, NoWait);
2122 goto out;
2123 }
2124
2125 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2126 netdev_err(dev, "unable to go back to sleep\n");
2127
2128 out:
2129 return err;
2130 }
2131
2132 static int
2133 typhoon_close(struct net_device *dev)
2134 {
2135 struct typhoon *tp = netdev_priv(dev);
2136
2137 netif_stop_queue(dev);
2138 napi_disable(&tp->napi);
2139
2140 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2141 netdev_err(dev, "unable to stop runtime\n");
2142
2143 /* Make sure there is no irq handler running on a different CPU. */
2144 free_irq(dev->irq, dev);
2145
2146 typhoon_free_rx_rings(tp);
2147 typhoon_init_rings(tp);
2148
2149 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2150 netdev_err(dev, "unable to boot sleep image\n");
2151
2152 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2153 netdev_err(dev, "unable to put card to sleep\n");
2154
2155 return 0;
2156 }
2157
2158 #ifdef CONFIG_PM
2159 static int
2160 typhoon_resume(struct pci_dev *pdev)
2161 {
2162 struct net_device *dev = pci_get_drvdata(pdev);
2163 struct typhoon *tp = netdev_priv(dev);
2164
2165 /* If we're down, resume when we are upped.
2166 */
2167 if(!netif_running(dev))
2168 return 0;
2169
2170 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2171 netdev_err(dev, "critical: could not wake up in resume\n");
2172 goto reset;
2173 }
2174
2175 if(typhoon_start_runtime(tp) < 0) {
2176 netdev_err(dev, "critical: could not start runtime in resume\n");
2177 goto reset;
2178 }
2179
2180 netif_device_attach(dev);
2181 return 0;
2182
2183 reset:
2184 typhoon_reset(tp->ioaddr, NoWait);
2185 return -EBUSY;
2186 }
2187
2188 static int
2189 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2190 {
2191 struct net_device *dev = pci_get_drvdata(pdev);
2192 struct typhoon *tp = netdev_priv(dev);
2193 struct cmd_desc xp_cmd;
2194
2195 /* If we're down, we're already suspended.
2196 */
2197 if(!netif_running(dev))
2198 return 0;
2199
2200 /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2201 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2202 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2203
2204 netif_device_detach(dev);
2205
2206 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2207 netdev_err(dev, "unable to stop runtime\n");
2208 goto need_resume;
2209 }
2210
2211 typhoon_free_rx_rings(tp);
2212 typhoon_init_rings(tp);
2213
2214 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2215 netdev_err(dev, "unable to boot sleep image\n");
2216 goto need_resume;
2217 }
2218
2219 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2220 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2221 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2222 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2223 netdev_err(dev, "unable to set mac address in suspend\n");
2224 goto need_resume;
2225 }
2226
2227 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2228 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2229 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2230 netdev_err(dev, "unable to set rx filter in suspend\n");
2231 goto need_resume;
2232 }
2233
2234 if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2235 netdev_err(dev, "unable to put card to sleep\n");
2236 goto need_resume;
2237 }
2238
2239 return 0;
2240
2241 need_resume:
2242 typhoon_resume(pdev);
2243 return -EBUSY;
2244 }
2245 #endif
2246
2247 static int __devinit
2248 typhoon_test_mmio(struct pci_dev *pdev)
2249 {
2250 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2251 int mode = 0;
2252 u32 val;
2253
2254 if(!ioaddr)
2255 goto out;
2256
2257 if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2258 TYPHOON_STATUS_WAITING_FOR_HOST)
2259 goto out_unmap;
2260
2261 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2262 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2263 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2264
2265 /* Ok, see if we can change our interrupt status register by
2266 * sending ourselves an interrupt. If so, then MMIO works.
2267 * The 50usec delay is arbitrary -- it could probably be smaller.
2268 */
2269 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2270 if((val & TYPHOON_INTR_SELF) == 0) {
2271 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2272 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2273 udelay(50);
2274 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2275 if(val & TYPHOON_INTR_SELF)
2276 mode = 1;
2277 }
2278
2279 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2280 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2281 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2282 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2283
2284 out_unmap:
2285 pci_iounmap(pdev, ioaddr);
2286
2287 out:
2288 if(!mode)
2289 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2290 return mode;
2291 }
2292
2293 static const struct net_device_ops typhoon_netdev_ops = {
2294 .ndo_open = typhoon_open,
2295 .ndo_stop = typhoon_close,
2296 .ndo_start_xmit = typhoon_start_tx,
2297 .ndo_set_multicast_list = typhoon_set_rx_mode,
2298 .ndo_tx_timeout = typhoon_tx_timeout,
2299 .ndo_get_stats = typhoon_get_stats,
2300 .ndo_validate_addr = eth_validate_addr,
2301 .ndo_set_mac_address = typhoon_set_mac_address,
2302 .ndo_change_mtu = eth_change_mtu,
2303 };
2304
2305 static int __devinit
2306 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2307 {
2308 struct net_device *dev;
2309 struct typhoon *tp;
2310 int card_id = (int) ent->driver_data;
2311 void __iomem *ioaddr;
2312 void *shared;
2313 dma_addr_t shared_dma;
2314 struct cmd_desc xp_cmd;
2315 struct resp_desc xp_resp[3];
2316 int err = 0;
2317 const char *err_msg;
2318
2319 dev = alloc_etherdev(sizeof(*tp));
2320 if(dev == NULL) {
2321 err_msg = "unable to alloc new net device";
2322 err = -ENOMEM;
2323 goto error_out;
2324 }
2325 SET_NETDEV_DEV(dev, &pdev->dev);
2326
2327 err = pci_enable_device(pdev);
2328 if(err < 0) {
2329 err_msg = "unable to enable device";
2330 goto error_out_dev;
2331 }
2332
2333 err = pci_set_mwi(pdev);
2334 if(err < 0) {
2335 err_msg = "unable to set MWI";
2336 goto error_out_disable;
2337 }
2338
2339 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2340 if(err < 0) {
2341 err_msg = "No usable DMA configuration";
2342 goto error_out_mwi;
2343 }
2344
2345 /* sanity checks on IO and MMIO BARs
2346 */
2347 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2348 err_msg = "region #1 not a PCI IO resource, aborting";
2349 err = -ENODEV;
2350 goto error_out_mwi;
2351 }
2352 if(pci_resource_len(pdev, 0) < 128) {
2353 err_msg = "Invalid PCI IO region size, aborting";
2354 err = -ENODEV;
2355 goto error_out_mwi;
2356 }
2357 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2358 err_msg = "region #1 not a PCI MMIO resource, aborting";
2359 err = -ENODEV;
2360 goto error_out_mwi;
2361 }
2362 if(pci_resource_len(pdev, 1) < 128) {
2363 err_msg = "Invalid PCI MMIO region size, aborting";
2364 err = -ENODEV;
2365 goto error_out_mwi;
2366 }
2367
2368 err = pci_request_regions(pdev, KBUILD_MODNAME);
2369 if(err < 0) {
2370 err_msg = "could not request regions";
2371 goto error_out_mwi;
2372 }
2373
2374 /* map our registers
2375 */
2376 if(use_mmio != 0 && use_mmio != 1)
2377 use_mmio = typhoon_test_mmio(pdev);
2378
2379 ioaddr = pci_iomap(pdev, use_mmio, 128);
2380 if (!ioaddr) {
2381 err_msg = "cannot remap registers, aborting";
2382 err = -EIO;
2383 goto error_out_regions;
2384 }
2385
2386 /* allocate pci dma space for rx and tx descriptor rings
2387 */
2388 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2389 &shared_dma);
2390 if(!shared) {
2391 err_msg = "could not allocate DMA memory";
2392 err = -ENOMEM;
2393 goto error_out_remap;
2394 }
2395
2396 dev->irq = pdev->irq;
2397 tp = netdev_priv(dev);
2398 tp->shared = (struct typhoon_shared *) shared;
2399 tp->shared_dma = shared_dma;
2400 tp->pdev = pdev;
2401 tp->tx_pdev = pdev;
2402 tp->ioaddr = ioaddr;
2403 tp->tx_ioaddr = ioaddr;
2404 tp->dev = dev;
2405
2406 /* Init sequence:
2407 * 1) Reset the adapter to clear any bad juju
2408 * 2) Reload the sleep image
2409 * 3) Boot the sleep image
2410 * 4) Get the hardware address.
2411 * 5) Put the card to sleep.
2412 */
2413 if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2414 err_msg = "could not reset 3XP";
2415 err = -EIO;
2416 goto error_out_dma;
2417 }
2418
2419 /* Now that we've reset the 3XP and are sure it's not going to
2420 * write all over memory, enable bus mastering, and save our
2421 * state for resuming after a suspend.
2422 */
2423 pci_set_master(pdev);
2424 pci_save_state(pdev);
2425
2426 typhoon_init_interface(tp);
2427 typhoon_init_rings(tp);
2428
2429 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2430 err_msg = "cannot boot 3XP sleep image";
2431 err = -EIO;
2432 goto error_out_reset;
2433 }
2434
2435 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2436 if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2437 err_msg = "cannot read MAC address";
2438 err = -EIO;
2439 goto error_out_reset;
2440 }
2441
2442 *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2443 *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2444
2445 if(!is_valid_ether_addr(dev->dev_addr)) {
2446 err_msg = "Could not obtain valid ethernet address, aborting";
2447 goto error_out_reset;
2448 }
2449
2450 /* Read the Sleep Image version last, so the response is valid
2451 * later when we print out the version reported.
2452 */
2453 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2454 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2455 err_msg = "Could not get Sleep Image version";
2456 goto error_out_reset;
2457 }
2458
2459 tp->capabilities = typhoon_card_info[card_id].capabilities;
2460 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2461
2462 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2463 * READ_VERSIONS command. Those versions are OK after waking up
2464 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2465 * seem to need a little extra help to get started. Since we don't
2466 * know how to nudge it along, just kick it.
2467 */
2468 if(xp_resp[0].numDesc != 0)
2469 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2470
2471 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2472 err_msg = "cannot put adapter to sleep";
2473 err = -EIO;
2474 goto error_out_reset;
2475 }
2476
2477 /* The chip-specific entries in the device structure. */
2478 dev->netdev_ops = &typhoon_netdev_ops;
2479 netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2480 dev->watchdog_timeo = TX_TIMEOUT;
2481
2482 SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2483
2484 /* We can handle scatter gather, up to 16 entries, and
2485 * we can do IP checksumming (only version 4, doh...)
2486 */
2487 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2488 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2489 dev->features |= NETIF_F_TSO;
2490
2491 if(register_netdev(dev) < 0) {
2492 err_msg = "unable to register netdev";
2493 goto error_out_reset;
2494 }
2495
2496 pci_set_drvdata(pdev, dev);
2497
2498 netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2499 typhoon_card_info[card_id].name,
2500 use_mmio ? "MMIO" : "IO",
2501 (unsigned long long)pci_resource_start(pdev, use_mmio),
2502 dev->dev_addr);
2503
2504 /* xp_resp still contains the response to the READ_VERSIONS command.
2505 * For debugging, let the user know what version he has.
2506 */
2507 if(xp_resp[0].numDesc == 0) {
2508 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2509 * of version is Month/Day of build.
2510 */
2511 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2512 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2513 monthday >> 8, monthday & 0xff);
2514 } else if(xp_resp[0].numDesc == 2) {
2515 /* This is the Typhoon 1.1+ type Sleep Image
2516 */
2517 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2518 u8 *ver_string = (u8 *) &xp_resp[1];
2519 ver_string[25] = 0;
2520 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2521 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2522 sleep_ver & 0xfff, ver_string);
2523 } else {
2524 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2525 xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2526 }
2527
2528 return 0;
2529
2530 error_out_reset:
2531 typhoon_reset(ioaddr, NoWait);
2532
2533 error_out_dma:
2534 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2535 shared, shared_dma);
2536 error_out_remap:
2537 pci_iounmap(pdev, ioaddr);
2538 error_out_regions:
2539 pci_release_regions(pdev);
2540 error_out_mwi:
2541 pci_clear_mwi(pdev);
2542 error_out_disable:
2543 pci_disable_device(pdev);
2544 error_out_dev:
2545 free_netdev(dev);
2546 error_out:
2547 pr_err("%s: %s\n", pci_name(pdev), err_msg);
2548 return err;
2549 }
2550
2551 static void __devexit
2552 typhoon_remove_one(struct pci_dev *pdev)
2553 {
2554 struct net_device *dev = pci_get_drvdata(pdev);
2555 struct typhoon *tp = netdev_priv(dev);
2556
2557 unregister_netdev(dev);
2558 pci_set_power_state(pdev, PCI_D0);
2559 pci_restore_state(pdev);
2560 typhoon_reset(tp->ioaddr, NoWait);
2561 pci_iounmap(pdev, tp->ioaddr);
2562 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2563 tp->shared, tp->shared_dma);
2564 pci_release_regions(pdev);
2565 pci_clear_mwi(pdev);
2566 pci_disable_device(pdev);
2567 pci_set_drvdata(pdev, NULL);
2568 free_netdev(dev);
2569 }
2570
2571 static struct pci_driver typhoon_driver = {
2572 .name = KBUILD_MODNAME,
2573 .id_table = typhoon_pci_tbl,
2574 .probe = typhoon_init_one,
2575 .remove = __devexit_p(typhoon_remove_one),
2576 #ifdef CONFIG_PM
2577 .suspend = typhoon_suspend,
2578 .resume = typhoon_resume,
2579 #endif
2580 };
2581
2582 static int __init
2583 typhoon_init(void)
2584 {
2585 return pci_register_driver(&typhoon_driver);
2586 }
2587
2588 static void __exit
2589 typhoon_cleanup(void)
2590 {
2591 if (typhoon_fw)
2592 release_firmware(typhoon_fw);
2593 pci_unregister_driver(&typhoon_driver);
2594 }
2595
2596 module_init(typhoon_init);
2597 module_exit(typhoon_cleanup);
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