drivers/net/wireless/ath/ath.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH_H
  18 #define ATH_H
  19
  20 #include <linux/skbuff.h>
  21 #include <linux/if_ether.h>
  22 #include <linux/spinlock.h>
  23 #include <net/mac80211.h>
  24
  25 /*
  26  * The key cache is used for h/w cipher state and also for
  27  * tracking station state such as the current tx antenna.
  28  * We also setup a mapping table between key cache slot indices
  29  * and station state to short-circuit node lookups on rx.
  30  * Different parts have different size key caches.  We handle
  31  * up to ATH_KEYMAX entries (could dynamically allocate state).
  32  */
  33 #define ATH_KEYMAX              128     /* max key cache size we handle */
  34
  35 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  36
  37 struct ath_ani {
  38         bool caldone;
  39         unsigned int longcal_timer;
  40         unsigned int shortcal_timer;
  41         unsigned int resetcal_timer;
  42         unsigned int checkani_timer;
  43         struct timer_list timer;
  44 };
  45
  46 struct ath_cycle_counters {
  47         u32 cycles;
  48         u32 rx_busy;
  49         u32 rx_frame;
  50         u32 tx_frame;
  51 };
  52
  53 enum ath_device_state {
  54         ATH_HW_UNAVAILABLE,
  55         ATH_HW_INITIALIZED,
  56 };
  57
  58 enum ath_bus_type {
  59         ATH_PCI,
  60         ATH_AHB,
  61         ATH_USB,
  62 };
  63
  64 struct reg_dmn_pair_mapping {
  65         u16 regDmnEnum;
  66         u16 reg_5ghz_ctl;
  67         u16 reg_2ghz_ctl;
  68 };
  69
  70 struct ath_regulatory {
  71         char alpha2[2];
  72         u16 country_code;
  73         u16 max_power_level;
  74         u32 tp_scale;
  75         u16 current_rd;
  76         u16 current_rd_ext;
  77         int16_t power_limit;
  78         struct reg_dmn_pair_mapping *regpair;
  79 };
  80
  81 enum ath_crypt_caps {
  82         ATH_CRYPT_CAP_CIPHER_AESCCM             = BIT(0),
  83         ATH_CRYPT_CAP_MIC_COMBINED              = BIT(1),
  84 };
  85
  86 struct ath_keyval {
  87         u8 kv_type;
  88         u8 kv_pad;
  89         u16 kv_len;
  90         u8 kv_val[16]; /* TK */
  91         u8 kv_mic[8]; /* Michael MIC key */
  92         u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
  93                          * supports both MIC keys in the same key cache entry;
  94                          * in that case, kv_mic is the RX key) */
  95 };
  96
  97 enum ath_cipher {
  98         ATH_CIPHER_WEP = 0,
  99         ATH_CIPHER_AES_OCB = 1,
 100         ATH_CIPHER_AES_CCM = 2,
 101         ATH_CIPHER_CKIP = 3,
 102         ATH_CIPHER_TKIP = 4,
 103         ATH_CIPHER_CLR = 5,
 104         ATH_CIPHER_MIC = 127
 105 };
 106
 107 /**
 108  * struct ath_ops - Register read/write operations
 109  *
 110  * @read: Register read
 111  * @write: Register write
 112  * @enable_write_buffer: Enable multiple register writes
 113  * @write_flush: flush buffered register writes and disable buffering
 114  */
 115 struct ath_ops {
 116         unsigned int (*read)(void *, u32 reg_offset);
 117         void (*write)(void *, u32 val, u32 reg_offset);
 118         void (*enable_write_buffer)(void *);
 119         void (*write_flush) (void *);
 120 };
 121
 122 struct ath_common;
 123
 124 struct ath_bus_ops {
 125         enum ath_bus_type ath_bus_type;
 126         void (*read_cachesize)(struct ath_common *common, int *csz);
 127         bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
 128         void (*bt_coex_prep)(struct ath_common *common);
 129         void (*extn_synch_en)(struct ath_common *common);
 130 };
 131
 132 struct ath_common {
 133         void *ah;
 134         void *priv;
 135         struct ieee80211_hw *hw;
 136         int debug_mask;
 137         enum ath_device_state state;
 138
 139         struct ath_ani ani;
 140
 141         u16 cachelsz;
 142         u16 curaid;
 143         u8 macaddr[ETH_ALEN];
 144         u8 curbssid[ETH_ALEN];
 145         u8 bssidmask[ETH_ALEN];
 146
 147         u8 tx_chainmask;
 148         u8 rx_chainmask;
 149
 150         u32 rx_bufsize;
 151
 152         u32 keymax;
 153         DECLARE_BITMAP(keymap, ATH_KEYMAX);
 154         DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
 155         enum ath_crypt_caps crypt_caps;
 156
 157         unsigned int clockrate;
 158
 159         spinlock_t cc_lock;
 160         struct ath_cycle_counters cc_ani;
 161         struct ath_cycle_counters cc_survey;
 162
 163         struct ath_regulatory regulatory;
 164         const struct ath_ops *ops;
 165         const struct ath_bus_ops *bus_ops;
 166
 167         bool btcoex_enabled;
 168 };
 169
 170 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
 171                                 u32 len,
 172                                 gfp_t gfp_mask);
 173
 174 void ath_hw_setbssidmask(struct ath_common *common);
 175 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
 176 int ath_key_config(struct ath_common *common,
 177                           struct ieee80211_vif *vif,
 178                           struct ieee80211_sta *sta,
 179                           struct ieee80211_key_conf *key);
 180 bool ath_hw_keyreset(struct ath_common *common, u16 entry);
 181 void ath_hw_cycle_counters_update(struct ath_common *common);
 182 int32_t ath_hw_get_listen_time(struct ath_common *common);
 183
 184 extern __attribute__ ((format (printf, 3, 4))) int
 185 ath_printk(const char *level, struct ath_common *common, const char *fmt, ...);
 186
 187 #define ath_emerg(common, fmt, ...)                             \
 188         ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
 189 #define ath_alert(common, fmt, ...)                             \
 190         ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
 191 #define ath_crit(common, fmt, ...)                              \
 192         ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
 193 #define ath_err(common, fmt, ...)                               \
 194         ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
 195 #define ath_warn(common, fmt, ...)                              \
 196         ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
 197 #define ath_notice(common, fmt, ...)                            \
 198         ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
 199 #define ath_info(common, fmt, ...)                              \
 200         ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
 201
 202 /**
 203  * enum ath_debug_level - atheros wireless debug level
 204  *
 205  * @ATH_DBG_RESET: reset processing
 206  * @ATH_DBG_QUEUE: hardware queue management
 207  * @ATH_DBG_EEPROM: eeprom processing
 208  * @ATH_DBG_CALIBRATE: periodic calibration
 209  * @ATH_DBG_INTERRUPT: interrupt processing
 210  * @ATH_DBG_REGULATORY: regulatory processing
 211  * @ATH_DBG_ANI: adaptive noise immunitive processing
 212  * @ATH_DBG_XMIT: basic xmit operation
 213  * @ATH_DBG_BEACON: beacon handling
 214  * @ATH_DBG_CONFIG: configuration of the hardware
 215  * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
 216  * @ATH_DBG_PS: power save processing
 217  * @ATH_DBG_HWTIMER: hardware timer handling
 218  * @ATH_DBG_BTCOEX: bluetooth coexistance
 219  * @ATH_DBG_BSTUCK: stuck beacons
 220  * @ATH_DBG_ANY: enable all debugging
 221  *
 222  * The debug level is used to control the amount and type of debugging output
 223  * we want to see. Each driver has its own method for enabling debugging and
 224  * modifying debug level states -- but this is typically done through a
 225  * module parameter 'debug' along with a respective 'debug' debugfs file
 226  * entry.
 227  */
 228 enum ATH_DEBUG {
 229         ATH_DBG_RESET           = 0x00000001,
 230         ATH_DBG_QUEUE           = 0x00000002,
 231         ATH_DBG_EEPROM          = 0x00000004,
 232         ATH_DBG_CALIBRATE       = 0x00000008,
 233         ATH_DBG_INTERRUPT       = 0x00000010,
 234         ATH_DBG_REGULATORY      = 0x00000020,
 235         ATH_DBG_ANI             = 0x00000040,
 236         ATH_DBG_XMIT            = 0x00000080,
 237         ATH_DBG_BEACON          = 0x00000100,
 238         ATH_DBG_CONFIG          = 0x00000200,
 239         ATH_DBG_FATAL           = 0x00000400,
 240         ATH_DBG_PS              = 0x00000800,
 241         ATH_DBG_HWTIMER         = 0x00001000,
 242         ATH_DBG_BTCOEX          = 0x00002000,
 243         ATH_DBG_WMI             = 0x00004000,
 244         ATH_DBG_BSTUCK          = 0x00008000,
 245         ATH_DBG_ANY             = 0xffffffff
 246 };
 247
 248 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
 249
 250 #ifdef CONFIG_ATH_DEBUG
 251
 252 #define ath_dbg(common, dbg_mask, fmt, ...)                     \
 253 ({                                                              \
 254         int rtn;                                                \
 255         if ((common)->debug_mask & dbg_mask)                    \
 256                 rtn = ath_printk(KERN_DEBUG, common, fmt,       \
 257                                  ##__VA_ARGS__);                \
 258         else                                                    \
 259                 rtn = 0;                                        \
 260                                                                 \
 261         rtn;                                                    \
 262 })
 263 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
 264 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
 265
 266 #else
 267
 268 static inline  __attribute__ ((format (printf, 3, 4))) int
 269 ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
 270         const char *fmt, ...)
 271 {
 272         return 0;
 273 }
 274 #define ATH_DBG_WARN(foo, arg...) do {} while (0)
 275 #define ATH_DBG_WARN_ON_ONCE(foo) ({                            \
 276         int __ret_warn_once = !!(foo);                          \
 277         unlikely(__ret_warn_once);                              \
 278 })
 279
 280 #endif /* CONFIG_ATH_DEBUG */
 281
 282 /** Returns string describing opmode, or NULL if unknown mode. */
 283 #ifdef CONFIG_ATH_DEBUG
 284 const char *ath_opmode_to_string(enum nl80211_iftype opmode);
 285 #else
 286 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
 287 {
 288         return "UNKNOWN";
 289 }
 290 #endif
 291
 292 #endif /* ATH_H */