drivers/net/wireless/ath/ath5k/desc.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 /******************************\
  21  Hardware Descriptor Functions
  22 \******************************/
  23
  24 #include "ath5k.h"
  25 #include "reg.h"
  26 #include "debug.h"
  27 #include "base.h"
  28
  29
  30 /************************\
  31 * TX Control descriptors *
  32 \************************/
  33
  34 /*
  35  * Initialize the 2-word tx control descriptor on 5210/5211
  36  */
  37 static int
  38 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
  39         unsigned int pkt_len, unsigned int hdr_len, int padsize,
  40         enum ath5k_pkt_type type,
  41         unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
  42         unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
  43         unsigned int rtscts_rate, unsigned int rtscts_duration)
  44 {
  45         u32 frame_type;
  46         struct ath5k_hw_2w_tx_ctl *tx_ctl;
  47         unsigned int frame_len;
  48
  49         tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
  50
  51         /*
  52          * Validate input
  53          * - Zero retries don't make sense.
  54          * - A zero rate will put the HW into a mode where it continously sends
  55          *   noise on the channel, so it is important to avoid this.
  56          */
  57         if (unlikely(tx_tries0 == 0)) {
  58                 ATH5K_ERR(ah->ah_sc, "zero retries\n");
  59                 WARN_ON(1);
  60                 return -EINVAL;
  61         }
  62         if (unlikely(tx_rate0 == 0)) {
  63                 ATH5K_ERR(ah->ah_sc, "zero rate\n");
  64                 WARN_ON(1);
  65                 return -EINVAL;
  66         }
  67
  68         /* Clear descriptor */
  69         memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
  70
  71         /* Setup control descriptor */
  72
  73         /* Verify and set frame length */
  74
  75         /* remove padding we might have added before */
  76         frame_len = pkt_len - padsize + FCS_LEN;
  77
  78         if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
  79                 return -EINVAL;
  80
  81         tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
  82
  83         /* Verify and set buffer length */
  84
  85         /* NB: beacon's BufLen must be a multiple of 4 bytes */
  86         if (type == AR5K_PKT_TYPE_BEACON)
  87                 pkt_len = roundup(pkt_len, 4);
  88
  89         if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
  90                 return -EINVAL;
  91
  92         tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
  93
  94         /*
  95          * Verify and set header length (only 5210)
  96          */
  97         if (ah->ah_version == AR5K_AR5210) {
  98                 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210)
  99                         return -EINVAL;
 100                 tx_ctl->tx_control_0 |=
 101                         AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210);
 102         }
 103
 104         /*Differences between 5210-5211*/
 105         if (ah->ah_version == AR5K_AR5210) {
 106                 switch (type) {
 107                 case AR5K_PKT_TYPE_BEACON:
 108                 case AR5K_PKT_TYPE_PROBE_RESP:
 109                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
 110                 case AR5K_PKT_TYPE_PIFS:
 111                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
 112                 default:
 113                         frame_type = type;
 114                 }
 115
 116                 tx_ctl->tx_control_0 |=
 117                 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210) |
 118                 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
 119
 120         } else {
 121                 tx_ctl->tx_control_0 |=
 122                         AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
 123                         AR5K_REG_SM(antenna_mode,
 124                                 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
 125                 tx_ctl->tx_control_1 |=
 126                         AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211);
 127         }
 128
 129 #define _TX_FLAGS(_c, _flag)                                    \
 130         if (flags & AR5K_TXDESC_##_flag) {                      \
 131                 tx_ctl->tx_control_##_c |=                      \
 132                         AR5K_2W_TX_DESC_CTL##_c##_##_flag;      \
 133         }
 134 #define _TX_FLAGS_5211(_c, _flag)                                       \
 135         if (flags & AR5K_TXDESC_##_flag) {                              \
 136                 tx_ctl->tx_control_##_c |=                              \
 137                         AR5K_2W_TX_DESC_CTL##_c##_##_flag##_5211;       \
 138         }
 139         _TX_FLAGS(0, CLRDMASK);
 140         _TX_FLAGS(0, INTREQ);
 141         _TX_FLAGS(0, RTSENA);
 142
 143         if (ah->ah_version == AR5K_AR5211) {
 144                 _TX_FLAGS_5211(0, VEOL);
 145                 _TX_FLAGS_5211(1, NOACK);
 146         }
 147
 148 #undef _TX_FLAGS
 149 #undef _TX_FLAGS_5211
 150
 151         /*
 152          * WEP crap
 153          */
 154         if (key_index != AR5K_TXKEYIX_INVALID) {
 155                 tx_ctl->tx_control_0 |=
 156                         AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
 157                 tx_ctl->tx_control_1 |=
 158                         AR5K_REG_SM(key_index,
 159                         AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX);
 160         }
 161
 162         /*
 163          * RTS/CTS Duration [5210 ?]
 164          */
 165         if ((ah->ah_version == AR5K_AR5210) &&
 166                         (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
 167                 tx_ctl->tx_control_1 |= rtscts_duration &
 168                                 AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210;
 169
 170         return 0;
 171 }
 172
 173 /*
 174  * Initialize the 4-word tx control descriptor on 5212
 175  */
 176 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
 177         struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
 178         int padsize,
 179         enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
 180         unsigned int tx_tries0, unsigned int key_index,
 181         unsigned int antenna_mode, unsigned int flags,
 182         unsigned int rtscts_rate,
 183         unsigned int rtscts_duration)
 184 {
 185         struct ath5k_hw_4w_tx_ctl *tx_ctl;
 186         unsigned int frame_len;
 187
 188         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
 189
 190         /*
 191          * Validate input
 192          * - Zero retries don't make sense.
 193          * - A zero rate will put the HW into a mode where it continously sends
 194          *   noise on the channel, so it is important to avoid this.
 195          */
 196         if (unlikely(tx_tries0 == 0)) {
 197                 ATH5K_ERR(ah->ah_sc, "zero retries\n");
 198                 WARN_ON(1);
 199                 return -EINVAL;
 200         }
 201         if (unlikely(tx_rate0 == 0)) {
 202                 ATH5K_ERR(ah->ah_sc, "zero rate\n");
 203                 WARN_ON(1);
 204                 return -EINVAL;
 205         }
 206
 207         tx_power += ah->ah_txpower.txp_offset;
 208         if (tx_power > AR5K_TUNE_MAX_TXPOWER)
 209                 tx_power = AR5K_TUNE_MAX_TXPOWER;
 210
 211         /* Clear descriptor */
 212         memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
 213
 214         /* Setup control descriptor */
 215
 216         /* Verify and set frame length */
 217
 218         /* remove padding we might have added before */
 219         frame_len = pkt_len - padsize + FCS_LEN;
 220
 221         if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
 222                 return -EINVAL;
 223
 224         tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
 225
 226         /* Verify and set buffer length */
 227
 228         /* NB: beacon's BufLen must be a multiple of 4 bytes */
 229         if (type == AR5K_PKT_TYPE_BEACON)
 230                 pkt_len = roundup(pkt_len, 4);
 231
 232         if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
 233                 return -EINVAL;
 234
 235         tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
 236
 237         tx_ctl->tx_control_0 |=
 238                 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
 239                 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
 240         tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
 241                                         AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
 242         tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
 243                                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
 244         tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
 245
 246 #define _TX_FLAGS(_c, _flag)                                    \
 247         if (flags & AR5K_TXDESC_##_flag) {                      \
 248                 tx_ctl->tx_control_##_c |=                      \
 249                         AR5K_4W_TX_DESC_CTL##_c##_##_flag;      \
 250         }
 251
 252         _TX_FLAGS(0, CLRDMASK);
 253         _TX_FLAGS(0, VEOL);
 254         _TX_FLAGS(0, INTREQ);
 255         _TX_FLAGS(0, RTSENA);
 256         _TX_FLAGS(0, CTSENA);
 257         _TX_FLAGS(1, NOACK);
 258
 259 #undef _TX_FLAGS
 260
 261         /*
 262          * WEP crap
 263          */
 264         if (key_index != AR5K_TXKEYIX_INVALID) {
 265                 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
 266                 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
 267                                 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX);
 268         }
 269
 270         /*
 271          * RTS/CTS
 272          */
 273         if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
 274                 if ((flags & AR5K_TXDESC_RTSENA) &&
 275                                 (flags & AR5K_TXDESC_CTSENA))
 276                         return -EINVAL;
 277                 tx_ctl->tx_control_2 |= rtscts_duration &
 278                                 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
 279                 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
 280                                 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
 281         }
 282
 283         return 0;
 284 }
 285
 286 /*
 287  * Initialize a 4-word multi rate retry tx control descriptor on 5212
 288  */
 289 int
 290 ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
 291         unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
 292         u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
 293 {
 294         struct ath5k_hw_4w_tx_ctl *tx_ctl;
 295
 296         /* no mrr support for cards older than 5212 */
 297         if (ah->ah_version < AR5K_AR5212)
 298                 return 0;
 299
 300         /*
 301          * Rates can be 0 as long as the retry count is 0 too.
 302          * A zero rate and nonzero retry count will put the HW into a mode where
 303          * it continously sends noise on the channel, so it is important to
 304          * avoid this.
 305          */
 306         if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
 307                      (tx_rate2 == 0 && tx_tries2 != 0) ||
 308                      (tx_rate3 == 0 && tx_tries3 != 0))) {
 309                 ATH5K_ERR(ah->ah_sc, "zero rate\n");
 310                 WARN_ON(1);
 311                 return -EINVAL;
 312         }
 313
 314         if (ah->ah_version == AR5K_AR5212) {
 315                 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
 316
 317 #define _XTX_TRIES(_n)                                                  \
 318         if (tx_tries##_n) {                                             \
 319                 tx_ctl->tx_control_2 |=                                 \
 320                     AR5K_REG_SM(tx_tries##_n,                           \
 321                     AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n);               \
 322                 tx_ctl->tx_control_3 |=                                 \
 323                     AR5K_REG_SM(tx_rate##_n,                            \
 324                     AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n);                \
 325         }
 326
 327                 _XTX_TRIES(1);
 328                 _XTX_TRIES(2);
 329                 _XTX_TRIES(3);
 330
 331 #undef _XTX_TRIES
 332
 333                 return 1;
 334         }
 335
 336         return 0;
 337 }
 338
 339
 340 /***********************\
 341 * TX Status descriptors *
 342 \***********************/
 343
 344 /*
 345  * Proccess the tx status descriptor on 5210/5211
 346  */
 347 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
 348                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
 349 {
 350         struct ath5k_hw_2w_tx_ctl *tx_ctl;
 351         struct ath5k_hw_tx_status *tx_status;
 352
 353         tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
 354         tx_status = &desc->ud.ds_tx5210.tx_stat;
 355
 356         /* No frame has been send or error */
 357         if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
 358                 return -EINPROGRESS;
 359
 360         /*
 361          * Get descriptor status
 362          */
 363         ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
 364                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
 365         ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
 366                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
 367         ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
 368                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
 369         /*TODO: ts->ts_virtcol + test*/
 370         ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
 371                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
 372         ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
 373                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
 374         ts->ts_antenna = 1;
 375         ts->ts_status = 0;
 376         ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
 377                 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
 378         ts->ts_retry[0] = ts->ts_longretry;
 379         ts->ts_final_idx = 0;
 380
 381         if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
 382                 if (tx_status->tx_status_0 &
 383                                 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 384                         ts->ts_status |= AR5K_TXERR_XRETRY;
 385
 386                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
 387                         ts->ts_status |= AR5K_TXERR_FIFO;
 388
 389                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
 390                         ts->ts_status |= AR5K_TXERR_FILT;
 391         }
 392
 393         return 0;
 394 }
 395
 396 /*
 397  * Proccess a tx status descriptor on 5212
 398  */
 399 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
 400                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
 401 {
 402         struct ath5k_hw_4w_tx_ctl *tx_ctl;
 403         struct ath5k_hw_tx_status *tx_status;
 404
 405         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
 406         tx_status = &desc->ud.ds_tx5212.tx_stat;
 407
 408         /* No frame has been send or error */
 409         if (unlikely(!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)))
 410                 return -EINPROGRESS;
 411
 412         /*
 413          * Get descriptor status
 414          */
 415         ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
 416                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
 417         ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
 418                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
 419         ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
 420                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
 421         ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
 422                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
 423         ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
 424                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
 425         ts->ts_antenna = (tx_status->tx_status_1 &
 426                 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212) ? 2 : 1;
 427         ts->ts_status = 0;
 428
 429         ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
 430                         AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212);
 431
 432         /* The longretry counter has the number of un-acked retries
 433          * for the final rate. To get the total number of retries
 434          * we have to add the retry counters for the other rates
 435          * as well
 436          */
 437         ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
 438         switch (ts->ts_final_idx) {
 439         case 3:
 440                 ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
 441                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
 442
 443                 ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
 444                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
 445                 ts->ts_longretry += ts->ts_retry[2];
 446                 /* fall through */
 447         case 2:
 448                 ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
 449                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
 450
 451                 ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
 452                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
 453                 ts->ts_longretry += ts->ts_retry[1];
 454                 /* fall through */
 455         case 1:
 456                 ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
 457                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
 458
 459                 ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
 460                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
 461                 ts->ts_longretry += ts->ts_retry[0];
 462                 /* fall through */
 463         case 0:
 464                 ts->ts_rate[0] = tx_ctl->tx_control_3 &
 465                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
 466                 break;
 467         }
 468
 469         /* TX error */
 470         if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
 471                 if (tx_status->tx_status_0 &
 472                                 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 473                         ts->ts_status |= AR5K_TXERR_XRETRY;
 474
 475                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
 476                         ts->ts_status |= AR5K_TXERR_FIFO;
 477
 478                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
 479                         ts->ts_status |= AR5K_TXERR_FILT;
 480         }
 481
 482         return 0;
 483 }
 484
 485
 486 /****************\
 487 * RX Descriptors *
 488 \****************/
 489
 490 /*
 491  * Initialize an rx control descriptor
 492  */
 493 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
 494                            u32 size, unsigned int flags)
 495 {
 496         struct ath5k_hw_rx_ctl *rx_ctl;
 497
 498         rx_ctl = &desc->ud.ds_rx.rx_ctl;
 499
 500         /*
 501          * Clear the descriptor
 502          * If we don't clean the status descriptor,
 503          * while scanning we get too many results,
 504          * most of them virtual, after some secs
 505          * of scanning system hangs. M.F.
 506         */
 507         memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
 508
 509         if (unlikely(size & ~AR5K_DESC_RX_CTL1_BUF_LEN))
 510                 return -EINVAL;
 511
 512         /* Setup descriptor */
 513         rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
 514
 515         if (flags & AR5K_RXDESC_INTREQ)
 516                 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
 517
 518         return 0;
 519 }
 520
 521 /*
 522  * Proccess the rx status descriptor on 5210/5211
 523  */
 524 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
 525                 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
 526 {
 527         struct ath5k_hw_rx_status *rx_status;
 528
 529         rx_status = &desc->ud.ds_rx.rx_stat;
 530
 531         /* No frame received / not ready */
 532         if (unlikely(!(rx_status->rx_status_1 &
 533                         AR5K_5210_RX_DESC_STATUS1_DONE)))
 534                 return -EINPROGRESS;
 535
 536         memset(rs, 0, sizeof(struct ath5k_rx_status));
 537
 538         /*
 539          * Frame receive status
 540          */
 541         rs->rs_datalen = rx_status->rx_status_0 &
 542                 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
 543         rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
 544                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
 545         rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
 546                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
 547         rs->rs_more = !!(rx_status->rx_status_0 &
 548                 AR5K_5210_RX_DESC_STATUS0_MORE);
 549         /* TODO: this timestamp is 13 bit, later on we assume 15 bit!
 550          * also the HAL code for 5210 says the timestamp is bits [10..22] of the
 551          * TSF, and extends the timestamp here to 15 bit.
 552          * we need to check on 5210...
 553          */
 554         rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
 555                 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 556
 557         if (ah->ah_version == AR5K_AR5211)
 558                 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
 559                                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211);
 560         else
 561                 rs->rs_antenna = (rx_status->rx_status_0 &
 562                                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210)
 563                                 ? 2 : 1;
 564
 565         /*
 566          * Key table status
 567          */
 568         if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
 569                 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
 570                         AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
 571         else
 572                 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
 573
 574         /*
 575          * Receive/descriptor errors
 576          */
 577         if (!(rx_status->rx_status_1 &
 578                         AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
 579                 if (rx_status->rx_status_1 &
 580                                 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
 581                         rs->rs_status |= AR5K_RXERR_CRC;
 582
 583                 /* only on 5210 */
 584                 if ((ah->ah_version == AR5K_AR5210) &&
 585                     (rx_status->rx_status_1 &
 586                                 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210))
 587                         rs->rs_status |= AR5K_RXERR_FIFO;
 588
 589                 if (rx_status->rx_status_1 &
 590                                 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
 591                         rs->rs_status |= AR5K_RXERR_PHY;
 592                         rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
 593                                 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
 594                 }
 595
 596                 if (rx_status->rx_status_1 &
 597                                 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
 598                         rs->rs_status |= AR5K_RXERR_DECRYPT;
 599         }
 600
 601         return 0;
 602 }
 603
 604 /*
 605  * Proccess the rx status descriptor on 5212
 606  */
 607 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
 608                                         struct ath5k_desc *desc,
 609                                         struct ath5k_rx_status *rs)
 610 {
 611         struct ath5k_hw_rx_status *rx_status;
 612
 613         rx_status = &desc->ud.ds_rx.rx_stat;
 614
 615         /* No frame received / not ready */
 616         if (unlikely(!(rx_status->rx_status_1 &
 617                                 AR5K_5212_RX_DESC_STATUS1_DONE)))
 618                 return -EINPROGRESS;
 619
 620         memset(rs, 0, sizeof(struct ath5k_rx_status));
 621
 622         /*
 623          * Frame receive status
 624          */
 625         rs->rs_datalen = rx_status->rx_status_0 &
 626                 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
 627         rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
 628                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
 629         rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
 630                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
 631         rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
 632                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
 633         rs->rs_more = !!(rx_status->rx_status_0 &
 634                 AR5K_5212_RX_DESC_STATUS0_MORE);
 635         rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
 636                 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 637
 638         /*
 639          * Key table status
 640          */
 641         if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
 642                 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
 643                                            AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
 644         else
 645                 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
 646
 647         /*
 648          * Receive/descriptor errors
 649          */
 650         if (!(rx_status->rx_status_1 &
 651             AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
 652                 if (rx_status->rx_status_1 &
 653                                 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
 654                         rs->rs_status |= AR5K_RXERR_CRC;
 655
 656                 if (rx_status->rx_status_1 &
 657                                 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
 658                         rs->rs_status |= AR5K_RXERR_PHY;
 659                         rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
 660                                 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE);
 661                         if (!ah->ah_capabilities.cap_has_phyerr_counters)
 662                                 ath5k_ani_phy_error_report(ah, rs->rs_phyerr);
 663                 }
 664
 665                 if (rx_status->rx_status_1 &
 666                                 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
 667                         rs->rs_status |= AR5K_RXERR_DECRYPT;
 668
 669                 if (rx_status->rx_status_1 &
 670                                 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
 671                         rs->rs_status |= AR5K_RXERR_MIC;
 672         }
 673         return 0;
 674 }
 675
 676
 677 /********\
 678 * Attach *
 679 \********/
 680
 681 /*
 682  * Init function pointers inside ath5k_hw struct
 683  */
 684 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
 685 {
 686         if (ah->ah_version == AR5K_AR5212) {
 687                 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
 688                 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
 689                 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
 690         } else if (ah->ah_version <= AR5K_AR5211) {
 691                 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
 692                 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
 693                 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
 694         } else
 695                 return -ENOTSUPP;
 696         return 0;
 697 }