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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / wireless / ath / ath9k / ath9k.h
blob3681caf54282bdae2e1f64e46f8d6335fd2fe6c6
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/leds.h>
23 #include <linux/completion.h>
24 #include <linux/pm_qos_params.h>
25
26 #include "debug.h"
27 #include "common.h"
28
29 /*
30 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
31 * should rely on this file or its contents.
32 */
33
34 struct ath_node;
35
36 /* Macro to expand scalars to 64-bit objects */
37
38 #define ito64(x) (sizeof(x) == 1) ? \
39 (((unsigned long long int)(x)) & (0xff)) : \
40 (sizeof(x) == 2) ? \
41 (((unsigned long long int)(x)) & 0xffff) : \
42 ((sizeof(x) == 4) ? \
43 (((unsigned long long int)(x)) & 0xffffffff) : \
44 (unsigned long long int)(x))
45
46 /* increment with wrap-around */
47 #define INCR(_l, _sz) do { \
48 (_l)++; \
49 (_l) &= ((_sz) - 1); \
50 } while (0)
51
52 /* decrement with wrap-around */
53 #define DECR(_l, _sz) do { \
54 (_l)--; \
55 (_l) &= ((_sz) - 1); \
56 } while (0)
57
58 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
59
60 #define ATH9K_PM_QOS_DEFAULT_VALUE 55
61
62 #define TSF_TO_TU(_h,_l) \
63 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64
65 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
66
67 struct ath_config {
68 u32 ath_aggr_prot;
69 u16 txpowlimit;
70 u8 cabqReadytime;
71 };
72
73 /*************************/
74 /* Descriptor Management */
75 /*************************/
76
77 #define ATH_TXBUF_RESET(_bf) do { \
78 (_bf)->bf_stale = false; \
79 (_bf)->bf_lastbf = NULL; \
80 (_bf)->bf_next = NULL; \
81 memset(&((_bf)->bf_state), 0, \
82 sizeof(struct ath_buf_state)); \
83 } while (0)
84
85 #define ATH_RXBUF_RESET(_bf) do { \
86 (_bf)->bf_stale = false; \
87 } while (0)
88
89 /**
90 * enum buffer_type - Buffer type flags
91 *
92 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
93 * @BUF_AGGR: Indicates whether the buffer can be aggregated
94 * (used in aggregation scheduling)
95 * @BUF_XRETRY: To denote excessive retries of the buffer
96 */
97 enum buffer_type {
98 BUF_AMPDU = BIT(2),
99 BUF_AGGR = BIT(3),
100 BUF_XRETRY = BIT(5),
101 };
102
103 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
104 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
105 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
106
107 #define ATH_TXSTATUS_RING_SIZE 64
108
109 struct ath_descdma {
110 void *dd_desc;
111 dma_addr_t dd_desc_paddr;
112 u32 dd_desc_len;
113 struct ath_buf *dd_bufptr;
114 };
115
116 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
117 struct list_head *head, const char *name,
118 int nbuf, int ndesc, bool is_tx);
119 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
120 struct list_head *head);
121
122 /***********/
123 /* RX / TX */
124 /***********/
125
126 #define ATH_MAX_ANTENNA 3
127 #define ATH_RXBUF 512
128 #define ATH_TXBUF 512
129 #define ATH_TXBUF_RESERVE 5
130 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
131 #define ATH_TXMAXTRY 13
132 #define ATH_MGT_TXMAXTRY 4
133
134 #define TID_TO_WME_AC(_tid) \
135 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
136 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
137 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
138 WME_AC_VO)
139
140 #define ADDBA_EXCHANGE_ATTEMPTS 10
141 #define ATH_AGGR_DELIM_SZ 4
142 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
143 /* number of delimiters for encryption padding */
144 #define ATH_AGGR_ENCRYPTDELIM 10
145 /* minimum h/w qdepth to be sustained to maximize aggregation */
146 #define ATH_AGGR_MIN_QDEPTH 2
147 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
148
149 #define IEEE80211_SEQ_SEQ_SHIFT 4
150 #define IEEE80211_SEQ_MAX 4096
151 #define IEEE80211_WEP_IVLEN 3
152 #define IEEE80211_WEP_KIDLEN 1
153 #define IEEE80211_WEP_CRCLEN 4
154 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
155 (IEEE80211_WEP_IVLEN + \
156 IEEE80211_WEP_KIDLEN + \
157 IEEE80211_WEP_CRCLEN))
158
159 /* return whether a bit at index _n in bitmap _bm is set
160 * _sz is the size of the bitmap */
161 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
162 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
163
164 /* return block-ack bitmap index given sequence and starting sequence */
165 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
166
167 /* returns delimiter padding required given the packet length */
168 #define ATH_AGGR_GET_NDELIM(_len) \
169 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
170 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
171
172 #define BAW_WITHIN(_start, _bawsz, _seqno) \
173 ((((_seqno) - (_start)) & 4095) < (_bawsz))
174
175 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
176
177 #define ATH_TX_COMPLETE_POLL_INT 1000
178
179 enum ATH_AGGR_STATUS {
180 ATH_AGGR_DONE,
181 ATH_AGGR_BAW_CLOSED,
182 ATH_AGGR_LIMITED,
183 };
184
185 #define ATH_TXFIFO_DEPTH 8
186 struct ath_txq {
187 u32 axq_qnum;
188 u32 *axq_link;
189 struct list_head axq_q;
190 spinlock_t axq_lock;
191 u32 axq_depth;
192 u32 axq_ampdu_depth;
193 bool stopped;
194 bool axq_tx_inprogress;
195 struct list_head axq_acq;
196 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
197 struct list_head txq_fifo_pending;
198 u8 txq_headidx;
199 u8 txq_tailidx;
200 int pending_frames;
201 };
202
203 struct ath_atx_ac {
204 struct ath_txq *txq;
205 int sched;
206 struct list_head list;
207 struct list_head tid_q;
208 };
209
210 struct ath_frame_info {
211 int framelen;
212 u32 keyix;
213 enum ath9k_key_type keytype;
214 u8 retries;
215 u16 seqno;
216 };
217
218 struct ath_buf_state {
219 u8 bf_type;
220 u8 bfs_paprd;
221 enum ath9k_internal_frame_type bfs_ftype;
222 };
223
224 struct ath_buf {
225 struct list_head list;
226 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
227 an aggregate) */
228 struct ath_buf *bf_next; /* next subframe in the aggregate */
229 struct sk_buff *bf_mpdu; /* enclosing frame structure */
230 void *bf_desc; /* virtual addr of desc */
231 dma_addr_t bf_daddr; /* physical addr of desc */
232 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
233 bool bf_stale;
234 u16 bf_flags;
235 struct ath_buf_state bf_state;
236 struct ath_wiphy *aphy;
237 };
238
239 struct ath_atx_tid {
240 struct list_head list;
241 struct list_head buf_q;
242 struct ath_node *an;
243 struct ath_atx_ac *ac;
244 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
245 u16 seq_start;
246 u16 seq_next;
247 u16 baw_size;
248 int tidno;
249 int baw_head; /* first un-acked tx buffer */
250 int baw_tail; /* next unused tx buffer slot */
251 int sched;
252 int paused;
253 u8 state;
254 };
255
256 struct ath_node {
257 struct ath_common *common;
258 struct ath_atx_tid tid[WME_NUM_TID];
259 struct ath_atx_ac ac[WME_NUM_AC];
260 u16 maxampdu;
261 u8 mpdudensity;
262 };
263
264 #define AGGR_CLEANUP BIT(1)
265 #define AGGR_ADDBA_COMPLETE BIT(2)
266 #define AGGR_ADDBA_PROGRESS BIT(3)
267
268 struct ath_tx_control {
269 struct ath_txq *txq;
270 struct ath_node *an;
271 int if_id;
272 enum ath9k_internal_frame_type frame_type;
273 u8 paprd;
274 };
275
276 #define ATH_TX_ERROR 0x01
277 #define ATH_TX_XRETRY 0x02
278 #define ATH_TX_BAR 0x04
279
280 struct ath_tx {
281 u16 seq_no;
282 u32 txqsetup;
283 spinlock_t txbuflock;
284 struct list_head txbuf;
285 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
286 struct ath_descdma txdma;
287 struct ath_txq *txq_map[WME_NUM_AC];
288 };
289
290 struct ath_rx_edma {
291 struct sk_buff_head rx_fifo;
292 struct sk_buff_head rx_buffers;
293 u32 rx_fifo_hwsize;
294 };
295
296 struct ath_rx {
297 u8 defant;
298 u8 rxotherant;
299 u32 *rxlink;
300 unsigned int rxfilter;
301 spinlock_t rxbuflock;
302 struct list_head rxbuf;
303 struct ath_descdma rxdma;
304 struct ath_buf *rx_bufptr;
305 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
306 };
307
308 int ath_startrecv(struct ath_softc *sc);
309 bool ath_stoprecv(struct ath_softc *sc);
310 void ath_flushrecv(struct ath_softc *sc);
311 u32 ath_calcrxfilter(struct ath_softc *sc);
312 int ath_rx_init(struct ath_softc *sc, int nbufs);
313 void ath_rx_cleanup(struct ath_softc *sc);
314 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
315 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
316 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
317 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
318 void ath_draintxq(struct ath_softc *sc,
319 struct ath_txq *txq, bool retry_tx);
320 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
321 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
322 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
323 int ath_tx_init(struct ath_softc *sc, int nbufs);
324 void ath_tx_cleanup(struct ath_softc *sc);
325 int ath_txq_update(struct ath_softc *sc, int qnum,
326 struct ath9k_tx_queue_info *q);
327 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
328 struct ath_tx_control *txctl);
329 void ath_tx_tasklet(struct ath_softc *sc);
330 void ath_tx_edma_tasklet(struct ath_softc *sc);
331 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
332 u16 tid, u16 *ssn);
333 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
334 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
335
336 /********/
337 /* VIFs */
338 /********/
339
340 struct ath_vif {
341 int av_bslot;
342 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
343 enum nl80211_iftype av_opmode;
344 struct ath_buf *av_bcbuf;
345 struct ath_tx_control av_btxctl;
346 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
347 };
348
349 /*******************/
350 /* Beacon Handling */
351 /*******************/
352
353 /*
354 * Regardless of the number of beacons we stagger, (i.e. regardless of the
355 * number of BSSIDs) if a given beacon does not go out even after waiting this
356 * number of beacon intervals, the game's up.
357 */
358 #define BSTUCK_THRESH (9 * ATH_BCBUF)
359 #define ATH_BCBUF 4
360 #define ATH_DEFAULT_BINTVAL 100 /* TU */
361 #define ATH_DEFAULT_BMISS_LIMIT 10
362 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
363
364 struct ath_beacon_config {
365 u16 beacon_interval;
366 u16 listen_interval;
367 u16 dtim_period;
368 u16 bmiss_timeout;
369 u8 dtim_count;
370 };
371
372 struct ath_beacon {
373 enum {
374 OK, /* no change needed */
375 UPDATE, /* update pending */
376 COMMIT /* beacon sent, commit change */
377 } updateslot; /* slot time update fsm */
378
379 u32 beaconq;
380 u32 bmisscnt;
381 u32 ast_be_xmit;
382 u64 bc_tstamp;
383 struct ieee80211_vif *bslot[ATH_BCBUF];
384 struct ath_wiphy *bslot_aphy[ATH_BCBUF];
385 int slottime;
386 int slotupdate;
387 struct ath9k_tx_queue_info beacon_qi;
388 struct ath_descdma bdma;
389 struct ath_txq *cabq;
390 struct list_head bbuf;
391 };
392
393 void ath_beacon_tasklet(unsigned long data);
394 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
395 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
396 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
397 int ath_beaconq_config(struct ath_softc *sc);
398
399 /*******/
400 /* ANI */
401 /*******/
402
403 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
404 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
405 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
406 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
407 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
408 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
409 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
410
411 #define ATH_PAPRD_TIMEOUT 100 /* msecs */
412
413 void ath_hw_check(struct work_struct *work);
414 void ath_paprd_calibrate(struct work_struct *work);
415 void ath_ani_calibrate(unsigned long data);
416
417 /**********/
418 /* BTCOEX */
419 /**********/
420
421 struct ath_btcoex {
422 bool hw_timer_enabled;
423 spinlock_t btcoex_lock;
424 struct timer_list period_timer; /* Timer for BT period */
425 u32 bt_priority_cnt;
426 unsigned long bt_priority_time;
427 int bt_stomp_type; /* Types of BT stomping */
428 u32 btcoex_no_stomp; /* in usec */
429 u32 btcoex_period; /* in usec */
430 u32 btscan_no_stomp; /* in usec */
431 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
432 };
433
434 int ath_init_btcoex_timer(struct ath_softc *sc);
435 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
436 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
437
438 /********************/
439 /* LED Control */
440 /********************/
441
442 #define ATH_LED_PIN_DEF 1
443 #define ATH_LED_PIN_9287 8
444 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
445 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
446
447 enum ath_led_type {
448 ATH_LED_RADIO,
449 ATH_LED_ASSOC,
450 ATH_LED_TX,
451 ATH_LED_RX
452 };
453
454 struct ath_led {
455 struct ath_softc *sc;
456 struct led_classdev led_cdev;
457 enum ath_led_type led_type;
458 char name[32];
459 bool registered;
460 };
461
462 void ath_init_leds(struct ath_softc *sc);
463 void ath_deinit_leds(struct ath_softc *sc);
464
465 /* Antenna diversity/combining */
466 #define ATH_ANT_RX_CURRENT_SHIFT 4
467 #define ATH_ANT_RX_MAIN_SHIFT 2
468 #define ATH_ANT_RX_MASK 0x3
469
470 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
471 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
472 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
473 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
474 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
475 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
476 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
477
478 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
479 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
480 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
481 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
482 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
483
484 enum ath9k_ant_div_comb_lna_conf {
485 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
486 ATH_ANT_DIV_COMB_LNA2,
487 ATH_ANT_DIV_COMB_LNA1,
488 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
489 };
490
491 struct ath_ant_comb {
492 u16 count;
493 u16 total_pkt_count;
494 bool scan;
495 bool scan_not_start;
496 int main_total_rssi;
497 int alt_total_rssi;
498 int alt_recv_cnt;
499 int main_recv_cnt;
500 int rssi_lna1;
501 int rssi_lna2;
502 int rssi_add;
503 int rssi_sub;
504 int rssi_first;
505 int rssi_second;
506 int rssi_third;
507 bool alt_good;
508 int quick_scan_cnt;
509 int main_conf;
510 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
511 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
512 int first_bias;
513 int second_bias;
514 bool first_ratio;
515 bool second_ratio;
516 unsigned long scan_start_time;
517 };
518
519 /********************/
520 /* Main driver core */
521 /********************/
522
523 /*
524 * Default cache line size, in bytes.
525 * Used when PCI device not fully initialized by bootrom/BIOS
526 */
527 #define DEFAULT_CACHELINE 32
528 #define ATH_REGCLASSIDS_MAX 10
529 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
530 #define ATH_MAX_SW_RETRIES 10
531 #define ATH_CHAN_MAX 255
532 #define IEEE80211_WEP_NKID 4 /* number of key ids */
533
534 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
535 #define ATH_RATE_DUMMY_MARKER 0
536
537 #define SC_OP_INVALID BIT(0)
538 #define SC_OP_BEACONS BIT(1)
539 #define SC_OP_RXAGGR BIT(2)
540 #define SC_OP_TXAGGR BIT(3)
541 #define SC_OP_OFFCHANNEL BIT(4)
542 #define SC_OP_PREAMBLE_SHORT BIT(5)
543 #define SC_OP_PROTECT_ENABLE BIT(6)
544 #define SC_OP_RXFLUSH BIT(7)
545 #define SC_OP_LED_ASSOCIATED BIT(8)
546 #define SC_OP_LED_ON BIT(9)
547 #define SC_OP_TSF_RESET BIT(11)
548 #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
549 #define SC_OP_BT_SCAN BIT(13)
550 #define SC_OP_ANI_RUN BIT(14)
551 #define SC_OP_ENABLE_APM BIT(15)
552
553 /* Powersave flags */
554 #define PS_WAIT_FOR_BEACON BIT(0)
555 #define PS_WAIT_FOR_CAB BIT(1)
556 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
557 #define PS_WAIT_FOR_TX_ACK BIT(3)
558 #define PS_BEACON_SYNC BIT(4)
559
560 struct ath_wiphy;
561 struct ath_rate_table;
562
563 struct ath_softc {
564 struct ieee80211_hw *hw;
565 struct device *dev;
566
567 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
568 struct ath_wiphy *pri_wiphy;
569 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
570 * have NULL entries */
571 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
572 int chan_idx;
573 int chan_is_ht;
574 struct ath_wiphy *next_wiphy;
575 struct work_struct chan_work;
576 int wiphy_select_failures;
577 unsigned long wiphy_select_first_fail;
578 struct delayed_work wiphy_work;
579 unsigned long wiphy_scheduler_int;
580 int wiphy_scheduler_index;
581 struct survey_info *cur_survey;
582 struct survey_info survey[ATH9K_NUM_CHANNELS];
583
584 struct tasklet_struct intr_tq;
585 struct tasklet_struct bcon_tasklet;
586 struct ath_hw *sc_ah;
587 void __iomem *mem;
588 int irq;
589 spinlock_t sc_serial_rw;
590 spinlock_t sc_pm_lock;
591 spinlock_t sc_pcu_lock;
592 struct mutex mutex;
593 struct work_struct paprd_work;
594 struct work_struct hw_check_work;
595 struct completion paprd_complete;
596 bool paprd_pending;
597
598 u32 intrstatus;
599 u32 sc_flags; /* SC_OP_* */
600 u16 ps_flags; /* PS_* */
601 u16 curtxpow;
602 u8 nbcnvifs;
603 u16 nvifs;
604 bool ps_enabled;
605 bool ps_idle;
606 unsigned long ps_usecount;
607
608 struct ath_config config;
609 struct ath_rx rx;
610 struct ath_tx tx;
611 struct ath_beacon beacon;
612 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
613
614 struct ath_led radio_led;
615 struct ath_led assoc_led;
616 struct ath_led tx_led;
617 struct ath_led rx_led;
618 struct delayed_work ath_led_blink_work;
619 int led_on_duration;
620 int led_off_duration;
621 int led_on_cnt;
622 int led_off_cnt;
623
624 int beacon_interval;
625
626 #ifdef CONFIG_ATH9K_DEBUGFS
627 struct ath9k_debug debug;
628 #endif
629 struct ath_beacon_config cur_beacon_conf;
630 struct delayed_work tx_complete_work;
631 struct ath_btcoex btcoex;
632
633 struct ath_descdma txsdma;
634
635 struct ath_ant_comb ant_comb;
636
637 struct pm_qos_request_list pm_qos_req;
638 };
639
640 struct ath_wiphy {
641 struct ath_softc *sc; /* shared for all virtual wiphys */
642 struct ieee80211_hw *hw;
643 struct ath9k_hw_cal_data caldata;
644 enum ath_wiphy_state {
645 ATH_WIPHY_INACTIVE,
646 ATH_WIPHY_ACTIVE,
647 ATH_WIPHY_PAUSING,
648 ATH_WIPHY_PAUSED,
649 ATH_WIPHY_SCAN,
650 } state;
651 bool idle;
652 int chan_idx;
653 int chan_is_ht;
654 int last_rssi;
655 };
656
657 void ath9k_tasklet(unsigned long data);
658 int ath_reset(struct ath_softc *sc, bool retry_tx);
659 int ath_cabq_update(struct ath_softc *);
660
661 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
662 {
663 common->bus_ops->read_cachesize(common, csz);
664 }
665
666 extern struct ieee80211_ops ath9k_ops;
667 extern int ath9k_modparam_nohwcrypt;
668 extern int led_blink;
669 extern int ath9k_pm_qos_value;
670 extern bool is_ath9k_unloaded;
671
672 irqreturn_t ath_isr(int irq, void *dev);
673 void ath9k_init_crypto(struct ath_softc *sc);
674 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
675 const struct ath_bus_ops *bus_ops);
676 void ath9k_deinit_device(struct ath_softc *sc);
677 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
678 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
679 struct ath9k_channel *ichan);
680 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
681 struct ath9k_channel *hchan);
682
683 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
684 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
685 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
686
687 #ifdef CONFIG_PCI
688 int ath_pci_init(void);
689 void ath_pci_exit(void);
690 #else
691 static inline int ath_pci_init(void) { return 0; };
692 static inline void ath_pci_exit(void) {};
693 #endif
694
695 #ifdef CONFIG_ATHEROS_AR71XX
696 int ath_ahb_init(void);
697 void ath_ahb_exit(void);
698 #else
699 static inline int ath_ahb_init(void) { return 0; };
700 static inline void ath_ahb_exit(void) {};
701 #endif
702
703 void ath9k_ps_wakeup(struct ath_softc *sc);
704 void ath9k_ps_restore(struct ath_softc *sc);
705
706 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
707
708 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
709 int ath9k_wiphy_add(struct ath_softc *sc);
710 int ath9k_wiphy_del(struct ath_wiphy *aphy);
711 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
712 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
713 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
714 int ath9k_wiphy_select(struct ath_wiphy *aphy);
715 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
716 void ath9k_wiphy_chan_work(struct work_struct *work);
717 bool ath9k_wiphy_started(struct ath_softc *sc);
718 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
719 struct ath_wiphy *selected);
720 bool ath9k_wiphy_scanning(struct ath_softc *sc);
721 void ath9k_wiphy_work(struct work_struct *work);
722 bool ath9k_all_wiphys_idle(struct ath_softc *sc);
723 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
724
725 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
726 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
727
728 void ath_start_rfkill_poll(struct ath_softc *sc);
729 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
730
731 #endif /* ATH9K_H */
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