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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / wireless / ath / ath9k / hw.h
blob5a3dfec45e96004d02c84a33cbb39ff9aa201d45
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33
34 #define ATHEROS_VENDOR_ID 0x168c
35
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9485_PCIE 0x0032
47
48 #define AR5416_AR9100_DEVID 0x000b
49
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
53
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
60 #define ATH_DEFAULT_NOISE_FLOOR -95
61
62 #define ATH9K_RSSI_BAD -128
63
64 #define ATH9K_NUM_CHANNELS 38
65
66 /* Register read/write primitives */
67 #define REG_WRITE(_ah, _reg, _val) \
68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
69
70 #define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
72
73 #define ENABLE_REGWRITE_BUFFER(_ah) \
74 do { \
75 if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
76 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
77 } while (0)
78
79 #define REGWRITE_BUFFER_FLUSH(_ah) \
80 do { \
81 if (ath9k_hw_common(_ah)->ops->write_flush) \
82 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
83 } while (0)
84
85 #define SM(_v, _f) (((_v) << _f##_S) & _f)
86 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
87 #define REG_RMW(_a, _r, _set, _clr) \
88 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
89 #define REG_RMW_FIELD(_a, _r, _f, _v) \
90 REG_WRITE(_a, _r, \
91 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
92 #define REG_READ_FIELD(_a, _r, _f) \
93 (((REG_READ(_a, _r) & _f) >> _f##_S))
94 #define REG_SET_BIT(_a, _r, _f) \
95 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
96 #define REG_CLR_BIT(_a, _r, _f) \
97 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
98
99 #define DO_DELAY(x) do { \
100 if ((++(x) % 64) == 0) \
101 udelay(1); \
102 } while (0)
103
104 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
105 int r; \
106 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
107 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
108 INI_RA((iniarray), r, (column))); \
109 DO_DELAY(regWr); \
110 } \
111 } while (0)
112
113 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
114 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
115 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
116 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
117 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
118 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
119 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
120
121 #define AR_GPIOD_MASK 0x00001FFF
122 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
123
124 #define BASE_ACTIVATE_DELAY 100
125 #define RTC_PLL_SETTLE_DELAY 100
126 #define COEF_SCALE_S 24
127 #define HT40_CHANNEL_CENTER_SHIFT 10
128
129 #define ATH9K_ANTENNA0_CHAINMASK 0x1
130 #define ATH9K_ANTENNA1_CHAINMASK 0x2
131
132 #define ATH9K_NUM_DMA_DEBUG_REGS 8
133 #define ATH9K_NUM_QUEUES 10
134
135 #define MAX_RATE_POWER 63
136 #define AH_WAIT_TIMEOUT 100000 /* (us) */
137 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
138 #define AH_TIME_QUANTUM 10
139 #define AR_KEYTABLE_SIZE 128
140 #define POWER_UP_TIME 10000
141 #define SPUR_RSSI_THRESH 40
142
143 #define CAB_TIMEOUT_VAL 10
144 #define BEACON_TIMEOUT_VAL 10
145 #define MIN_BEACON_TIMEOUT_VAL 1
146 #define SLEEP_SLOP 3
147
148 #define INIT_CONFIG_STATUS 0x00000000
149 #define INIT_RSSI_THR 0x00000700
150 #define INIT_BCON_CNTRL_REG 0x00000000
151
152 #define TU_TO_USEC(_tu) ((_tu) << 10)
153
154 #define ATH9K_HW_RX_HP_QDEPTH 16
155 #define ATH9K_HW_RX_LP_QDEPTH 128
156
157 #define PAPRD_GAIN_TABLE_ENTRIES 32
158 #define PAPRD_TABLE_SZ 24
159
160 enum ath_hw_txq_subtype {
161 ATH_TXQ_AC_BE = 0,
162 ATH_TXQ_AC_BK = 1,
163 ATH_TXQ_AC_VI = 2,
164 ATH_TXQ_AC_VO = 3,
165 };
166
167 enum ath_ini_subsys {
168 ATH_INI_PRE = 0,
169 ATH_INI_CORE,
170 ATH_INI_POST,
171 ATH_INI_NUM_SPLIT,
172 };
173
174 enum ath9k_hw_caps {
175 ATH9K_HW_CAP_HT = BIT(0),
176 ATH9K_HW_CAP_RFSILENT = BIT(1),
177 ATH9K_HW_CAP_CST = BIT(2),
178 ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
179 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
180 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
181 ATH9K_HW_CAP_EDMA = BIT(6),
182 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
183 ATH9K_HW_CAP_LDPC = BIT(8),
184 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
185 ATH9K_HW_CAP_SGI_20 = BIT(10),
186 ATH9K_HW_CAP_PAPRD = BIT(11),
187 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
188 ATH9K_HW_CAP_2GHZ = BIT(13),
189 ATH9K_HW_CAP_5GHZ = BIT(14),
190 ATH9K_HW_CAP_APM = BIT(15),
191 };
192
193 struct ath9k_hw_capabilities {
194 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
195 u16 total_queues;
196 u16 keycache_size;
197 u16 low_5ghz_chan, high_5ghz_chan;
198 u16 low_2ghz_chan, high_2ghz_chan;
199 u16 rts_aggr_limit;
200 u8 tx_chainmask;
201 u8 rx_chainmask;
202 u8 max_txchains;
203 u8 max_rxchains;
204 u16 tx_triglevel_max;
205 u16 reg_cap;
206 u8 num_gpio_pins;
207 u8 rx_hp_qdepth;
208 u8 rx_lp_qdepth;
209 u8 rx_status_len;
210 u8 tx_desc_len;
211 u8 txs_len;
212 u16 pcie_lcr_offset;
213 bool pcie_lcr_extsync_en;
214 };
215
216 struct ath9k_ops_config {
217 int dma_beacon_response_time;
218 int sw_beacon_response_time;
219 int additional_swba_backoff;
220 int ack_6mb;
221 u32 cwm_ignore_extcca;
222 u8 pcie_powersave_enable;
223 bool pcieSerDesWrite;
224 u8 pcie_clock_req;
225 u32 pcie_waen;
226 u8 analog_shiftreg;
227 u8 ht_enable;
228 u32 ofdm_trig_low;
229 u32 ofdm_trig_high;
230 u32 cck_trig_high;
231 u32 cck_trig_low;
232 u32 enable_ani;
233 int serialize_regmode;
234 bool rx_intr_mitigation;
235 bool tx_intr_mitigation;
236 #define SPUR_DISABLE 0
237 #define SPUR_ENABLE_IOCTL 1
238 #define SPUR_ENABLE_EEPROM 2
239 #define AR_SPUR_5413_1 1640
240 #define AR_SPUR_5413_2 1200
241 #define AR_NO_SPUR 0x8000
242 #define AR_BASE_FREQ_2GHZ 2300
243 #define AR_BASE_FREQ_5GHZ 4900
244 #define AR_SPUR_FEEQ_BOUND_HT40 19
245 #define AR_SPUR_FEEQ_BOUND_HT20 10
246 int spurmode;
247 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
248 u8 max_txtrig_level;
249 u16 ani_poll_interval; /* ANI poll interval in ms */
250 };
251
252 enum ath9k_int {
253 ATH9K_INT_RX = 0x00000001,
254 ATH9K_INT_RXDESC = 0x00000002,
255 ATH9K_INT_RXHP = 0x00000001,
256 ATH9K_INT_RXLP = 0x00000002,
257 ATH9K_INT_RXNOFRM = 0x00000008,
258 ATH9K_INT_RXEOL = 0x00000010,
259 ATH9K_INT_RXORN = 0x00000020,
260 ATH9K_INT_TX = 0x00000040,
261 ATH9K_INT_TXDESC = 0x00000080,
262 ATH9K_INT_TIM_TIMER = 0x00000100,
263 ATH9K_INT_BB_WATCHDOG = 0x00000400,
264 ATH9K_INT_TXURN = 0x00000800,
265 ATH9K_INT_MIB = 0x00001000,
266 ATH9K_INT_RXPHY = 0x00004000,
267 ATH9K_INT_RXKCM = 0x00008000,
268 ATH9K_INT_SWBA = 0x00010000,
269 ATH9K_INT_BMISS = 0x00040000,
270 ATH9K_INT_BNR = 0x00100000,
271 ATH9K_INT_TIM = 0x00200000,
272 ATH9K_INT_DTIM = 0x00400000,
273 ATH9K_INT_DTIMSYNC = 0x00800000,
274 ATH9K_INT_GPIO = 0x01000000,
275 ATH9K_INT_CABEND = 0x02000000,
276 ATH9K_INT_TSFOOR = 0x04000000,
277 ATH9K_INT_GENTIMER = 0x08000000,
278 ATH9K_INT_CST = 0x10000000,
279 ATH9K_INT_GTT = 0x20000000,
280 ATH9K_INT_FATAL = 0x40000000,
281 ATH9K_INT_GLOBAL = 0x80000000,
282 ATH9K_INT_BMISC = ATH9K_INT_TIM |
283 ATH9K_INT_DTIM |
284 ATH9K_INT_DTIMSYNC |
285 ATH9K_INT_TSFOOR |
286 ATH9K_INT_CABEND,
287 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
288 ATH9K_INT_RXDESC |
289 ATH9K_INT_RXEOL |
290 ATH9K_INT_RXORN |
291 ATH9K_INT_TXURN |
292 ATH9K_INT_TXDESC |
293 ATH9K_INT_MIB |
294 ATH9K_INT_RXPHY |
295 ATH9K_INT_RXKCM |
296 ATH9K_INT_SWBA |
297 ATH9K_INT_BMISS |
298 ATH9K_INT_GPIO,
299 ATH9K_INT_NOCARD = 0xffffffff
300 };
301
302 #define CHANNEL_CW_INT 0x00002
303 #define CHANNEL_CCK 0x00020
304 #define CHANNEL_OFDM 0x00040
305 #define CHANNEL_2GHZ 0x00080
306 #define CHANNEL_5GHZ 0x00100
307 #define CHANNEL_PASSIVE 0x00200
308 #define CHANNEL_DYN 0x00400
309 #define CHANNEL_HALF 0x04000
310 #define CHANNEL_QUARTER 0x08000
311 #define CHANNEL_HT20 0x10000
312 #define CHANNEL_HT40PLUS 0x20000
313 #define CHANNEL_HT40MINUS 0x40000
314
315 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
316 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
317 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
318 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
319 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
320 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
321 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
322 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
323 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
324 #define CHANNEL_ALL \
325 (CHANNEL_OFDM| \
326 CHANNEL_CCK| \
327 CHANNEL_2GHZ | \
328 CHANNEL_5GHZ | \
329 CHANNEL_HT20 | \
330 CHANNEL_HT40PLUS | \
331 CHANNEL_HT40MINUS)
332
333 struct ath9k_hw_cal_data {
334 u16 channel;
335 u32 channelFlags;
336 int32_t CalValid;
337 int8_t iCoff;
338 int8_t qCoff;
339 bool paprd_done;
340 bool nfcal_pending;
341 bool nfcal_interference;
342 u16 small_signal_gain[AR9300_MAX_CHAINS];
343 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
344 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
345 };
346
347 struct ath9k_channel {
348 struct ieee80211_channel *chan;
349 struct ar5416AniState ani;
350 u16 channel;
351 u32 channelFlags;
352 u32 chanmode;
353 s16 noisefloor;
354 };
355
356 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
357 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
358 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
359 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
360 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
361 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
362 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
363 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
364 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
365 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
366 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
367 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
368
369 /* These macros check chanmode and not channelFlags */
370 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
371 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
372 ((_c)->chanmode == CHANNEL_G_HT20))
373 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
374 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
375 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
376 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
377 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
378
379 enum ath9k_power_mode {
380 ATH9K_PM_AWAKE = 0,
381 ATH9K_PM_FULL_SLEEP,
382 ATH9K_PM_NETWORK_SLEEP,
383 ATH9K_PM_UNDEFINED
384 };
385
386 enum ath9k_tp_scale {
387 ATH9K_TP_SCALE_MAX = 0,
388 ATH9K_TP_SCALE_50,
389 ATH9K_TP_SCALE_25,
390 ATH9K_TP_SCALE_12,
391 ATH9K_TP_SCALE_MIN
392 };
393
394 enum ser_reg_mode {
395 SER_REG_MODE_OFF = 0,
396 SER_REG_MODE_ON = 1,
397 SER_REG_MODE_AUTO = 2,
398 };
399
400 enum ath9k_rx_qtype {
401 ATH9K_RX_QUEUE_HP,
402 ATH9K_RX_QUEUE_LP,
403 ATH9K_RX_QUEUE_MAX,
404 };
405
406 struct ath9k_beacon_state {
407 u32 bs_nexttbtt;
408 u32 bs_nextdtim;
409 u32 bs_intval;
410 #define ATH9K_BEACON_PERIOD 0x0000ffff
411 #define ATH9K_BEACON_ENA 0x00800000
412 #define ATH9K_BEACON_RESET_TSF 0x01000000
413 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
414 u32 bs_dtimperiod;
415 u16 bs_cfpperiod;
416 u16 bs_cfpmaxduration;
417 u32 bs_cfpnext;
418 u16 bs_timoffset;
419 u16 bs_bmissthreshold;
420 u32 bs_sleepduration;
421 u32 bs_tsfoor_threshold;
422 };
423
424 struct chan_centers {
425 u16 synth_center;
426 u16 ctl_center;
427 u16 ext_center;
428 };
429
430 enum {
431 ATH9K_RESET_POWER_ON,
432 ATH9K_RESET_WARM,
433 ATH9K_RESET_COLD,
434 };
435
436 struct ath9k_hw_version {
437 u32 magic;
438 u16 devid;
439 u16 subvendorid;
440 u32 macVersion;
441 u16 macRev;
442 u16 phyRev;
443 u16 analog5GhzRev;
444 u16 analog2GhzRev;
445 u16 subsysid;
446 enum ath_usb_dev usbdev;
447 };
448
449 /* Generic TSF timer definitions */
450
451 #define ATH_MAX_GEN_TIMER 16
452
453 #define AR_GENTMR_BIT(_index) (1 << (_index))
454
455 /*
456 * Using de Bruijin sequence to look up 1's index in a 32 bit number
457 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
458 */
459 #define debruijn32 0x077CB531U
460
461 struct ath_gen_timer_configuration {
462 u32 next_addr;
463 u32 period_addr;
464 u32 mode_addr;
465 u32 mode_mask;
466 };
467
468 struct ath_gen_timer {
469 void (*trigger)(void *arg);
470 void (*overflow)(void *arg);
471 void *arg;
472 u8 index;
473 };
474
475 struct ath_gen_timer_table {
476 u32 gen_timer_index[32];
477 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
478 union {
479 unsigned long timer_bits;
480 u16 val;
481 } timer_mask;
482 };
483
484 struct ath_hw_antcomb_conf {
485 u8 main_lna_conf;
486 u8 alt_lna_conf;
487 u8 fast_div_bias;
488 };
489
490 /**
491 * struct ath_hw_radar_conf - radar detection initialization parameters
492 *
493 * @pulse_inband: threshold for checking the ratio of in-band power
494 * to total power for short radar pulses (half dB steps)
495 * @pulse_inband_step: threshold for checking an in-band power to total
496 * power ratio increase for short radar pulses (half dB steps)
497 * @pulse_height: threshold for detecting the beginning of a short
498 * radar pulse (dB step)
499 * @pulse_rssi: threshold for detecting if a short radar pulse is
500 * gone (dB step)
501 * @pulse_maxlen: maximum pulse length (0.8 us steps)
502 *
503 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
504 * @radar_inband: threshold for checking the ratio of in-band power
505 * to total power for long radar pulses (half dB steps)
506 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
507 *
508 * @ext_channel: enable extension channel radar detection
509 */
510 struct ath_hw_radar_conf {
511 unsigned int pulse_inband;
512 unsigned int pulse_inband_step;
513 unsigned int pulse_height;
514 unsigned int pulse_rssi;
515 unsigned int pulse_maxlen;
516
517 unsigned int radar_rssi;
518 unsigned int radar_inband;
519 int fir_power;
520
521 bool ext_channel;
522 };
523
524 /**
525 * struct ath_hw_private_ops - callbacks used internally by hardware code
526 *
527 * This structure contains private callbacks designed to only be used internally
528 * by the hardware core.
529 *
530 * @init_cal_settings: setup types of calibrations supported
531 * @init_cal: starts actual calibration
532 *
533 * @init_mode_regs: Initializes mode registers
534 * @init_mode_gain_regs: Initialize TX/RX gain registers
535 *
536 * @rf_set_freq: change frequency
537 * @spur_mitigate_freq: spur mitigation
538 * @rf_alloc_ext_banks:
539 * @rf_free_ext_banks:
540 * @set_rf_regs:
541 * @compute_pll_control: compute the PLL control value to use for
542 * AR_RTC_PLL_CONTROL for a given channel
543 * @setup_calibration: set up calibration
544 * @iscal_supported: used to query if a type of calibration is supported
545 *
546 * @ani_cache_ini_regs: cache the values for ANI from the initial
547 * register settings through the register initialization.
548 */
549 struct ath_hw_private_ops {
550 /* Calibration ops */
551 void (*init_cal_settings)(struct ath_hw *ah);
552 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
553
554 void (*init_mode_regs)(struct ath_hw *ah);
555 void (*init_mode_gain_regs)(struct ath_hw *ah);
556 void (*setup_calibration)(struct ath_hw *ah,
557 struct ath9k_cal_list *currCal);
558
559 /* PHY ops */
560 int (*rf_set_freq)(struct ath_hw *ah,
561 struct ath9k_channel *chan);
562 void (*spur_mitigate_freq)(struct ath_hw *ah,
563 struct ath9k_channel *chan);
564 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
565 void (*rf_free_ext_banks)(struct ath_hw *ah);
566 bool (*set_rf_regs)(struct ath_hw *ah,
567 struct ath9k_channel *chan,
568 u16 modesIndex);
569 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
570 void (*init_bb)(struct ath_hw *ah,
571 struct ath9k_channel *chan);
572 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
573 void (*olc_init)(struct ath_hw *ah);
574 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
575 void (*mark_phy_inactive)(struct ath_hw *ah);
576 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
577 bool (*rfbus_req)(struct ath_hw *ah);
578 void (*rfbus_done)(struct ath_hw *ah);
579 void (*restore_chainmask)(struct ath_hw *ah);
580 void (*set_diversity)(struct ath_hw *ah, bool value);
581 u32 (*compute_pll_control)(struct ath_hw *ah,
582 struct ath9k_channel *chan);
583 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
584 int param);
585 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
586 void (*set_radar_params)(struct ath_hw *ah,
587 struct ath_hw_radar_conf *conf);
588
589 /* ANI */
590 void (*ani_cache_ini_regs)(struct ath_hw *ah);
591 };
592
593 /**
594 * struct ath_hw_ops - callbacks used by hardware code and driver code
595 *
596 * This structure contains callbacks designed to to be used internally by
597 * hardware code and also by the lower level driver.
598 *
599 * @config_pci_powersave:
600 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
601 */
602 struct ath_hw_ops {
603 void (*config_pci_powersave)(struct ath_hw *ah,
604 int restore,
605 int power_off);
606 void (*rx_enable)(struct ath_hw *ah);
607 void (*set_desc_link)(void *ds, u32 link);
608 void (*get_desc_link)(void *ds, u32 **link);
609 bool (*calibrate)(struct ath_hw *ah,
610 struct ath9k_channel *chan,
611 u8 rxchainmask,
612 bool longcal);
613 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
614 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
615 bool is_firstseg, bool is_is_lastseg,
616 const void *ds0, dma_addr_t buf_addr,
617 unsigned int qcu);
618 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
619 struct ath_tx_status *ts);
620 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
621 u32 pktLen, enum ath9k_pkt_type type,
622 u32 txPower, u32 keyIx,
623 enum ath9k_key_type keyType,
624 u32 flags);
625 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
626 void *lastds,
627 u32 durUpdateEn, u32 rtsctsRate,
628 u32 rtsctsDuration,
629 struct ath9k_11n_rate_series series[],
630 u32 nseries, u32 flags);
631 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
632 u32 aggrLen);
633 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
634 u32 numDelims);
635 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
636 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
637 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
638 u32 burstDuration);
639 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
640 u32 vmf);
641 };
642
643 struct ath_nf_limits {
644 s16 max;
645 s16 min;
646 s16 nominal;
647 };
648
649 /* ah_flags */
650 #define AH_USE_EEPROM 0x1
651 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
652
653 struct ath_hw {
654 struct ieee80211_hw *hw;
655 struct ath_common common;
656 struct ath9k_hw_version hw_version;
657 struct ath9k_ops_config config;
658 struct ath9k_hw_capabilities caps;
659 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
660 struct ath9k_channel *curchan;
661
662 union {
663 struct ar5416_eeprom_def def;
664 struct ar5416_eeprom_4k map4k;
665 struct ar9287_eeprom map9287;
666 struct ar9300_eeprom ar9300_eep;
667 } eeprom;
668 const struct eeprom_ops *eep_ops;
669
670 bool sw_mgmt_crypto;
671 bool is_pciexpress;
672 bool is_monitoring;
673 bool need_an_top2_fixup;
674 u16 tx_trig_level;
675
676 u32 nf_regs[6];
677 struct ath_nf_limits nf_2g;
678 struct ath_nf_limits nf_5g;
679 u16 rfsilent;
680 u32 rfkill_gpio;
681 u32 rfkill_polarity;
682 u32 ah_flags;
683
684 bool htc_reset_init;
685
686 enum nl80211_iftype opmode;
687 enum ath9k_power_mode power_mode;
688
689 struct ath9k_hw_cal_data *caldata;
690 struct ath9k_pacal_info pacal_info;
691 struct ar5416Stats stats;
692 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
693
694 int16_t curchan_rad_index;
695 enum ath9k_int imask;
696 u32 imrs2_reg;
697 u32 txok_interrupt_mask;
698 u32 txerr_interrupt_mask;
699 u32 txdesc_interrupt_mask;
700 u32 txeol_interrupt_mask;
701 u32 txurn_interrupt_mask;
702 bool chip_fullsleep;
703 u32 atim_window;
704
705 /* Calibration */
706 u32 supp_cals;
707 struct ath9k_cal_list iq_caldata;
708 struct ath9k_cal_list adcgain_caldata;
709 struct ath9k_cal_list adcdc_caldata;
710 struct ath9k_cal_list tempCompCalData;
711 struct ath9k_cal_list *cal_list;
712 struct ath9k_cal_list *cal_list_last;
713 struct ath9k_cal_list *cal_list_curr;
714 #define totalPowerMeasI meas0.unsign
715 #define totalPowerMeasQ meas1.unsign
716 #define totalIqCorrMeas meas2.sign
717 #define totalAdcIOddPhase meas0.unsign
718 #define totalAdcIEvenPhase meas1.unsign
719 #define totalAdcQOddPhase meas2.unsign
720 #define totalAdcQEvenPhase meas3.unsign
721 #define totalAdcDcOffsetIOddPhase meas0.sign
722 #define totalAdcDcOffsetIEvenPhase meas1.sign
723 #define totalAdcDcOffsetQOddPhase meas2.sign
724 #define totalAdcDcOffsetQEvenPhase meas3.sign
725 union {
726 u32 unsign[AR5416_MAX_CHAINS];
727 int32_t sign[AR5416_MAX_CHAINS];
728 } meas0;
729 union {
730 u32 unsign[AR5416_MAX_CHAINS];
731 int32_t sign[AR5416_MAX_CHAINS];
732 } meas1;
733 union {
734 u32 unsign[AR5416_MAX_CHAINS];
735 int32_t sign[AR5416_MAX_CHAINS];
736 } meas2;
737 union {
738 u32 unsign[AR5416_MAX_CHAINS];
739 int32_t sign[AR5416_MAX_CHAINS];
740 } meas3;
741 u16 cal_samples;
742
743 u32 sta_id1_defaults;
744 u32 misc_mode;
745 enum {
746 AUTO_32KHZ,
747 USE_32KHZ,
748 DONT_USE_32KHZ,
749 } enable_32kHz_clock;
750
751 /* Private to hardware code */
752 struct ath_hw_private_ops private_ops;
753 /* Accessed by the lower level driver */
754 struct ath_hw_ops ops;
755
756 /* Used to program the radio on non single-chip devices */
757 u32 *analogBank0Data;
758 u32 *analogBank1Data;
759 u32 *analogBank2Data;
760 u32 *analogBank3Data;
761 u32 *analogBank6Data;
762 u32 *analogBank6TPCData;
763 u32 *analogBank7Data;
764 u32 *addac5416_21;
765 u32 *bank6Temp;
766
767 u8 txpower_limit;
768 int coverage_class;
769 u32 slottime;
770 u32 globaltxtimeout;
771
772 /* ANI */
773 u32 proc_phyerr;
774 u32 aniperiod;
775 int totalSizeDesired[5];
776 int coarse_high[5];
777 int coarse_low[5];
778 int firpwr[5];
779 enum ath9k_ani_cmd ani_function;
780
781 /* Bluetooth coexistance */
782 struct ath_btcoex_hw btcoex_hw;
783
784 u32 intr_txqs;
785 u8 txchainmask;
786 u8 rxchainmask;
787
788 struct ath_hw_radar_conf radar_conf;
789
790 u32 originalGain[22];
791 int initPDADC;
792 int PDADCdelta;
793 u8 led_pin;
794
795 struct ar5416IniArray iniModes;
796 struct ar5416IniArray iniCommon;
797 struct ar5416IniArray iniBank0;
798 struct ar5416IniArray iniBB_RfGain;
799 struct ar5416IniArray iniBank1;
800 struct ar5416IniArray iniBank2;
801 struct ar5416IniArray iniBank3;
802 struct ar5416IniArray iniBank6;
803 struct ar5416IniArray iniBank6TPC;
804 struct ar5416IniArray iniBank7;
805 struct ar5416IniArray iniAddac;
806 struct ar5416IniArray iniPcieSerdes;
807 struct ar5416IniArray iniPcieSerdesLowPower;
808 struct ar5416IniArray iniModesAdditional;
809 struct ar5416IniArray iniModesRxGain;
810 struct ar5416IniArray iniModesTxGain;
811 struct ar5416IniArray iniModes_9271_1_0_only;
812 struct ar5416IniArray iniCckfirNormal;
813 struct ar5416IniArray iniCckfirJapan2484;
814 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
815 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
816 struct ar5416IniArray iniModes_9271_ANI_reg;
817 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
818 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
819
820 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
821 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
822 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
823 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
824
825 u32 intr_gen_timer_trigger;
826 u32 intr_gen_timer_thresh;
827 struct ath_gen_timer_table hw_gen_timers;
828
829 struct ar9003_txs *ts_ring;
830 void *ts_start;
831 u32 ts_paddr_start;
832 u32 ts_paddr_end;
833 u16 ts_tail;
834 u8 ts_size;
835
836 u32 bb_watchdog_last_status;
837 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
838
839 unsigned int paprd_target_power;
840 unsigned int paprd_training_power;
841 unsigned int paprd_ratemask;
842 unsigned int paprd_ratemask_ht40;
843 bool paprd_table_write_done;
844 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
845 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
846 /*
847 * Store the permanent value of Reg 0x4004in WARegVal
848 * so we dont have to R/M/W. We should not be reading
849 * this register when in sleep states.
850 */
851 u32 WARegVal;
852
853 /* Enterprise mode cap */
854 u32 ent_mode;
855 };
856
857 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
858 {
859 return &ah->common;
860 }
861
862 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
863 {
864 return &(ath9k_hw_common(ah)->regulatory);
865 }
866
867 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
868 {
869 return &ah->private_ops;
870 }
871
872 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
873 {
874 return &ah->ops;
875 }
876
877 static inline u8 get_streams(int mask)
878 {
879 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
880 }
881
882 /* Initialization, Detach, Reset */
883 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
884 void ath9k_hw_deinit(struct ath_hw *ah);
885 int ath9k_hw_init(struct ath_hw *ah);
886 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
887 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
888 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
889 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
890
891 /* GPIO / RFKILL / Antennae */
892 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
893 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
894 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
895 u32 ah_signal_type);
896 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
897 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
898 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
899 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
900 struct ath_hw_antcomb_conf *antconf);
901 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
902 struct ath_hw_antcomb_conf *antconf);
903
904 /* General Operation */
905 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
906 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
907 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
908 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
909 u8 phy, int kbps,
910 u32 frameLen, u16 rateix, bool shortPreamble);
911 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
912 struct ath9k_channel *chan,
913 struct chan_centers *centers);
914 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
915 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
916 bool ath9k_hw_phy_disable(struct ath_hw *ah);
917 bool ath9k_hw_disable(struct ath_hw *ah);
918 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
919 void ath9k_hw_setopmode(struct ath_hw *ah);
920 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
921 void ath9k_hw_setbssidmask(struct ath_hw *ah);
922 void ath9k_hw_write_associd(struct ath_hw *ah);
923 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
924 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
925 void ath9k_hw_reset_tsf(struct ath_hw *ah);
926 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
927 void ath9k_hw_init_global_settings(struct ath_hw *ah);
928 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
929 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
930 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
931 const struct ath9k_beacon_state *bs);
932 bool ath9k_hw_check_alive(struct ath_hw *ah);
933
934 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
935
936 /* Generic hw timer primitives */
937 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
938 void (*trigger)(void *),
939 void (*overflow)(void *),
940 void *arg,
941 u8 timer_index);
942 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
943 struct ath_gen_timer *timer,
944 u32 timer_next,
945 u32 timer_period);
946 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
947
948 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
949 void ath_gen_timer_isr(struct ath_hw *hw);
950
951 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
952
953 /* HTC */
954 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
955
956 /* PHY */
957 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
958 u32 *coef_mantissa, u32 *coef_exponent);
959
960 /*
961 * Code Specific to AR5008, AR9001 or AR9002,
962 * we stuff these here to avoid callbacks for AR9003.
963 */
964 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
965 int ar9002_hw_rf_claim(struct ath_hw *ah);
966 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
967 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
968 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
969
970 /*
971 * Code specific to AR9003, we stuff these here to avoid callbacks
972 * for older families
973 */
974 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
975 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
976 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
977 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
978 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
979 struct ath9k_hw_cal_data *caldata,
980 int chain);
981 int ar9003_paprd_create_curve(struct ath_hw *ah,
982 struct ath9k_hw_cal_data *caldata, int chain);
983 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
984 int ar9003_paprd_init_table(struct ath_hw *ah);
985 bool ar9003_paprd_is_done(struct ath_hw *ah);
986 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
987
988 /* Hardware family op attach helpers */
989 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
990 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
991 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
992
993 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
994 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
995
996 void ar9002_hw_attach_ops(struct ath_hw *ah);
997 void ar9003_hw_attach_ops(struct ath_hw *ah);
998
999 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1000 /*
1001 * ANI work can be shared between all families but a next
1002 * generation implementation of ANI will be used only for AR9003 only
1003 * for now as the other families still need to be tested with the same
1004 * next generation ANI. Feel free to start testing it though for the
1005 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1006 */
1007 extern int modparam_force_new_ani;
1008 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1009 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1010 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1011
1012 #define ATH_PCIE_CAP_LINK_CTRL 0x70
1013 #define ATH_PCIE_CAP_LINK_L0S 1
1014 #define ATH_PCIE_CAP_LINK_L1 2
1015
1016 #define ATH9K_CLOCK_RATE_CCK 22
1017 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1018 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1019 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1020
1021 #endif
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