2 * Shared Atheros AR9170 Header
4 * RX/TX meta descriptor format
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
22 * This file incorporates work covered by the following copyright and
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
39 #ifndef __CARL9170_SHARED_WLAN_H
40 #define __CARL9170_SHARED_WLAN_H
44 #define AR9170_RX_PHY_RATE_CCK_1M 0x0a
45 #define AR9170_RX_PHY_RATE_CCK_2M 0x14
46 #define AR9170_RX_PHY_RATE_CCK_5M 0x37
47 #define AR9170_RX_PHY_RATE_CCK_11M 0x6e
49 #define AR9170_ENC_ALG_NONE 0x0
50 #define AR9170_ENC_ALG_WEP64 0x1
51 #define AR9170_ENC_ALG_TKIP 0x2
52 #define AR9170_ENC_ALG_AESCCMP 0x4
53 #define AR9170_ENC_ALG_WEP128 0x5
54 #define AR9170_ENC_ALG_WEP256 0x6
55 #define AR9170_ENC_ALG_CENC 0x7
57 #define AR9170_RX_ENC_SOFTWARE 0x8
59 #define AR9170_RX_STATUS_MODULATION 0x03
60 #define AR9170_RX_STATUS_MODULATION_S 0
61 #define AR9170_RX_STATUS_MODULATION_CCK 0x00
62 #define AR9170_RX_STATUS_MODULATION_OFDM 0x01
63 #define AR9170_RX_STATUS_MODULATION_HT 0x02
64 #define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
66 /* depends on modulation */
67 #define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
68 #define AR9170_RX_STATUS_GREENFIELD 0x08
70 #define AR9170_RX_STATUS_MPDU 0x30
71 #define AR9170_RX_STATUS_MPDU_S 4
72 #define AR9170_RX_STATUS_MPDU_SINGLE 0x00
73 #define AR9170_RX_STATUS_MPDU_FIRST 0x20
74 #define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
75 #define AR9170_RX_STATUS_MPDU_LAST 0x10
77 #define AR9170_RX_STATUS_CONT_AGGR 0x40
78 #define AR9170_RX_STATUS_TOTAL_ERROR 0x80
80 #define AR9170_RX_ERROR_RXTO 0x01
81 #define AR9170_RX_ERROR_OVERRUN 0x02
82 #define AR9170_RX_ERROR_DECRYPT 0x04
83 #define AR9170_RX_ERROR_FCS 0x08
84 #define AR9170_RX_ERROR_WRONG_RA 0x10
85 #define AR9170_RX_ERROR_PLCP 0x20
86 #define AR9170_RX_ERROR_MMIC 0x40
88 /* these are either-or */
89 #define AR9170_TX_MAC_PROT_RTS 0x0001
90 #define AR9170_TX_MAC_PROT_CTS 0x0002
91 #define AR9170_TX_MAC_PROT 0x0003
93 #define AR9170_TX_MAC_NO_ACK 0x0004
94 /* if unset, MAC will only do SIFS space before frame */
95 #define AR9170_TX_MAC_BACKOFF 0x0008
96 #define AR9170_TX_MAC_BURST 0x0010
97 #define AR9170_TX_MAC_AGGR 0x0020
99 /* encryption is a two-bit field */
100 #define AR9170_TX_MAC_ENCR_NONE 0x0000
101 #define AR9170_TX_MAC_ENCR_RC4 0x0040
102 #define AR9170_TX_MAC_ENCR_CENC 0x0080
103 #define AR9170_TX_MAC_ENCR_AES 0x00c0
105 #define AR9170_TX_MAC_MMIC 0x0100
106 #define AR9170_TX_MAC_HW_DURATION 0x0200
107 #define AR9170_TX_MAC_QOS_S 10
108 #define AR9170_TX_MAC_QOS 0x0c00
109 #define AR9170_TX_MAC_DISABLE_TXOP 0x1000
110 #define AR9170_TX_MAC_TXOP_RIFS 0x2000
111 #define AR9170_TX_MAC_IMM_BA 0x4000
114 #define AR9170_TX_PHY_MOD_CCK 0x00000000
115 #define AR9170_TX_PHY_MOD_OFDM 0x00000001
116 #define AR9170_TX_PHY_MOD_HT 0x00000002
118 /* depends on modulation */
119 #define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
120 #define AR9170_TX_PHY_GREENFIELD 0x00000004
122 #define AR9170_TX_PHY_BW_S 3
123 #define AR9170_TX_PHY_BW (3 << AR9170_TX_PHY_BW_SHIFT)
124 #define AR9170_TX_PHY_BW_20MHZ 0
125 #define AR9170_TX_PHY_BW_40MHZ 2
126 #define AR9170_TX_PHY_BW_40MHZ_DUP 3
128 #define AR9170_TX_PHY_TX_HEAVY_CLIP_S 6
129 #define AR9170_TX_PHY_TX_HEAVY_CLIP (7 << \
130 AR9170_TX_PHY_TX_HEAVY_CLIP_S)
132 #define AR9170_TX_PHY_TX_PWR_S 9
133 #define AR9170_TX_PHY_TX_PWR (0x3f << \
134 AR9170_TX_PHY_TX_PWR_S)
136 #define AR9170_TX_PHY_TXCHAIN_S 15
137 #define AR9170_TX_PHY_TXCHAIN (7 << \
138 AR9170_TX_PHY_TXCHAIN_S)
139 #define AR9170_TX_PHY_TXCHAIN_1 1
140 /* use for cck, ofdm 6/9/12/18/24 and HT if capable */
141 #define AR9170_TX_PHY_TXCHAIN_2 5
143 #define AR9170_TX_PHY_MCS_S 18
144 #define AR9170_TX_PHY_MCS (0x7f << \
147 #define AR9170_TX_PHY_RATE_CCK_1M 0x0
148 #define AR9170_TX_PHY_RATE_CCK_2M 0x1
149 #define AR9170_TX_PHY_RATE_CCK_5M 0x2
150 #define AR9170_TX_PHY_RATE_CCK_11M 0x3
152 /* same as AR9170_RX_PHY_RATE */
153 #define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb
154 #define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf
155 #define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa
156 #define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe
157 #define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9
158 #define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd
159 #define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8
160 #define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc
162 #define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0
163 #define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1
164 #define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2
165 #define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3
166 #define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4
167 #define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5
168 #define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6
169 #define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7
170 #define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8
171 #define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9
172 #define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa
173 #define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb
174 #define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc
175 #define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd
176 #define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe
177 #define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf
179 #define AR9170_TX_PHY_SHORT_GI 0x80000000
181 #ifdef __CARL9170FW__
182 struct ar9170_tx_hw_mac_control
{
186 * Beware of compiler bugs in all gcc pre 4.4!
213 struct ar9170_tx_hw_phy_control
{
217 * Beware of compiler bugs in all gcc pre 4.4!
236 struct ar9170_tx_rate_info
{
240 u8 free
:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */
243 struct carl9170_tx_superdesc
{
250 u8 ampdu_commit_density
:1;
251 u8 ampdu_commit_factor
:1;
252 u8 ampdu_unused_bit
:1;
259 struct ar9170_tx_rate_info ri
[CARL9170_TX_MAX_RATES
];
260 struct ar9170_tx_hw_phy_control rr
[CARL9170_TX_MAX_RETRY_RATES
];
263 struct ar9170_tx_hwdesc
{
265 struct ar9170_tx_hw_mac_control mac
;
266 struct ar9170_tx_hw_phy_control phy
;
269 struct ar9170_tx_frame
{
270 struct ar9170_tx_hwdesc hdr
;
273 struct ieee80211_hdr i3e
;
278 struct carl9170_tx_superframe
{
279 struct carl9170_tx_superdesc s
;
280 struct ar9170_tx_frame f
;
283 #endif /* __CARL9170FW__ */
285 struct _ar9170_tx_hwdesc
{
291 #define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0
292 #define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7
293 #define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18
294 #define CARL9170_TX_SUPER_AMPDU_FACTOR_S 3
295 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20
296 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S 5
297 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40
298 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6
300 #define CARL9170_TX_SUPER_MISC_QUEUE 0x3
301 #define CARL9170_TX_SUPER_MISC_QUEUE_S 0
302 #define CARL9170_TX_SUPER_MISC_VIF_ID 0x38
303 #define CARL9170_TX_SUPER_MISC_VIF_ID_S 3
304 #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40
305 #define CARL9170_TX_SUPER_MISC_CAB 0x80
307 #define CARL9170_TX_SUPER_RI_TRIES 0x7
308 #define CARL9170_TX_SUPER_RI_TRIES_S 0
309 #define CARL9170_TX_SUPER_RI_ERP_PROT 0x18
310 #define CARL9170_TX_SUPER_RI_ERP_PROT_S 3
311 #define CARL9170_TX_SUPER_RI_AMPDU 0x20
312 #define CARL9170_TX_SUPER_RI_AMPDU_S 5
314 struct _carl9170_tx_superdesc
{
322 u8 ri
[CARL9170_TX_MAX_RATES
];
323 __le32 rr
[CARL9170_TX_MAX_RETRY_RATES
];
326 struct _carl9170_tx_superframe
{
327 struct _carl9170_tx_superdesc s
;
328 struct _ar9170_tx_hwdesc f
;
332 #define CARL9170_TX_SUPERDESC_LEN 24
333 #define AR9170_TX_HWDESC_LEN 8
334 #define CARL9170_TX_SUPERFRAME_LEN (CARL9170_TX_SUPERDESC_LEN + \
335 AR9170_TX_HWDESC_LEN)
337 struct ar9170_rx_head
{
341 #define AR9170_RX_HEAD_LEN 12
343 struct ar9170_rx_phystatus
{
346 u8 rssi_ant0
, rssi_ant1
, rssi_ant2
,
347 rssi_ant0x
, rssi_ant1x
, rssi_ant2x
,
353 u8 evm_stream0
[6], evm_stream1
[6];
357 #define AR9170_RX_PHYSTATUS_LEN 20
359 struct ar9170_rx_macstatus
{
365 #define AR9170_RX_MACSTATUS_LEN 4
367 struct ar9170_rx_frame_single
{
368 struct ar9170_rx_head phy_head
;
369 struct ieee80211_hdr i3e
;
370 struct ar9170_rx_phystatus phy_tail
;
371 struct ar9170_rx_macstatus macstatus
;
374 struct ar9170_rx_frame_head
{
375 struct ar9170_rx_head phy_head
;
376 struct ieee80211_hdr i3e
;
377 struct ar9170_rx_macstatus macstatus
;
380 struct ar9170_rx_frame_middle
{
381 struct ieee80211_hdr i3e
;
382 struct ar9170_rx_macstatus macstatus
;
385 struct ar9170_rx_frame_tail
{
386 struct ieee80211_hdr i3e
;
387 struct ar9170_rx_phystatus phy_tail
;
388 struct ar9170_rx_macstatus macstatus
;
391 struct ar9170_rx_frame
{
393 struct ar9170_rx_frame_single single
;
394 struct ar9170_rx_frame_head head
;
395 struct ar9170_rx_frame_middle middle
;
396 struct ar9170_rx_frame_tail tail
;
400 static inline u8
ar9170_get_decrypt_type(struct ar9170_rx_macstatus
*t
)
402 return (t
->SAidx
& 0xc0) >> 4 |
403 (t
->DAidx
& 0xc0) >> 6;
416 static const u8 ar9170_qmap
[__AR9170_NUM_TXQ
] = { 2, 1, 0, 3 };
418 #define AR9170_TXQ_DEPTH 32
420 #endif /* __CARL9170_SHARED_WLAN_H */