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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / wireless / b43 / phy_n.c
blobab81ed8b19d7e9030327123b5417be4d6ae10f9c
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23 */
24
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
28
29 #include "b43.h"
30 #include "phy_n.h"
31 #include "tables_nphy.h"
32 #include "radio_2055.h"
33 #include "radio_2056.h"
34 #include "main.h"
35
36 struct nphy_txgains {
37 u16 txgm[2];
38 u16 pga[2];
39 u16 pad[2];
40 u16 ipa[2];
41 };
42
43 struct nphy_iqcal_params {
44 u16 txgm;
45 u16 pga;
46 u16 pad;
47 u16 ipa;
48 u16 cal_gain;
49 u16 ncorr[5];
50 };
51
52 struct nphy_iq_est {
53 s32 iq0_prod;
54 u32 i0_pwr;
55 u32 q0_pwr;
56 s32 iq1_prod;
57 u32 i1_pwr;
58 u32 q1_pwr;
59 };
60
61 enum b43_nphy_rf_sequence {
62 B43_RFSEQ_RX2TX,
63 B43_RFSEQ_TX2RX,
64 B43_RFSEQ_RESET2RX,
65 B43_RFSEQ_UPDATE_GAINH,
66 B43_RFSEQ_UPDATE_GAINL,
67 B43_RFSEQ_UPDATE_GAINU,
68 };
69
70 enum b43_nphy_rssi_type {
71 B43_NPHY_RSSI_X = 0,
72 B43_NPHY_RSSI_Y,
73 B43_NPHY_RSSI_Z,
74 B43_NPHY_RSSI_PWRDET,
75 B43_NPHY_RSSI_TSSI_I,
76 B43_NPHY_RSSI_TSSI_Q,
77 B43_NPHY_RSSI_TBD,
78 };
79
80 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
81 bool enable);
82 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
83 u8 *events, u8 *delays, u8 length);
84 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
85 enum b43_nphy_rf_sequence seq);
86 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
87 u16 value, u8 core, bool off);
88 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
89 u16 value, u8 core);
90
91 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
92 {//TODO
93 }
94
95 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
96 {//TODO
97 }
98
99 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
100 bool ignore_tssi)
101 {//TODO
102 return B43_TXPWR_RES_DONE;
103 }
104
105 static void b43_chantab_radio_upload(struct b43_wldev *dev,
106 const struct b43_nphy_channeltab_entry_rev2 *e)
107 {
108 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
109 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
110 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
111 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
112 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
113
114 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
115 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
116 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
117 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
118 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
119
120 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
121 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
122 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
123 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
124 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
125
126 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
127 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
128 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
129 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
130 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
131
132 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
133 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
134 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
135 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
136 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
137
138 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
139 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
140 }
141
142 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
143 const struct b43_nphy_channeltab_entry_rev3 *e)
144 {
145 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
146 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
147 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
148 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
149 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
150 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
151 e->radio_syn_pll_loopfilter1);
152 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
153 e->radio_syn_pll_loopfilter2);
154 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
155 e->radio_syn_pll_loopfilter3);
156 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
157 e->radio_syn_pll_loopfilter4);
158 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
159 e->radio_syn_pll_loopfilter5);
160 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
161 e->radio_syn_reserved_addr27);
162 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
163 e->radio_syn_reserved_addr28);
164 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
165 e->radio_syn_reserved_addr29);
166 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
167 e->radio_syn_logen_vcobuf1);
168 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
169 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
170 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
171
172 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
173 e->radio_rx0_lnaa_tune);
174 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
175 e->radio_rx0_lnag_tune);
176
177 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
178 e->radio_tx0_intpaa_boost_tune);
179 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
180 e->radio_tx0_intpag_boost_tune);
181 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
182 e->radio_tx0_pada_boost_tune);
183 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
184 e->radio_tx0_padg_boost_tune);
185 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
186 e->radio_tx0_pgaa_boost_tune);
187 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
188 e->radio_tx0_pgag_boost_tune);
189 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
190 e->radio_tx0_mixa_boost_tune);
191 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
192 e->radio_tx0_mixg_boost_tune);
193
194 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
195 e->radio_rx1_lnaa_tune);
196 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
197 e->radio_rx1_lnag_tune);
198
199 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
200 e->radio_tx1_intpaa_boost_tune);
201 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
202 e->radio_tx1_intpag_boost_tune);
203 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
204 e->radio_tx1_pada_boost_tune);
205 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
206 e->radio_tx1_padg_boost_tune);
207 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
208 e->radio_tx1_pgaa_boost_tune);
209 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
210 e->radio_tx1_pgag_boost_tune);
211 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
212 e->radio_tx1_mixa_boost_tune);
213 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
214 e->radio_tx1_mixg_boost_tune);
215 }
216
217 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
218 static void b43_radio_2056_setup(struct b43_wldev *dev,
219 const struct b43_nphy_channeltab_entry_rev3 *e)
220 {
221 B43_WARN_ON(dev->phy.rev < 3);
222
223 b43_chantab_radio_2056_upload(dev, e);
224 /* TODO */
225 udelay(50);
226 /* VCO calibration */
227 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
228 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
229 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
230 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
231 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
232 udelay(300);
233 }
234
235 static void b43_chantab_phy_upload(struct b43_wldev *dev,
236 const struct b43_phy_n_sfo_cfg *e)
237 {
238 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
239 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
240 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
241 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
242 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
243 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
244 }
245
246 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
247 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
248 {
249 struct b43_phy_n *nphy = dev->phy.n;
250 u8 i;
251 u16 tmp;
252
253 if (nphy->hang_avoid)
254 b43_nphy_stay_in_carrier_search(dev, 1);
255
256 nphy->txpwrctrl = enable;
257 if (!enable) {
258 if (dev->phy.rev >= 3)
259 ; /* TODO */
260
261 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
262 for (i = 0; i < 84; i++)
263 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
264
265 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
266 for (i = 0; i < 84; i++)
267 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
268
269 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
270 if (dev->phy.rev >= 3)
271 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
272 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
273
274 if (dev->phy.rev >= 3) {
275 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
276 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
277 } else {
278 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
279 }
280
281 if (dev->phy.rev == 2)
282 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
283 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
284 else if (dev->phy.rev < 2)
285 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
286 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
287
288 if (dev->phy.rev < 2 && 0)
289 ; /* TODO */
290 } else {
291 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
292 }
293
294 if (nphy->hang_avoid)
295 b43_nphy_stay_in_carrier_search(dev, 0);
296 }
297
298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
299 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
300 {
301 struct b43_phy_n *nphy = dev->phy.n;
302 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
303
304 u8 txpi[2], bbmult, i;
305 u16 tmp, radio_gain, dac_gain;
306 u16 freq = dev->phy.channel_freq;
307 u32 txgain;
308 /* u32 gaintbl; rev3+ */
309
310 if (nphy->hang_avoid)
311 b43_nphy_stay_in_carrier_search(dev, 1);
312
313 if (dev->phy.rev >= 3) {
314 txpi[0] = 40;
315 txpi[1] = 40;
316 } else if (sprom->revision < 4) {
317 txpi[0] = 72;
318 txpi[1] = 72;
319 } else {
320 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
321 txpi[0] = sprom->txpid2g[0];
322 txpi[1] = sprom->txpid2g[1];
323 } else if (freq >= 4900 && freq < 5100) {
324 txpi[0] = sprom->txpid5gl[0];
325 txpi[1] = sprom->txpid5gl[1];
326 } else if (freq >= 5100 && freq < 5500) {
327 txpi[0] = sprom->txpid5g[0];
328 txpi[1] = sprom->txpid5g[1];
329 } else if (freq >= 5500) {
330 txpi[0] = sprom->txpid5gh[0];
331 txpi[1] = sprom->txpid5gh[1];
332 } else {
333 txpi[0] = 91;
334 txpi[1] = 91;
335 }
336 }
337
338 /*
339 for (i = 0; i < 2; i++) {
340 nphy->txpwrindex[i].index_internal = txpi[i];
341 nphy->txpwrindex[i].index_internal_save = txpi[i];
342 }
343 */
344
345 for (i = 0; i < 2; i++) {
346 if (dev->phy.rev >= 3) {
347 /* FIXME: support 5GHz */
348 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
349 radio_gain = (txgain >> 16) & 0x1FFFF;
350 } else {
351 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
352 radio_gain = (txgain >> 16) & 0x1FFF;
353 }
354
355 dac_gain = (txgain >> 8) & 0x3F;
356 bbmult = txgain & 0xFF;
357
358 if (dev->phy.rev >= 3) {
359 if (i == 0)
360 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
361 else
362 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
363 } else {
364 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
365 }
366
367 if (i == 0)
368 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
369 else
370 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
371
372 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
373 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
374
375 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
376 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
377
378 if (i == 0)
379 tmp = (tmp & 0x00FF) | (bbmult << 8);
380 else
381 tmp = (tmp & 0xFF00) | bbmult;
382
383 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
384 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
385
386 if (0)
387 ; /* TODO */
388 }
389
390 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
391
392 if (nphy->hang_avoid)
393 b43_nphy_stay_in_carrier_search(dev, 0);
394 }
395
396
397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
398 static void b43_radio_2055_setup(struct b43_wldev *dev,
399 const struct b43_nphy_channeltab_entry_rev2 *e)
400 {
401 B43_WARN_ON(dev->phy.rev >= 3);
402
403 b43_chantab_radio_upload(dev, e);
404 udelay(50);
405 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
406 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
407 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
408 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
409 udelay(300);
410 }
411
412 static void b43_radio_init2055_pre(struct b43_wldev *dev)
413 {
414 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
415 ~B43_NPHY_RFCTL_CMD_PORFORCE);
416 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
417 B43_NPHY_RFCTL_CMD_CHIP0PU |
418 B43_NPHY_RFCTL_CMD_OEPORFORCE);
419 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
420 B43_NPHY_RFCTL_CMD_PORFORCE);
421 }
422
423 static void b43_radio_init2055_post(struct b43_wldev *dev)
424 {
425 struct b43_phy_n *nphy = dev->phy.n;
426 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
427 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
428 int i;
429 u16 val;
430 bool workaround = false;
431
432 if (sprom->revision < 4)
433 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
434 binfo->type != 0x46D ||
435 binfo->rev < 0x41);
436 else
437 workaround =
438 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
439
440 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
441 if (workaround) {
442 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
443 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
444 }
445 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
446 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
447 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
448 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
449 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
450 msleep(1);
451 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
452 for (i = 0; i < 200; i++) {
453 val = b43_radio_read(dev, B2055_CAL_COUT2);
454 if (val & 0x80) {
455 i = 0;
456 break;
457 }
458 udelay(10);
459 }
460 if (i)
461 b43err(dev->wl, "radio post init timeout\n");
462 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
463 b43_switch_channel(dev, dev->phy.channel);
464 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
465 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
466 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
467 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
468 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
469 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
470 if (!nphy->gain_boost) {
471 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
472 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
473 } else {
474 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
475 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
476 }
477 udelay(2);
478 }
479
480 /*
481 * Initialize a Broadcom 2055 N-radio
482 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
483 */
484 static void b43_radio_init2055(struct b43_wldev *dev)
485 {
486 b43_radio_init2055_pre(dev);
487 if (b43_status(dev) < B43_STAT_INITIALIZED) {
488 /* Follow wl, not specs. Do not force uploading all regs */
489 b2055_upload_inittab(dev, 0, 0);
490 } else {
491 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
492 b2055_upload_inittab(dev, ghz5, 0);
493 }
494 b43_radio_init2055_post(dev);
495 }
496
497 static void b43_radio_init2056_pre(struct b43_wldev *dev)
498 {
499 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
500 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
501 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
502 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
503 B43_NPHY_RFCTL_CMD_OEPORFORCE);
504 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
505 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
506 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
507 B43_NPHY_RFCTL_CMD_CHIP0PU);
508 }
509
510 static void b43_radio_init2056_post(struct b43_wldev *dev)
511 {
512 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
513 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
514 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
515 msleep(1);
516 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
517 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
518 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
519 /*
520 if (nphy->init_por)
521 Call Radio 2056 Recalibrate
522 */
523 }
524
525 /*
526 * Initialize a Broadcom 2056 N-radio
527 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
528 */
529 static void b43_radio_init2056(struct b43_wldev *dev)
530 {
531 b43_radio_init2056_pre(dev);
532 b2056_upload_inittabs(dev, 0, 0);
533 b43_radio_init2056_post(dev);
534 }
535
536 /*
537 * Upload the N-PHY tables.
538 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
539 */
540 static void b43_nphy_tables_init(struct b43_wldev *dev)
541 {
542 if (dev->phy.rev < 3)
543 b43_nphy_rev0_1_2_tables_init(dev);
544 else
545 b43_nphy_rev3plus_tables_init(dev);
546 }
547
548 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
549 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
550 {
551 struct b43_phy_n *nphy = dev->phy.n;
552 enum ieee80211_band band;
553 u16 tmp;
554
555 if (!enable) {
556 nphy->rfctrl_intc1_save = b43_phy_read(dev,
557 B43_NPHY_RFCTL_INTC1);
558 nphy->rfctrl_intc2_save = b43_phy_read(dev,
559 B43_NPHY_RFCTL_INTC2);
560 band = b43_current_band(dev->wl);
561 if (dev->phy.rev >= 3) {
562 if (band == IEEE80211_BAND_5GHZ)
563 tmp = 0x600;
564 else
565 tmp = 0x480;
566 } else {
567 if (band == IEEE80211_BAND_5GHZ)
568 tmp = 0x180;
569 else
570 tmp = 0x120;
571 }
572 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
573 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
574 } else {
575 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
576 nphy->rfctrl_intc1_save);
577 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
578 nphy->rfctrl_intc2_save);
579 }
580 }
581
582 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
583 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
584 {
585 struct b43_phy_n *nphy = dev->phy.n;
586 u16 tmp;
587 enum ieee80211_band band = b43_current_band(dev->wl);
588 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
589 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
590
591 if (dev->phy.rev >= 3) {
592 if (ipa) {
593 tmp = 4;
594 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
595 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
596 }
597
598 tmp = 1;
599 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
600 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
601 }
602 }
603
604 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
605 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
606 {
607 u32 tmslow;
608
609 if (dev->phy.type != B43_PHYTYPE_N)
610 return;
611
612 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
613 if (force)
614 tmslow |= SSB_TMSLOW_FGC;
615 else
616 tmslow &= ~SSB_TMSLOW_FGC;
617 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
618 }
619
620 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
621 static void b43_nphy_reset_cca(struct b43_wldev *dev)
622 {
623 u16 bbcfg;
624
625 b43_nphy_bmac_clock_fgc(dev, 1);
626 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
627 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
628 udelay(1);
629 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
630 b43_nphy_bmac_clock_fgc(dev, 0);
631 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
632 }
633
634 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
635 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
636 {
637 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
638
639 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
640 if (preamble == 1)
641 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
642 else
643 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
644
645 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
646 }
647
648 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
649 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
650 {
651 struct b43_phy_n *nphy = dev->phy.n;
652
653 bool override = false;
654 u16 chain = 0x33;
655
656 if (nphy->txrx_chain == 0) {
657 chain = 0x11;
658 override = true;
659 } else if (nphy->txrx_chain == 1) {
660 chain = 0x22;
661 override = true;
662 }
663
664 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
665 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
666 chain);
667
668 if (override)
669 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
670 B43_NPHY_RFSEQMODE_CAOVER);
671 else
672 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
673 ~B43_NPHY_RFSEQMODE_CAOVER);
674 }
675
676 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
677 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
678 u16 samps, u8 time, bool wait)
679 {
680 int i;
681 u16 tmp;
682
683 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
684 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
685 if (wait)
686 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
687 else
688 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
689
690 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
691
692 for (i = 1000; i; i--) {
693 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
694 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
695 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
696 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
697 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
698 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
699 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
700 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
701
702 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
703 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
704 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
705 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
706 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
707 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
708 return;
709 }
710 udelay(10);
711 }
712 memset(est, 0, sizeof(*est));
713 }
714
715 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
716 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
717 struct b43_phy_n_iq_comp *pcomp)
718 {
719 if (write) {
720 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
721 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
722 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
723 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
724 } else {
725 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
726 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
727 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
728 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
729 }
730 }
731
732 #if 0
733 /* Ready but not used anywhere */
734 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
735 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
736 {
737 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
738
739 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
740 if (core == 0) {
741 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
742 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
743 } else {
744 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
745 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
746 }
747 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
748 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
749 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
750 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
751 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
752 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
753 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
754 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
755 }
756
757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
758 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
759 {
760 u8 rxval, txval;
761 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
762
763 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
764 if (core == 0) {
765 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
766 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
767 } else {
768 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
769 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
770 }
771 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
772 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
773 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
774 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
775 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
776 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
777 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
778 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
779
780 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
781 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
782
783 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
784 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
785 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
786 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
787 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
788 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
789 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
790 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
791 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
792
793 if (core == 0) {
794 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
795 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
796 } else {
797 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
798 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
799 }
800
801 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
802 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
803 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
804
805 if (core == 0) {
806 rxval = 1;
807 txval = 8;
808 } else {
809 rxval = 4;
810 txval = 2;
811 }
812 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
813 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
814 }
815 #endif
816
817 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
818 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
819 {
820 int i;
821 s32 iq;
822 u32 ii;
823 u32 qq;
824 int iq_nbits, qq_nbits;
825 int arsh, brsh;
826 u16 tmp, a, b;
827
828 struct nphy_iq_est est;
829 struct b43_phy_n_iq_comp old;
830 struct b43_phy_n_iq_comp new = { };
831 bool error = false;
832
833 if (mask == 0)
834 return;
835
836 b43_nphy_rx_iq_coeffs(dev, false, &old);
837 b43_nphy_rx_iq_coeffs(dev, true, &new);
838 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
839 new = old;
840
841 for (i = 0; i < 2; i++) {
842 if (i == 0 && (mask & 1)) {
843 iq = est.iq0_prod;
844 ii = est.i0_pwr;
845 qq = est.q0_pwr;
846 } else if (i == 1 && (mask & 2)) {
847 iq = est.iq1_prod;
848 ii = est.i1_pwr;
849 qq = est.q1_pwr;
850 } else {
851 continue;
852 }
853
854 if (ii + qq < 2) {
855 error = true;
856 break;
857 }
858
859 iq_nbits = fls(abs(iq));
860 qq_nbits = fls(qq);
861
862 arsh = iq_nbits - 20;
863 if (arsh >= 0) {
864 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
865 tmp = ii >> arsh;
866 } else {
867 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
868 tmp = ii << -arsh;
869 }
870 if (tmp == 0) {
871 error = true;
872 break;
873 }
874 a /= tmp;
875
876 brsh = qq_nbits - 11;
877 if (brsh >= 0) {
878 b = (qq << (31 - qq_nbits));
879 tmp = ii >> brsh;
880 } else {
881 b = (qq << (31 - qq_nbits));
882 tmp = ii << -brsh;
883 }
884 if (tmp == 0) {
885 error = true;
886 break;
887 }
888 b = int_sqrt(b / tmp - a * a) - (1 << 10);
889
890 if (i == 0 && (mask & 0x1)) {
891 if (dev->phy.rev >= 3) {
892 new.a0 = a & 0x3FF;
893 new.b0 = b & 0x3FF;
894 } else {
895 new.a0 = b & 0x3FF;
896 new.b0 = a & 0x3FF;
897 }
898 } else if (i == 1 && (mask & 0x2)) {
899 if (dev->phy.rev >= 3) {
900 new.a1 = a & 0x3FF;
901 new.b1 = b & 0x3FF;
902 } else {
903 new.a1 = b & 0x3FF;
904 new.b1 = a & 0x3FF;
905 }
906 }
907 }
908
909 if (error)
910 new = old;
911
912 b43_nphy_rx_iq_coeffs(dev, true, &new);
913 }
914
915 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
916 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
917 {
918 u16 array[4];
919 int i;
920
921 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
922 for (i = 0; i < 4; i++)
923 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
924
925 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
926 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
927 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
928 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
929 }
930
931 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
932 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
933 const u16 *clip_st)
934 {
935 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
936 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
937 }
938
939 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
940 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
941 {
942 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
943 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
944 }
945
946 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
947 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
948 {
949 if (dev->phy.rev >= 3) {
950 if (!init)
951 return;
952 if (0 /* FIXME */) {
953 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
954 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
955 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
956 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
957 }
958 } else {
959 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
960 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
961
962 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
963 0xFC00);
964 b43_write32(dev, B43_MMIO_MACCTL,
965 b43_read32(dev, B43_MMIO_MACCTL) &
966 ~B43_MACCTL_GPOUTSMSK);
967 b43_write16(dev, B43_MMIO_GPIO_MASK,
968 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
969 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
970 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
971
972 if (init) {
973 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
974 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
975 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
976 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
977 }
978 }
979 }
980
981 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
982 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
983 {
984 u16 tmp;
985
986 if (dev->dev->id.revision == 16)
987 b43_mac_suspend(dev);
988
989 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
990 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
991 B43_NPHY_CLASSCTL_WAITEDEN);
992 tmp &= ~mask;
993 tmp |= (val & mask);
994 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
995
996 if (dev->dev->id.revision == 16)
997 b43_mac_enable(dev);
998
999 return tmp;
1000 }
1001
1002 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1003 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1004 {
1005 struct b43_phy *phy = &dev->phy;
1006 struct b43_phy_n *nphy = phy->n;
1007
1008 if (enable) {
1009 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1010 if (nphy->deaf_count++ == 0) {
1011 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1012 b43_nphy_classifier(dev, 0x7, 0);
1013 b43_nphy_read_clip_detection(dev, nphy->clip_state);
1014 b43_nphy_write_clip_detection(dev, clip);
1015 }
1016 b43_nphy_reset_cca(dev);
1017 } else {
1018 if (--nphy->deaf_count == 0) {
1019 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1020 b43_nphy_write_clip_detection(dev, nphy->clip_state);
1021 }
1022 }
1023 }
1024
1025 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1026 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1027 {
1028 struct b43_phy_n *nphy = dev->phy.n;
1029 u16 tmp;
1030
1031 if (nphy->hang_avoid)
1032 b43_nphy_stay_in_carrier_search(dev, 1);
1033
1034 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1035 if (tmp & 0x1)
1036 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1037 else if (tmp & 0x2)
1038 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1039
1040 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1041
1042 if (nphy->bb_mult_save & 0x80000000) {
1043 tmp = nphy->bb_mult_save & 0xFFFF;
1044 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1045 nphy->bb_mult_save = 0;
1046 }
1047
1048 if (nphy->hang_avoid)
1049 b43_nphy_stay_in_carrier_search(dev, 0);
1050 }
1051
1052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1053 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1054 {
1055 struct b43_phy_n *nphy = dev->phy.n;
1056
1057 u8 channel = dev->phy.channel;
1058 int tone[2] = { 57, 58 };
1059 u32 noise[2] = { 0x3FF, 0x3FF };
1060
1061 B43_WARN_ON(dev->phy.rev < 3);
1062
1063 if (nphy->hang_avoid)
1064 b43_nphy_stay_in_carrier_search(dev, 1);
1065
1066 if (nphy->gband_spurwar_en) {
1067 /* TODO: N PHY Adjust Analog Pfbw (7) */
1068 if (channel == 11 && dev->phy.is_40mhz)
1069 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1070 else
1071 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1072 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1073 }
1074
1075 if (nphy->aband_spurwar_en) {
1076 if (channel == 54) {
1077 tone[0] = 0x20;
1078 noise[0] = 0x25F;
1079 } else if (channel == 38 || channel == 102 || channel == 118) {
1080 if (0 /* FIXME */) {
1081 tone[0] = 0x20;
1082 noise[0] = 0x21F;
1083 } else {
1084 tone[0] = 0;
1085 noise[0] = 0;
1086 }
1087 } else if (channel == 134) {
1088 tone[0] = 0x20;
1089 noise[0] = 0x21F;
1090 } else if (channel == 151) {
1091 tone[0] = 0x10;
1092 noise[0] = 0x23F;
1093 } else if (channel == 153 || channel == 161) {
1094 tone[0] = 0x30;
1095 noise[0] = 0x23F;
1096 } else {
1097 tone[0] = 0;
1098 noise[0] = 0;
1099 }
1100
1101 if (!tone[0] && !noise[0])
1102 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1103 else
1104 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1105 }
1106
1107 if (nphy->hang_avoid)
1108 b43_nphy_stay_in_carrier_search(dev, 0);
1109 }
1110
1111 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1112 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1113 {
1114 struct b43_phy_n *nphy = dev->phy.n;
1115
1116 u8 i;
1117 s16 tmp;
1118 u16 data[4];
1119 s16 gain[2];
1120 u16 minmax[2];
1121 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1122
1123 if (nphy->hang_avoid)
1124 b43_nphy_stay_in_carrier_search(dev, 1);
1125
1126 if (nphy->gain_boost) {
1127 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1128 gain[0] = 6;
1129 gain[1] = 6;
1130 } else {
1131 tmp = 40370 - 315 * dev->phy.channel;
1132 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1133 tmp = 23242 - 224 * dev->phy.channel;
1134 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1135 }
1136 } else {
1137 gain[0] = 0;
1138 gain[1] = 0;
1139 }
1140
1141 for (i = 0; i < 2; i++) {
1142 if (nphy->elna_gain_config) {
1143 data[0] = 19 + gain[i];
1144 data[1] = 25 + gain[i];
1145 data[2] = 25 + gain[i];
1146 data[3] = 25 + gain[i];
1147 } else {
1148 data[0] = lna_gain[0] + gain[i];
1149 data[1] = lna_gain[1] + gain[i];
1150 data[2] = lna_gain[2] + gain[i];
1151 data[3] = lna_gain[3] + gain[i];
1152 }
1153 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1154
1155 minmax[i] = 23 + gain[i];
1156 }
1157
1158 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1159 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1160 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1161 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1162
1163 if (nphy->hang_avoid)
1164 b43_nphy_stay_in_carrier_search(dev, 0);
1165 }
1166
1167 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1168 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1169 {
1170 struct b43_phy_n *nphy = dev->phy.n;
1171 u8 i, j;
1172 u8 code;
1173 u16 tmp;
1174
1175 /* TODO: for PHY >= 3
1176 s8 *lna1_gain, *lna2_gain;
1177 u8 *gain_db, *gain_bits;
1178 u16 *rfseq_init;
1179 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1180 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1181 */
1182
1183 u8 rfseq_events[3] = { 6, 8, 7 };
1184 u8 rfseq_delays[3] = { 10, 30, 1 };
1185
1186 if (dev->phy.rev >= 3) {
1187 /* TODO */
1188 } else {
1189 /* Set Clip 2 detect */
1190 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1191 B43_NPHY_C1_CGAINI_CL2DETECT);
1192 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1193 B43_NPHY_C2_CGAINI_CL2DETECT);
1194
1195 /* Set narrowband clip threshold */
1196 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1197 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1198
1199 if (!dev->phy.is_40mhz) {
1200 /* Set dwell lengths */
1201 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1202 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1203 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1204 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1205 }
1206
1207 /* Set wideband clip 2 threshold */
1208 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1209 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1210 21);
1211 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1212 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1213 21);
1214
1215 if (!dev->phy.is_40mhz) {
1216 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1217 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1218 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1219 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1220 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1221 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1222 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1223 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1224 }
1225
1226 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1227
1228 if (nphy->gain_boost) {
1229 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1230 dev->phy.is_40mhz)
1231 code = 4;
1232 else
1233 code = 5;
1234 } else {
1235 code = dev->phy.is_40mhz ? 6 : 7;
1236 }
1237
1238 /* Set HPVGA2 index */
1239 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1240 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1241 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1242 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1243 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1244 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1245
1246 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1247 /* specs say about 2 loops, but wl does 4 */
1248 for (i = 0; i < 4; i++)
1249 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1250 (code << 8 | 0x7C));
1251
1252 b43_nphy_adjust_lna_gain_table(dev);
1253
1254 if (nphy->elna_gain_config) {
1255 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1256 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1257 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1258 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1259 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1260
1261 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1262 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1263 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1264 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1265 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1266
1267 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1268 /* specs say about 2 loops, but wl does 4 */
1269 for (i = 0; i < 4; i++)
1270 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1271 (code << 8 | 0x74));
1272 }
1273
1274 if (dev->phy.rev == 2) {
1275 for (i = 0; i < 4; i++) {
1276 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1277 (0x0400 * i) + 0x0020);
1278 for (j = 0; j < 21; j++) {
1279 tmp = j * (i < 2 ? 3 : 1);
1280 b43_phy_write(dev,
1281 B43_NPHY_TABLE_DATALO, tmp);
1282 }
1283 }
1284
1285 b43_nphy_set_rf_sequence(dev, 5,
1286 rfseq_events, rfseq_delays, 3);
1287 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1288 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1289 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1290
1291 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1292 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1293 0xFF80, 4);
1294 }
1295 }
1296 }
1297
1298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1299 static void b43_nphy_workarounds(struct b43_wldev *dev)
1300 {
1301 struct ssb_bus *bus = dev->dev->bus;
1302 struct b43_phy *phy = &dev->phy;
1303 struct b43_phy_n *nphy = phy->n;
1304
1305 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1306 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1307
1308 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1309 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1310
1311 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1312 b43_nphy_classifier(dev, 1, 0);
1313 else
1314 b43_nphy_classifier(dev, 1, 1);
1315
1316 if (nphy->hang_avoid)
1317 b43_nphy_stay_in_carrier_search(dev, 1);
1318
1319 b43_phy_set(dev, B43_NPHY_IQFLIP,
1320 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1321
1322 if (dev->phy.rev >= 3) {
1323 /* TODO */
1324 } else {
1325 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1326 nphy->band5g_pwrgain) {
1327 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1328 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1329 } else {
1330 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1331 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1332 }
1333
1334 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1335 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1336 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1337 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1338
1339 if (dev->phy.rev < 2) {
1340 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1341 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1342 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1343 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1344 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1345 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1346 }
1347
1348 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1349 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1350 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1351 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1352
1353 if (bus->sprom.boardflags2_lo & 0x100 &&
1354 bus->boardinfo.type == 0x8B) {
1355 delays1[0] = 0x1;
1356 delays1[5] = 0x14;
1357 }
1358 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1359 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1360
1361 b43_nphy_gain_ctrl_workarounds(dev);
1362
1363 if (dev->phy.rev < 2) {
1364 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1365 b43_hf_write(dev, b43_hf_read(dev) |
1366 B43_HF_MLADVW);
1367 } else if (dev->phy.rev == 2) {
1368 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1369 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1370 }
1371
1372 if (dev->phy.rev < 2)
1373 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1374 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1375
1376 /* Set phase track alpha and beta */
1377 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1378 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1379 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1380 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1381 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1382 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1383
1384 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1385 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1386 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1387 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1388 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1389
1390 if (dev->phy.rev == 2)
1391 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1392 B43_NPHY_FINERX2_CGC_DECGC);
1393 }
1394
1395 if (nphy->hang_avoid)
1396 b43_nphy_stay_in_carrier_search(dev, 0);
1397 }
1398
1399 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1400 static int b43_nphy_load_samples(struct b43_wldev *dev,
1401 struct b43_c32 *samples, u16 len) {
1402 struct b43_phy_n *nphy = dev->phy.n;
1403 u16 i;
1404 u32 *data;
1405
1406 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1407 if (!data) {
1408 b43err(dev->wl, "allocation for samples loading failed\n");
1409 return -ENOMEM;
1410 }
1411 if (nphy->hang_avoid)
1412 b43_nphy_stay_in_carrier_search(dev, 1);
1413
1414 for (i = 0; i < len; i++) {
1415 data[i] = (samples[i].i & 0x3FF << 10);
1416 data[i] |= samples[i].q & 0x3FF;
1417 }
1418 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1419
1420 kfree(data);
1421 if (nphy->hang_avoid)
1422 b43_nphy_stay_in_carrier_search(dev, 0);
1423 return 0;
1424 }
1425
1426 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1427 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1428 bool test)
1429 {
1430 int i;
1431 u16 bw, len, rot, angle;
1432 struct b43_c32 *samples;
1433
1434
1435 bw = (dev->phy.is_40mhz) ? 40 : 20;
1436 len = bw << 3;
1437
1438 if (test) {
1439 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1440 bw = 82;
1441 else
1442 bw = 80;
1443
1444 if (dev->phy.is_40mhz)
1445 bw <<= 1;
1446
1447 len = bw << 1;
1448 }
1449
1450 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1451 if (!samples) {
1452 b43err(dev->wl, "allocation for samples generation failed\n");
1453 return 0;
1454 }
1455 rot = (((freq * 36) / bw) << 16) / 100;
1456 angle = 0;
1457
1458 for (i = 0; i < len; i++) {
1459 samples[i] = b43_cordic(angle);
1460 angle += rot;
1461 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1462 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1463 }
1464
1465 i = b43_nphy_load_samples(dev, samples, len);
1466 kfree(samples);
1467 return (i < 0) ? 0 : len;
1468 }
1469
1470 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1471 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1472 u16 wait, bool iqmode, bool dac_test)
1473 {
1474 struct b43_phy_n *nphy = dev->phy.n;
1475 int i;
1476 u16 seq_mode;
1477 u32 tmp;
1478
1479 if (nphy->hang_avoid)
1480 b43_nphy_stay_in_carrier_search(dev, true);
1481
1482 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1483 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1484 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1485 }
1486
1487 if (!dev->phy.is_40mhz)
1488 tmp = 0x6464;
1489 else
1490 tmp = 0x4747;
1491 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1492
1493 if (nphy->hang_avoid)
1494 b43_nphy_stay_in_carrier_search(dev, false);
1495
1496 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1497
1498 if (loops != 0xFFFF)
1499 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1500 else
1501 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1502
1503 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1504
1505 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1506
1507 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1508 if (iqmode) {
1509 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1510 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1511 } else {
1512 if (dac_test)
1513 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1514 else
1515 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1516 }
1517 for (i = 0; i < 100; i++) {
1518 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1519 i = 0;
1520 break;
1521 }
1522 udelay(10);
1523 }
1524 if (i)
1525 b43err(dev->wl, "run samples timeout\n");
1526
1527 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1528 }
1529
1530 /*
1531 * Transmits a known value for LO calibration
1532 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1533 */
1534 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1535 bool iqmode, bool dac_test)
1536 {
1537 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1538 if (samp == 0)
1539 return -1;
1540 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1541 return 0;
1542 }
1543
1544 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1545 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1546 {
1547 struct b43_phy_n *nphy = dev->phy.n;
1548 int i, j;
1549 u32 tmp;
1550 u32 cur_real, cur_imag, real_part, imag_part;
1551
1552 u16 buffer[7];
1553
1554 if (nphy->hang_avoid)
1555 b43_nphy_stay_in_carrier_search(dev, true);
1556
1557 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1558
1559 for (i = 0; i < 2; i++) {
1560 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1561 (buffer[i * 2 + 1] & 0x3FF);
1562 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1563 (((i + 26) << 10) | 320));
1564 for (j = 0; j < 128; j++) {
1565 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1566 ((tmp >> 16) & 0xFFFF));
1567 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1568 (tmp & 0xFFFF));
1569 }
1570 }
1571
1572 for (i = 0; i < 2; i++) {
1573 tmp = buffer[5 + i];
1574 real_part = (tmp >> 8) & 0xFF;
1575 imag_part = (tmp & 0xFF);
1576 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1577 (((i + 26) << 10) | 448));
1578
1579 if (dev->phy.rev >= 3) {
1580 cur_real = real_part;
1581 cur_imag = imag_part;
1582 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1583 }
1584
1585 for (j = 0; j < 128; j++) {
1586 if (dev->phy.rev < 3) {
1587 cur_real = (real_part * loscale[j] + 128) >> 8;
1588 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1589 tmp = ((cur_real & 0xFF) << 8) |
1590 (cur_imag & 0xFF);
1591 }
1592 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1593 ((tmp >> 16) & 0xFFFF));
1594 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1595 (tmp & 0xFFFF));
1596 }
1597 }
1598
1599 if (dev->phy.rev >= 3) {
1600 b43_shm_write16(dev, B43_SHM_SHARED,
1601 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1602 b43_shm_write16(dev, B43_SHM_SHARED,
1603 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1604 }
1605
1606 if (nphy->hang_avoid)
1607 b43_nphy_stay_in_carrier_search(dev, false);
1608 }
1609
1610 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1611 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1612 u8 *events, u8 *delays, u8 length)
1613 {
1614 struct b43_phy_n *nphy = dev->phy.n;
1615 u8 i;
1616 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1617 u16 offset1 = cmd << 4;
1618 u16 offset2 = offset1 + 0x80;
1619
1620 if (nphy->hang_avoid)
1621 b43_nphy_stay_in_carrier_search(dev, true);
1622
1623 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1624 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1625
1626 for (i = length; i < 16; i++) {
1627 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1628 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1629 }
1630
1631 if (nphy->hang_avoid)
1632 b43_nphy_stay_in_carrier_search(dev, false);
1633 }
1634
1635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1636 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1637 enum b43_nphy_rf_sequence seq)
1638 {
1639 static const u16 trigger[] = {
1640 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1641 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1642 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1643 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1644 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1645 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1646 };
1647 int i;
1648 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1649
1650 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1651
1652 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1653 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1654 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1655 for (i = 0; i < 200; i++) {
1656 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1657 goto ok;
1658 msleep(1);
1659 }
1660 b43err(dev->wl, "RF sequence status timeout\n");
1661 ok:
1662 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1663 }
1664
1665 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1666 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1667 u16 value, u8 core, bool off)
1668 {
1669 int i;
1670 u8 index = fls(field);
1671 u8 addr, en_addr, val_addr;
1672 /* we expect only one bit set */
1673 B43_WARN_ON(field & (~(1 << (index - 1))));
1674
1675 if (dev->phy.rev >= 3) {
1676 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1677 for (i = 0; i < 2; i++) {
1678 if (index == 0 || index == 16) {
1679 b43err(dev->wl,
1680 "Unsupported RF Ctrl Override call\n");
1681 return;
1682 }
1683
1684 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1685 en_addr = B43_PHY_N((i == 0) ?
1686 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1687 val_addr = B43_PHY_N((i == 0) ?
1688 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1689
1690 if (off) {
1691 b43_phy_mask(dev, en_addr, ~(field));
1692 b43_phy_mask(dev, val_addr,
1693 ~(rf_ctrl->val_mask));
1694 } else {
1695 if (core == 0 || ((1 << core) & i) != 0) {
1696 b43_phy_set(dev, en_addr, field);
1697 b43_phy_maskset(dev, val_addr,
1698 ~(rf_ctrl->val_mask),
1699 (value << rf_ctrl->val_shift));
1700 }
1701 }
1702 }
1703 } else {
1704 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1705 if (off) {
1706 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1707 value = 0;
1708 } else {
1709 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1710 }
1711
1712 for (i = 0; i < 2; i++) {
1713 if (index <= 1 || index == 16) {
1714 b43err(dev->wl,
1715 "Unsupported RF Ctrl Override call\n");
1716 return;
1717 }
1718
1719 if (index == 2 || index == 10 ||
1720 (index >= 13 && index <= 15)) {
1721 core = 1;
1722 }
1723
1724 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1725 addr = B43_PHY_N((i == 0) ?
1726 rf_ctrl->addr0 : rf_ctrl->addr1);
1727
1728 if ((core & (1 << i)) != 0)
1729 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1730 (value << rf_ctrl->shift));
1731
1732 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1733 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1734 B43_NPHY_RFCTL_CMD_START);
1735 udelay(1);
1736 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1737 }
1738 }
1739 }
1740
1741 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1742 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1743 u16 value, u8 core)
1744 {
1745 u8 i, j;
1746 u16 reg, tmp, val;
1747
1748 B43_WARN_ON(dev->phy.rev < 3);
1749 B43_WARN_ON(field > 4);
1750
1751 for (i = 0; i < 2; i++) {
1752 if ((core == 1 && i == 1) || (core == 2 && !i))
1753 continue;
1754
1755 reg = (i == 0) ?
1756 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1757 b43_phy_mask(dev, reg, 0xFBFF);
1758
1759 switch (field) {
1760 case 0:
1761 b43_phy_write(dev, reg, 0);
1762 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1763 break;
1764 case 1:
1765 if (!i) {
1766 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1767 0xFC3F, (value << 6));
1768 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1769 0xFFFE, 1);
1770 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1771 B43_NPHY_RFCTL_CMD_START);
1772 for (j = 0; j < 100; j++) {
1773 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1774 j = 0;
1775 break;
1776 }
1777 udelay(10);
1778 }
1779 if (j)
1780 b43err(dev->wl,
1781 "intc override timeout\n");
1782 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1783 0xFFFE);
1784 } else {
1785 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1786 0xFC3F, (value << 6));
1787 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1788 0xFFFE, 1);
1789 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1790 B43_NPHY_RFCTL_CMD_RXTX);
1791 for (j = 0; j < 100; j++) {
1792 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1793 j = 0;
1794 break;
1795 }
1796 udelay(10);
1797 }
1798 if (j)
1799 b43err(dev->wl,
1800 "intc override timeout\n");
1801 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1802 0xFFFE);
1803 }
1804 break;
1805 case 2:
1806 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1807 tmp = 0x0020;
1808 val = value << 5;
1809 } else {
1810 tmp = 0x0010;
1811 val = value << 4;
1812 }
1813 b43_phy_maskset(dev, reg, ~tmp, val);
1814 break;
1815 case 3:
1816 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1817 tmp = 0x0001;
1818 val = value;
1819 } else {
1820 tmp = 0x0004;
1821 val = value << 2;
1822 }
1823 b43_phy_maskset(dev, reg, ~tmp, val);
1824 break;
1825 case 4:
1826 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1827 tmp = 0x0002;
1828 val = value << 1;
1829 } else {
1830 tmp = 0x0008;
1831 val = value << 3;
1832 }
1833 b43_phy_maskset(dev, reg, ~tmp, val);
1834 break;
1835 }
1836 }
1837 }
1838
1839 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
1840 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1841 {
1842 unsigned int i;
1843 u16 val;
1844
1845 val = 0x1E1F;
1846 for (i = 0; i < 16; i++) {
1847 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1848 val -= 0x202;
1849 }
1850 val = 0x3E3F;
1851 for (i = 0; i < 16; i++) {
1852 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
1853 val -= 0x202;
1854 }
1855 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1856 }
1857
1858 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1859 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1860 s8 offset, u8 core, u8 rail,
1861 enum b43_nphy_rssi_type type)
1862 {
1863 u16 tmp;
1864 bool core1or5 = (core == 1) || (core == 5);
1865 bool core2or5 = (core == 2) || (core == 5);
1866
1867 offset = clamp_val(offset, -32, 31);
1868 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1869
1870 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1871 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1872 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1873 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1874 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1875 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1876 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1877 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1878
1879 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1880 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1881 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1882 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1883 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1884 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1885 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1886 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1887
1888 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1889 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1890 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1891 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1892 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1893 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1894 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1895 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1896
1897 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1898 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1899 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1900 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1901 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1902 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1903 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1904 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1905
1906 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1907 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1908 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1909 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1910 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1911 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1912 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1913 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1914
1915 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1916 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1917 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1918 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1919
1920 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1921 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1922 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1923 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1924 }
1925
1926 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1927 {
1928 u16 val;
1929
1930 if (type < 3)
1931 val = 0;
1932 else if (type == 6)
1933 val = 1;
1934 else if (type == 3)
1935 val = 2;
1936 else
1937 val = 3;
1938
1939 val = (val << 12) | (val << 14);
1940 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1941 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1942
1943 if (type < 3) {
1944 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1945 (type + 1) << 4);
1946 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1947 (type + 1) << 4);
1948 }
1949
1950 if (code == 0) {
1951 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1952 if (type < 3) {
1953 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1954 ~(B43_NPHY_RFCTL_CMD_RXEN |
1955 B43_NPHY_RFCTL_CMD_CORESEL));
1956 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1957 ~(0x1 << 12 |
1958 0x1 << 5 |
1959 0x1 << 1 |
1960 0x1));
1961 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1962 ~B43_NPHY_RFCTL_CMD_START);
1963 udelay(20);
1964 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1965 }
1966 } else {
1967 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1968 if (type < 3) {
1969 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1970 ~(B43_NPHY_RFCTL_CMD_RXEN |
1971 B43_NPHY_RFCTL_CMD_CORESEL),
1972 (B43_NPHY_RFCTL_CMD_RXEN |
1973 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1974 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1975 (0x1 << 12 |
1976 0x1 << 5 |
1977 0x1 << 1 |
1978 0x1));
1979 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1980 B43_NPHY_RFCTL_CMD_START);
1981 udelay(20);
1982 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1983 }
1984 }
1985 }
1986
1987 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1988 {
1989 struct b43_phy_n *nphy = dev->phy.n;
1990 u8 i;
1991 u16 reg, val;
1992
1993 if (code == 0) {
1994 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1995 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1996 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1997 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1998 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1999 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2000 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2001 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2002 } else {
2003 for (i = 0; i < 2; i++) {
2004 if ((code == 1 && i == 1) || (code == 2 && !i))
2005 continue;
2006
2007 reg = (i == 0) ?
2008 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2009 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2010
2011 if (type < 3) {
2012 reg = (i == 0) ?
2013 B43_NPHY_AFECTL_C1 :
2014 B43_NPHY_AFECTL_C2;
2015 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2016
2017 reg = (i == 0) ?
2018 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2019 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2020 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2021
2022 if (type == 0)
2023 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2024 else if (type == 1)
2025 val = 16;
2026 else
2027 val = 32;
2028 b43_phy_set(dev, reg, val);
2029
2030 reg = (i == 0) ?
2031 B43_NPHY_TXF_40CO_B1S0 :
2032 B43_NPHY_TXF_40CO_B32S1;
2033 b43_phy_set(dev, reg, 0x0020);
2034 } else {
2035 if (type == 6)
2036 val = 0x0100;
2037 else if (type == 3)
2038 val = 0x0200;
2039 else
2040 val = 0x0300;
2041
2042 reg = (i == 0) ?
2043 B43_NPHY_AFECTL_C1 :
2044 B43_NPHY_AFECTL_C2;
2045
2046 b43_phy_maskset(dev, reg, 0xFCFF, val);
2047 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2048
2049 if (type != 3 && type != 6) {
2050 enum ieee80211_band band =
2051 b43_current_band(dev->wl);
2052
2053 if ((nphy->ipa2g_on &&
2054 band == IEEE80211_BAND_2GHZ) ||
2055 (nphy->ipa5g_on &&
2056 band == IEEE80211_BAND_5GHZ))
2057 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2058 else
2059 val = 0x11;
2060 reg = (i == 0) ? 0x2000 : 0x3000;
2061 reg |= B2055_PADDRV;
2062 b43_radio_write16(dev, reg, val);
2063
2064 reg = (i == 0) ?
2065 B43_NPHY_AFECTL_OVER1 :
2066 B43_NPHY_AFECTL_OVER;
2067 b43_phy_set(dev, reg, 0x0200);
2068 }
2069 }
2070 }
2071 }
2072 }
2073
2074 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2075 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2076 {
2077 if (dev->phy.rev >= 3)
2078 b43_nphy_rev3_rssi_select(dev, code, type);
2079 else
2080 b43_nphy_rev2_rssi_select(dev, code, type);
2081 }
2082
2083 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2084 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2085 {
2086 int i;
2087 for (i = 0; i < 2; i++) {
2088 if (type == 2) {
2089 if (i == 0) {
2090 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2091 0xFC, buf[0]);
2092 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2093 0xFC, buf[1]);
2094 } else {
2095 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2096 0xFC, buf[2 * i]);
2097 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2098 0xFC, buf[2 * i + 1]);
2099 }
2100 } else {
2101 if (i == 0)
2102 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2103 0xF3, buf[0] << 2);
2104 else
2105 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2106 0xF3, buf[2 * i + 1] << 2);
2107 }
2108 }
2109 }
2110
2111 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2112 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2113 u8 nsamp)
2114 {
2115 int i;
2116 int out;
2117 u16 save_regs_phy[9];
2118 u16 s[2];
2119
2120 if (dev->phy.rev >= 3) {
2121 save_regs_phy[0] = b43_phy_read(dev,
2122 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2123 save_regs_phy[1] = b43_phy_read(dev,
2124 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2125 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2126 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2127 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2128 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2129 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2130 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2131 } else if (dev->phy.rev == 2) {
2132 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2133 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2134 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2135 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2136 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2137 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2138 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2139 }
2140
2141 b43_nphy_rssi_select(dev, 5, type);
2142
2143 if (dev->phy.rev < 2) {
2144 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2145 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2146 }
2147
2148 for (i = 0; i < 4; i++)
2149 buf[i] = 0;
2150
2151 for (i = 0; i < nsamp; i++) {
2152 if (dev->phy.rev < 2) {
2153 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2154 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2155 } else {
2156 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2157 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2158 }
2159
2160 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2161 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2162 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2163 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2164 }
2165 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2166 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2167
2168 if (dev->phy.rev < 2)
2169 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2170
2171 if (dev->phy.rev >= 3) {
2172 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2173 save_regs_phy[0]);
2174 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2175 save_regs_phy[1]);
2176 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2177 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2178 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2179 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2180 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2181 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2182 } else if (dev->phy.rev == 2) {
2183 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2184 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2185 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2186 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2187 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2188 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2189 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2190 }
2191
2192 return out;
2193 }
2194
2195 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2196 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2197 {
2198 int i, j;
2199 u8 state[4];
2200 u8 code, val;
2201 u16 class, override;
2202 u8 regs_save_radio[2];
2203 u16 regs_save_phy[2];
2204
2205 s8 offset[4];
2206 u8 core;
2207 u8 rail;
2208
2209 u16 clip_state[2];
2210 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2211 s32 results_min[4] = { };
2212 u8 vcm_final[4] = { };
2213 s32 results[4][4] = { };
2214 s32 miniq[4][2] = { };
2215
2216 if (type == 2) {
2217 code = 0;
2218 val = 6;
2219 } else if (type < 2) {
2220 code = 25;
2221 val = 4;
2222 } else {
2223 B43_WARN_ON(1);
2224 return;
2225 }
2226
2227 class = b43_nphy_classifier(dev, 0, 0);
2228 b43_nphy_classifier(dev, 7, 4);
2229 b43_nphy_read_clip_detection(dev, clip_state);
2230 b43_nphy_write_clip_detection(dev, clip_off);
2231
2232 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2233 override = 0x140;
2234 else
2235 override = 0x110;
2236
2237 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2238 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2239 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2240 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2241
2242 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2243 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2244 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2245 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2246
2247 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2248 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2249 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2250 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2251 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2252 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2253
2254 b43_nphy_rssi_select(dev, 5, type);
2255 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2256 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2257
2258 for (i = 0; i < 4; i++) {
2259 u8 tmp[4];
2260 for (j = 0; j < 4; j++)
2261 tmp[j] = i;
2262 if (type != 1)
2263 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2264 b43_nphy_poll_rssi(dev, type, results[i], 8);
2265 if (type < 2)
2266 for (j = 0; j < 2; j++)
2267 miniq[i][j] = min(results[i][2 * j],
2268 results[i][2 * j + 1]);
2269 }
2270
2271 for (i = 0; i < 4; i++) {
2272 s32 mind = 40;
2273 u8 minvcm = 0;
2274 s32 minpoll = 249;
2275 s32 curr;
2276 for (j = 0; j < 4; j++) {
2277 if (type == 2)
2278 curr = abs(results[j][i]);
2279 else
2280 curr = abs(miniq[j][i / 2] - code * 8);
2281
2282 if (curr < mind) {
2283 mind = curr;
2284 minvcm = j;
2285 }
2286
2287 if (results[j][i] < minpoll)
2288 minpoll = results[j][i];
2289 }
2290 results_min[i] = minpoll;
2291 vcm_final[i] = minvcm;
2292 }
2293
2294 if (type != 1)
2295 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2296
2297 for (i = 0; i < 4; i++) {
2298 offset[i] = (code * 8) - results[vcm_final[i]][i];
2299
2300 if (offset[i] < 0)
2301 offset[i] = -((abs(offset[i]) + 4) / 8);
2302 else
2303 offset[i] = (offset[i] + 4) / 8;
2304
2305 if (results_min[i] == 248)
2306 offset[i] = code - 32;
2307
2308 core = (i / 2) ? 2 : 1;
2309 rail = (i % 2) ? 1 : 0;
2310
2311 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2312 type);
2313 }
2314
2315 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2316 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2317
2318 switch (state[2]) {
2319 case 1:
2320 b43_nphy_rssi_select(dev, 1, 2);
2321 break;
2322 case 4:
2323 b43_nphy_rssi_select(dev, 1, 0);
2324 break;
2325 case 2:
2326 b43_nphy_rssi_select(dev, 1, 1);
2327 break;
2328 default:
2329 b43_nphy_rssi_select(dev, 1, 1);
2330 break;
2331 }
2332
2333 switch (state[3]) {
2334 case 1:
2335 b43_nphy_rssi_select(dev, 2, 2);
2336 break;
2337 case 4:
2338 b43_nphy_rssi_select(dev, 2, 0);
2339 break;
2340 default:
2341 b43_nphy_rssi_select(dev, 2, 1);
2342 break;
2343 }
2344
2345 b43_nphy_rssi_select(dev, 0, type);
2346
2347 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2348 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2349 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2350 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2351
2352 b43_nphy_classifier(dev, 7, class);
2353 b43_nphy_write_clip_detection(dev, clip_state);
2354 /* Specs don't say about reset here, but it makes wl and b43 dumps
2355 identical, it really seems wl performs this */
2356 b43_nphy_reset_cca(dev);
2357 }
2358
2359 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2360 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2361 {
2362 /* TODO */
2363 }
2364
2365 /*
2366 * RSSI Calibration
2367 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2368 */
2369 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2370 {
2371 if (dev->phy.rev >= 3) {
2372 b43_nphy_rev3_rssi_cal(dev);
2373 } else {
2374 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2375 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2376 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2377 }
2378 }
2379
2380 /*
2381 * Restore RSSI Calibration
2382 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2383 */
2384 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2385 {
2386 struct b43_phy_n *nphy = dev->phy.n;
2387
2388 u16 *rssical_radio_regs = NULL;
2389 u16 *rssical_phy_regs = NULL;
2390
2391 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2392 if (!nphy->rssical_chanspec_2G.center_freq)
2393 return;
2394 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2395 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2396 } else {
2397 if (!nphy->rssical_chanspec_5G.center_freq)
2398 return;
2399 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2400 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2401 }
2402
2403 /* TODO use some definitions */
2404 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2405 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2406
2407 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2408 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2409 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2410 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2411
2412 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2413 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2414 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2415 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2416
2417 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2418 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2419 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2420 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2421 }
2422
2423 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2424 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2425 {
2426 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2427 if (dev->phy.rev >= 6) {
2428 /* TODO If the chip is 47162
2429 return txpwrctrl_tx_gain_ipa_rev5 */
2430 return txpwrctrl_tx_gain_ipa_rev6;
2431 } else if (dev->phy.rev >= 5) {
2432 return txpwrctrl_tx_gain_ipa_rev5;
2433 } else {
2434 return txpwrctrl_tx_gain_ipa;
2435 }
2436 } else {
2437 return txpwrctrl_tx_gain_ipa_5g;
2438 }
2439 }
2440
2441 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2442 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2443 {
2444 struct b43_phy_n *nphy = dev->phy.n;
2445 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2446 u16 tmp;
2447 u8 offset, i;
2448
2449 if (dev->phy.rev >= 3) {
2450 for (i = 0; i < 2; i++) {
2451 tmp = (i == 0) ? 0x2000 : 0x3000;
2452 offset = i * 11;
2453
2454 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2455 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2456 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2457 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2458 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2459 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2460 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2461 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2462 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2463 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2464 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2465
2466 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2467 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2468 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2469 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2470 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2471 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2472 if (nphy->ipa5g_on) {
2473 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2474 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2475 } else {
2476 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2477 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2478 }
2479 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2480 } else {
2481 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2482 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2483 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2484 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2485 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2486 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2487 if (nphy->ipa2g_on) {
2488 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2489 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2490 (dev->phy.rev < 5) ? 0x11 : 0x01);
2491 } else {
2492 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2493 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2494 }
2495 }
2496 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2497 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2498 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2499 }
2500 } else {
2501 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2502 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2503
2504 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2505 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2506
2507 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2508 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2509
2510 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2511 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2512
2513 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2514 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2515
2516 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2517 B43_NPHY_BANDCTL_5GHZ)) {
2518 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2519 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2520 } else {
2521 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2522 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2523 }
2524
2525 if (dev->phy.rev < 2) {
2526 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2527 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2528 } else {
2529 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2530 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2531 }
2532 }
2533 }
2534
2535 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2536 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2537 struct nphy_txgains target,
2538 struct nphy_iqcal_params *params)
2539 {
2540 int i, j, indx;
2541 u16 gain;
2542
2543 if (dev->phy.rev >= 3) {
2544 params->txgm = target.txgm[core];
2545 params->pga = target.pga[core];
2546 params->pad = target.pad[core];
2547 params->ipa = target.ipa[core];
2548 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2549 (params->pad << 4) | (params->ipa);
2550 for (j = 0; j < 5; j++)
2551 params->ncorr[j] = 0x79;
2552 } else {
2553 gain = (target.pad[core]) | (target.pga[core] << 4) |
2554 (target.txgm[core] << 8);
2555
2556 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2557 1 : 0;
2558 for (i = 0; i < 9; i++)
2559 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2560 break;
2561 i = min(i, 8);
2562
2563 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2564 params->pga = tbl_iqcal_gainparams[indx][i][2];
2565 params->pad = tbl_iqcal_gainparams[indx][i][3];
2566 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2567 (params->pad << 2);
2568 for (j = 0; j < 4; j++)
2569 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2570 }
2571 }
2572
2573 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2574 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2575 {
2576 struct b43_phy_n *nphy = dev->phy.n;
2577 int i;
2578 u16 scale, entry;
2579
2580 u16 tmp = nphy->txcal_bbmult;
2581 if (core == 0)
2582 tmp >>= 8;
2583 tmp &= 0xff;
2584
2585 for (i = 0; i < 18; i++) {
2586 scale = (ladder_lo[i].percent * tmp) / 100;
2587 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2588 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2589
2590 scale = (ladder_iq[i].percent * tmp) / 100;
2591 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2592 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2593 }
2594 }
2595
2596 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2597 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2598 {
2599 int i;
2600 for (i = 0; i < 15; i++)
2601 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2602 tbl_tx_filter_coef_rev4[2][i]);
2603 }
2604
2605 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2606 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2607 {
2608 int i, j;
2609 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2610 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2611
2612 for (i = 0; i < 3; i++)
2613 for (j = 0; j < 15; j++)
2614 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2615 tbl_tx_filter_coef_rev4[i][j]);
2616
2617 if (dev->phy.is_40mhz) {
2618 for (j = 0; j < 15; j++)
2619 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2620 tbl_tx_filter_coef_rev4[3][j]);
2621 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2622 for (j = 0; j < 15; j++)
2623 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2624 tbl_tx_filter_coef_rev4[5][j]);
2625 }
2626
2627 if (dev->phy.channel == 14)
2628 for (j = 0; j < 15; j++)
2629 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2630 tbl_tx_filter_coef_rev4[6][j]);
2631 }
2632
2633 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2634 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2635 {
2636 struct b43_phy_n *nphy = dev->phy.n;
2637
2638 u16 curr_gain[2];
2639 struct nphy_txgains target;
2640 const u32 *table = NULL;
2641
2642 if (!nphy->txpwrctrl) {
2643 int i;
2644
2645 if (nphy->hang_avoid)
2646 b43_nphy_stay_in_carrier_search(dev, true);
2647 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2648 if (nphy->hang_avoid)
2649 b43_nphy_stay_in_carrier_search(dev, false);
2650
2651 for (i = 0; i < 2; ++i) {
2652 if (dev->phy.rev >= 3) {
2653 target.ipa[i] = curr_gain[i] & 0x000F;
2654 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2655 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2656 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2657 } else {
2658 target.ipa[i] = curr_gain[i] & 0x0003;
2659 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2660 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2661 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2662 }
2663 }
2664 } else {
2665 int i;
2666 u16 index[2];
2667 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2668 B43_NPHY_TXPCTL_STAT_BIDX) >>
2669 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2670 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2671 B43_NPHY_TXPCTL_STAT_BIDX) >>
2672 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2673
2674 for (i = 0; i < 2; ++i) {
2675 if (dev->phy.rev >= 3) {
2676 enum ieee80211_band band =
2677 b43_current_band(dev->wl);
2678
2679 if ((nphy->ipa2g_on &&
2680 band == IEEE80211_BAND_2GHZ) ||
2681 (nphy->ipa5g_on &&
2682 band == IEEE80211_BAND_5GHZ)) {
2683 table = b43_nphy_get_ipa_gain_table(dev);
2684 } else {
2685 if (band == IEEE80211_BAND_5GHZ) {
2686 if (dev->phy.rev == 3)
2687 table = b43_ntab_tx_gain_rev3_5ghz;
2688 else if (dev->phy.rev == 4)
2689 table = b43_ntab_tx_gain_rev4_5ghz;
2690 else
2691 table = b43_ntab_tx_gain_rev5plus_5ghz;
2692 } else {
2693 table = b43_ntab_tx_gain_rev3plus_2ghz;
2694 }
2695 }
2696
2697 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2698 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2699 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2700 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2701 } else {
2702 table = b43_ntab_tx_gain_rev0_1_2;
2703
2704 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2705 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2706 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2707 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2708 }
2709 }
2710 }
2711
2712 return target;
2713 }
2714
2715 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2716 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2717 {
2718 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2719
2720 if (dev->phy.rev >= 3) {
2721 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2722 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2723 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2724 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2725 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2726 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2727 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2728 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2729 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2730 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2731 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2732 b43_nphy_reset_cca(dev);
2733 } else {
2734 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2735 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2736 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2737 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2738 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2739 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2740 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2741 }
2742 }
2743
2744 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2745 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2746 {
2747 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2748 u16 tmp;
2749
2750 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2751 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2752 if (dev->phy.rev >= 3) {
2753 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2754 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2755
2756 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2757 regs[2] = tmp;
2758 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2759
2760 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2761 regs[3] = tmp;
2762 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2763
2764 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2765 b43_phy_mask(dev, B43_NPHY_BBCFG,
2766 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2767
2768 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2769 regs[5] = tmp;
2770 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2771
2772 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2773 regs[6] = tmp;
2774 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2775 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2776 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2777
2778 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2779 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2780 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2781
2782 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2783 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2784 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2785 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2786 } else {
2787 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2788 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2789 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2790 regs[2] = tmp;
2791 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2792 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2793 regs[3] = tmp;
2794 tmp |= 0x2000;
2795 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2796 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2797 regs[4] = tmp;
2798 tmp |= 0x2000;
2799 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2800 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2801 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2802 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2803 tmp = 0x0180;
2804 else
2805 tmp = 0x0120;
2806 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2807 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2808 }
2809 }
2810
2811 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2812 static void b43_nphy_save_cal(struct b43_wldev *dev)
2813 {
2814 struct b43_phy_n *nphy = dev->phy.n;
2815
2816 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2817 u16 *txcal_radio_regs = NULL;
2818 struct b43_chanspec *iqcal_chanspec;
2819 u16 *table = NULL;
2820
2821 if (nphy->hang_avoid)
2822 b43_nphy_stay_in_carrier_search(dev, 1);
2823
2824 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2825 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2826 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2827 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2828 table = nphy->cal_cache.txcal_coeffs_2G;
2829 } else {
2830 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2831 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2832 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2833 table = nphy->cal_cache.txcal_coeffs_5G;
2834 }
2835
2836 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2837 /* TODO use some definitions */
2838 if (dev->phy.rev >= 3) {
2839 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2840 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2841 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2842 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2843 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2844 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2845 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2846 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2847 } else {
2848 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2849 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2850 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2851 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2852 }
2853 iqcal_chanspec->center_freq = dev->phy.channel_freq;
2854 iqcal_chanspec->channel_type = dev->phy.channel_type;
2855 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
2856
2857 if (nphy->hang_avoid)
2858 b43_nphy_stay_in_carrier_search(dev, 0);
2859 }
2860
2861 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2862 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2863 {
2864 struct b43_phy_n *nphy = dev->phy.n;
2865
2866 u16 coef[4];
2867 u16 *loft = NULL;
2868 u16 *table = NULL;
2869
2870 int i;
2871 u16 *txcal_radio_regs = NULL;
2872 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2873
2874 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2875 if (!nphy->iqcal_chanspec_2G.center_freq)
2876 return;
2877 table = nphy->cal_cache.txcal_coeffs_2G;
2878 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2879 } else {
2880 if (!nphy->iqcal_chanspec_5G.center_freq)
2881 return;
2882 table = nphy->cal_cache.txcal_coeffs_5G;
2883 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2884 }
2885
2886 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2887
2888 for (i = 0; i < 4; i++) {
2889 if (dev->phy.rev >= 3)
2890 table[i] = coef[i];
2891 else
2892 coef[i] = 0;
2893 }
2894
2895 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2896 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2897 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2898
2899 if (dev->phy.rev < 2)
2900 b43_nphy_tx_iq_workaround(dev);
2901
2902 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2903 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2904 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2905 } else {
2906 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2907 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2908 }
2909
2910 /* TODO use some definitions */
2911 if (dev->phy.rev >= 3) {
2912 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2913 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2914 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2915 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2916 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2917 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2918 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2919 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2920 } else {
2921 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2922 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2923 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2924 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2925 }
2926 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2927 }
2928
2929 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2930 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2931 struct nphy_txgains target,
2932 bool full, bool mphase)
2933 {
2934 struct b43_phy_n *nphy = dev->phy.n;
2935 int i;
2936 int error = 0;
2937 int freq;
2938 bool avoid = false;
2939 u8 length;
2940 u16 tmp, core, type, count, max, numb, last, cmd;
2941 const u16 *table;
2942 bool phy6or5x;
2943
2944 u16 buffer[11];
2945 u16 diq_start = 0;
2946 u16 save[2];
2947 u16 gain[2];
2948 struct nphy_iqcal_params params[2];
2949 bool updated[2] = { };
2950
2951 b43_nphy_stay_in_carrier_search(dev, true);
2952
2953 if (dev->phy.rev >= 4) {
2954 avoid = nphy->hang_avoid;
2955 nphy->hang_avoid = 0;
2956 }
2957
2958 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2959
2960 for (i = 0; i < 2; i++) {
2961 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2962 gain[i] = params[i].cal_gain;
2963 }
2964
2965 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2966
2967 b43_nphy_tx_cal_radio_setup(dev);
2968 b43_nphy_tx_cal_phy_setup(dev);
2969
2970 phy6or5x = dev->phy.rev >= 6 ||
2971 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2972 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2973 if (phy6or5x) {
2974 if (dev->phy.is_40mhz) {
2975 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2976 tbl_tx_iqlo_cal_loft_ladder_40);
2977 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2978 tbl_tx_iqlo_cal_iqimb_ladder_40);
2979 } else {
2980 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2981 tbl_tx_iqlo_cal_loft_ladder_20);
2982 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2983 tbl_tx_iqlo_cal_iqimb_ladder_20);
2984 }
2985 }
2986
2987 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2988
2989 if (!dev->phy.is_40mhz)
2990 freq = 2500;
2991 else
2992 freq = 5000;
2993
2994 if (nphy->mphase_cal_phase_id > 2)
2995 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2996 0xFFFF, 0, true, false);
2997 else
2998 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2999
3000 if (error == 0) {
3001 if (nphy->mphase_cal_phase_id > 2) {
3002 table = nphy->mphase_txcal_bestcoeffs;
3003 length = 11;
3004 if (dev->phy.rev < 3)
3005 length -= 2;
3006 } else {
3007 if (!full && nphy->txiqlocal_coeffsvalid) {
3008 table = nphy->txiqlocal_bestc;
3009 length = 11;
3010 if (dev->phy.rev < 3)
3011 length -= 2;
3012 } else {
3013 full = true;
3014 if (dev->phy.rev >= 3) {
3015 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3016 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3017 } else {
3018 table = tbl_tx_iqlo_cal_startcoefs;
3019 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3020 }
3021 }
3022 }
3023
3024 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3025
3026 if (full) {
3027 if (dev->phy.rev >= 3)
3028 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3029 else
3030 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3031 } else {
3032 if (dev->phy.rev >= 3)
3033 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3034 else
3035 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3036 }
3037
3038 if (mphase) {
3039 count = nphy->mphase_txcal_cmdidx;
3040 numb = min(max,
3041 (u16)(count + nphy->mphase_txcal_numcmds));
3042 } else {
3043 count = 0;
3044 numb = max;
3045 }
3046
3047 for (; count < numb; count++) {
3048 if (full) {
3049 if (dev->phy.rev >= 3)
3050 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3051 else
3052 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3053 } else {
3054 if (dev->phy.rev >= 3)
3055 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3056 else
3057 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3058 }
3059
3060 core = (cmd & 0x3000) >> 12;
3061 type = (cmd & 0x0F00) >> 8;
3062
3063 if (phy6or5x && updated[core] == 0) {
3064 b43_nphy_update_tx_cal_ladder(dev, core);
3065 updated[core] = 1;
3066 }
3067
3068 tmp = (params[core].ncorr[type] << 8) | 0x66;
3069 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3070
3071 if (type == 1 || type == 3 || type == 4) {
3072 buffer[0] = b43_ntab_read(dev,
3073 B43_NTAB16(15, 69 + core));
3074 diq_start = buffer[0];
3075 buffer[0] = 0;
3076 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3077 0);
3078 }
3079
3080 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3081 for (i = 0; i < 2000; i++) {
3082 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3083 if (tmp & 0xC000)
3084 break;
3085 udelay(10);
3086 }
3087
3088 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3089 buffer);
3090 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3091 buffer);
3092
3093 if (type == 1 || type == 3 || type == 4)
3094 buffer[0] = diq_start;
3095 }
3096
3097 if (mphase)
3098 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3099
3100 last = (dev->phy.rev < 3) ? 6 : 7;
3101
3102 if (!mphase || nphy->mphase_cal_phase_id == last) {
3103 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3104 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3105 if (dev->phy.rev < 3) {
3106 buffer[0] = 0;
3107 buffer[1] = 0;
3108 buffer[2] = 0;
3109 buffer[3] = 0;
3110 }
3111 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3112 buffer);
3113 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3114 buffer);
3115 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3116 buffer);
3117 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3118 buffer);
3119 length = 11;
3120 if (dev->phy.rev < 3)
3121 length -= 2;
3122 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3123 nphy->txiqlocal_bestc);
3124 nphy->txiqlocal_coeffsvalid = true;
3125 nphy->txiqlocal_chanspec.center_freq =
3126 dev->phy.channel_freq;
3127 nphy->txiqlocal_chanspec.channel_type =
3128 dev->phy.channel_type;
3129 } else {
3130 length = 11;
3131 if (dev->phy.rev < 3)
3132 length -= 2;
3133 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3134 nphy->mphase_txcal_bestcoeffs);
3135 }
3136
3137 b43_nphy_stop_playback(dev);
3138 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3139 }
3140
3141 b43_nphy_tx_cal_phy_cleanup(dev);
3142 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3143
3144 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3145 b43_nphy_tx_iq_workaround(dev);
3146
3147 if (dev->phy.rev >= 4)
3148 nphy->hang_avoid = avoid;
3149
3150 b43_nphy_stay_in_carrier_search(dev, false);
3151
3152 return error;
3153 }
3154
3155 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3156 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3157 {
3158 struct b43_phy_n *nphy = dev->phy.n;
3159 u8 i;
3160 u16 buffer[7];
3161 bool equal = true;
3162
3163 if (!nphy->txiqlocal_coeffsvalid ||
3164 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3165 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3166 return;
3167
3168 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3169 for (i = 0; i < 4; i++) {
3170 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3171 equal = false;
3172 break;
3173 }
3174 }
3175
3176 if (!equal) {
3177 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3178 nphy->txiqlocal_bestc);
3179 for (i = 0; i < 4; i++)
3180 buffer[i] = 0;
3181 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3182 buffer);
3183 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3184 &nphy->txiqlocal_bestc[5]);
3185 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3186 &nphy->txiqlocal_bestc[5]);
3187 }
3188 }
3189
3190 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3191 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3192 struct nphy_txgains target, u8 type, bool debug)
3193 {
3194 struct b43_phy_n *nphy = dev->phy.n;
3195 int i, j, index;
3196 u8 rfctl[2];
3197 u8 afectl_core;
3198 u16 tmp[6];
3199 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3200 u32 real, imag;
3201 enum ieee80211_band band;
3202
3203 u8 use;
3204 u16 cur_hpf;
3205 u16 lna[3] = { 3, 3, 1 };
3206 u16 hpf1[3] = { 7, 2, 0 };
3207 u16 hpf2[3] = { 2, 0, 0 };
3208 u32 power[3] = { };
3209 u16 gain_save[2];
3210 u16 cal_gain[2];
3211 struct nphy_iqcal_params cal_params[2];
3212 struct nphy_iq_est est;
3213 int ret = 0;
3214 bool playtone = true;
3215 int desired = 13;
3216
3217 b43_nphy_stay_in_carrier_search(dev, 1);
3218
3219 if (dev->phy.rev < 2)
3220 b43_nphy_reapply_tx_cal_coeffs(dev);
3221 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3222 for (i = 0; i < 2; i++) {
3223 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3224 cal_gain[i] = cal_params[i].cal_gain;
3225 }
3226 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3227
3228 for (i = 0; i < 2; i++) {
3229 if (i == 0) {
3230 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3231 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3232 afectl_core = B43_NPHY_AFECTL_C1;
3233 } else {
3234 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3235 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3236 afectl_core = B43_NPHY_AFECTL_C2;
3237 }
3238
3239 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3240 tmp[2] = b43_phy_read(dev, afectl_core);
3241 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3242 tmp[4] = b43_phy_read(dev, rfctl[0]);
3243 tmp[5] = b43_phy_read(dev, rfctl[1]);
3244
3245 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3246 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3247 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3248 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3249 (1 - i));
3250 b43_phy_set(dev, afectl_core, 0x0006);
3251 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3252
3253 band = b43_current_band(dev->wl);
3254
3255 if (nphy->rxcalparams & 0xFF000000) {
3256 if (band == IEEE80211_BAND_5GHZ)
3257 b43_phy_write(dev, rfctl[0], 0x140);
3258 else
3259 b43_phy_write(dev, rfctl[0], 0x110);
3260 } else {
3261 if (band == IEEE80211_BAND_5GHZ)
3262 b43_phy_write(dev, rfctl[0], 0x180);
3263 else
3264 b43_phy_write(dev, rfctl[0], 0x120);
3265 }
3266
3267 if (band == IEEE80211_BAND_5GHZ)
3268 b43_phy_write(dev, rfctl[1], 0x148);
3269 else
3270 b43_phy_write(dev, rfctl[1], 0x114);
3271
3272 if (nphy->rxcalparams & 0x10000) {
3273 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3274 (i + 1));
3275 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3276 (2 - i));
3277 }
3278
3279 for (j = 0; j < 4; j++) {
3280 if (j < 3) {
3281 cur_lna = lna[j];
3282 cur_hpf1 = hpf1[j];
3283 cur_hpf2 = hpf2[j];
3284 } else {
3285 if (power[1] > 10000) {
3286 use = 1;
3287 cur_hpf = cur_hpf1;
3288 index = 2;
3289 } else {
3290 if (power[0] > 10000) {
3291 use = 1;
3292 cur_hpf = cur_hpf1;
3293 index = 1;
3294 } else {
3295 index = 0;
3296 use = 2;
3297 cur_hpf = cur_hpf2;
3298 }
3299 }
3300 cur_lna = lna[index];
3301 cur_hpf1 = hpf1[index];
3302 cur_hpf2 = hpf2[index];
3303 cur_hpf += desired - hweight32(power[index]);
3304 cur_hpf = clamp_val(cur_hpf, 0, 10);
3305 if (use == 1)
3306 cur_hpf1 = cur_hpf;
3307 else
3308 cur_hpf2 = cur_hpf;
3309 }
3310
3311 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3312 (cur_lna << 2));
3313 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3314 false);
3315 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3316 b43_nphy_stop_playback(dev);
3317
3318 if (playtone) {
3319 ret = b43_nphy_tx_tone(dev, 4000,
3320 (nphy->rxcalparams & 0xFFFF),
3321 false, false);
3322 playtone = false;
3323 } else {
3324 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3325 false, false);
3326 }
3327
3328 if (ret == 0) {
3329 if (j < 3) {
3330 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3331 false);
3332 if (i == 0) {
3333 real = est.i0_pwr;
3334 imag = est.q0_pwr;
3335 } else {
3336 real = est.i1_pwr;
3337 imag = est.q1_pwr;
3338 }
3339 power[i] = ((real + imag) / 1024) + 1;
3340 } else {
3341 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3342 }
3343 b43_nphy_stop_playback(dev);
3344 }
3345
3346 if (ret != 0)
3347 break;
3348 }
3349
3350 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3351 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3352 b43_phy_write(dev, rfctl[1], tmp[5]);
3353 b43_phy_write(dev, rfctl[0], tmp[4]);
3354 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3355 b43_phy_write(dev, afectl_core, tmp[2]);
3356 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3357
3358 if (ret != 0)
3359 break;
3360 }
3361
3362 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3363 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3364 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3365
3366 b43_nphy_stay_in_carrier_search(dev, 0);
3367
3368 return ret;
3369 }
3370
3371 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3372 struct nphy_txgains target, u8 type, bool debug)
3373 {
3374 return -1;
3375 }
3376
3377 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3378 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3379 struct nphy_txgains target, u8 type, bool debug)
3380 {
3381 if (dev->phy.rev >= 3)
3382 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3383 else
3384 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3385 }
3386
3387 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3388 static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3389 {
3390 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3391 if (on)
3392 tmslow |= B43_TMSLOW_MACPHYCLKEN;
3393 else
3394 tmslow &= ~B43_TMSLOW_MACPHYCLKEN;
3395 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3396 }
3397
3398 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3399 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3400 {
3401 struct b43_phy *phy = &dev->phy;
3402 struct b43_phy_n *nphy = phy->n;
3403 /* u16 buf[16]; it's rev3+ */
3404
3405 nphy->phyrxchain = mask;
3406
3407 if (0 /* FIXME clk */)
3408 return;
3409
3410 b43_mac_suspend(dev);
3411
3412 if (nphy->hang_avoid)
3413 b43_nphy_stay_in_carrier_search(dev, true);
3414
3415 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3416 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3417
3418 if ((mask & 0x3) != 0x3) {
3419 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3420 if (dev->phy.rev >= 3) {
3421 /* TODO */
3422 }
3423 } else {
3424 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3425 if (dev->phy.rev >= 3) {
3426 /* TODO */
3427 }
3428 }
3429
3430 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3431
3432 if (nphy->hang_avoid)
3433 b43_nphy_stay_in_carrier_search(dev, false);
3434
3435 b43_mac_enable(dev);
3436 }
3437
3438 /*
3439 * Init N-PHY
3440 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3441 */
3442 int b43_phy_initn(struct b43_wldev *dev)
3443 {
3444 struct ssb_bus *bus = dev->dev->bus;
3445 struct b43_phy *phy = &dev->phy;
3446 struct b43_phy_n *nphy = phy->n;
3447 u8 tx_pwr_state;
3448 struct nphy_txgains target;
3449 u16 tmp;
3450 enum ieee80211_band tmp2;
3451 bool do_rssi_cal;
3452
3453 u16 clip[2];
3454 bool do_cal = false;
3455
3456 if ((dev->phy.rev >= 3) &&
3457 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3458 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3459 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3460 }
3461 nphy->deaf_count = 0;
3462 b43_nphy_tables_init(dev);
3463 nphy->crsminpwr_adjusted = false;
3464 nphy->noisevars_adjusted = false;
3465
3466 /* Clear all overrides */
3467 if (dev->phy.rev >= 3) {
3468 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3469 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3470 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3471 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3472 } else {
3473 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3474 }
3475 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3476 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3477 if (dev->phy.rev < 6) {
3478 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3479 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3480 }
3481 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3482 ~(B43_NPHY_RFSEQMODE_CAOVER |
3483 B43_NPHY_RFSEQMODE_TROVER));
3484 if (dev->phy.rev >= 3)
3485 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3486 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3487
3488 if (dev->phy.rev <= 2) {
3489 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3490 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3491 ~B43_NPHY_BPHY_CTL3_SCALE,
3492 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3493 }
3494 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3495 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3496
3497 if (bus->sprom.boardflags2_lo & 0x100 ||
3498 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3499 bus->boardinfo.type == 0x8B))
3500 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3501 else
3502 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3503 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3504 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3505 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3506
3507 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3508 b43_nphy_update_txrx_chain(dev);
3509
3510 if (phy->rev < 2) {
3511 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3512 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3513 }
3514
3515 tmp2 = b43_current_band(dev->wl);
3516 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3517 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3518 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3519 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3520 nphy->papd_epsilon_offset[0] << 7);
3521 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3522 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3523 nphy->papd_epsilon_offset[1] << 7);
3524 b43_nphy_int_pa_set_tx_dig_filters(dev);
3525 } else if (phy->rev >= 5) {
3526 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3527 }
3528
3529 b43_nphy_workarounds(dev);
3530
3531 /* Reset CCA, in init code it differs a little from standard way */
3532 b43_nphy_bmac_clock_fgc(dev, 1);
3533 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3534 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3535 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3536 b43_nphy_bmac_clock_fgc(dev, 0);
3537
3538 b43_nphy_mac_phy_clock_set(dev, true);
3539
3540 b43_nphy_pa_override(dev, false);
3541 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3542 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3543 b43_nphy_pa_override(dev, true);
3544
3545 b43_nphy_classifier(dev, 0, 0);
3546 b43_nphy_read_clip_detection(dev, clip);
3547 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3548 b43_nphy_bphy_init(dev);
3549
3550 tx_pwr_state = nphy->txpwrctrl;
3551 b43_nphy_tx_power_ctrl(dev, false);
3552 b43_nphy_tx_power_fix(dev);
3553 /* TODO N PHY TX Power Control Idle TSSI */
3554 /* TODO N PHY TX Power Control Setup */
3555
3556 if (phy->rev >= 3) {
3557 /* TODO */
3558 } else {
3559 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3560 b43_ntab_tx_gain_rev0_1_2);
3561 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3562 b43_ntab_tx_gain_rev0_1_2);
3563 }
3564
3565 if (nphy->phyrxchain != 3)
3566 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3567 if (nphy->mphase_cal_phase_id > 0)
3568 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3569
3570 do_rssi_cal = false;
3571 if (phy->rev >= 3) {
3572 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3573 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3574 else
3575 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3576
3577 if (do_rssi_cal)
3578 b43_nphy_rssi_cal(dev);
3579 else
3580 b43_nphy_restore_rssi_cal(dev);
3581 } else {
3582 b43_nphy_rssi_cal(dev);
3583 }
3584
3585 if (!((nphy->measure_hold & 0x6) != 0)) {
3586 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3587 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3588 else
3589 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3590
3591 if (nphy->mute)
3592 do_cal = false;
3593
3594 if (do_cal) {
3595 target = b43_nphy_get_tx_gains(dev);
3596
3597 if (nphy->antsel_type == 2)
3598 b43_nphy_superswitch_init(dev, true);
3599 if (nphy->perical != 2) {
3600 b43_nphy_rssi_cal(dev);
3601 if (phy->rev >= 3) {
3602 nphy->cal_orig_pwr_idx[0] =
3603 nphy->txpwrindex[0].index_internal;
3604 nphy->cal_orig_pwr_idx[1] =
3605 nphy->txpwrindex[1].index_internal;
3606 /* TODO N PHY Pre Calibrate TX Gain */
3607 target = b43_nphy_get_tx_gains(dev);
3608 }
3609 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3610 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3611 b43_nphy_save_cal(dev);
3612 } else if (nphy->mphase_cal_phase_id == 0)
3613 ;/* N PHY Periodic Calibration with arg 3 */
3614 } else {
3615 b43_nphy_restore_cal(dev);
3616 }
3617 }
3618
3619 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3620 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3621 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3622 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3623 if (phy->rev >= 3 && phy->rev <= 6)
3624 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3625 b43_nphy_tx_lp_fbw(dev);
3626 if (phy->rev >= 3)
3627 b43_nphy_spur_workaround(dev);
3628
3629 return 0;
3630 }
3631
3632 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3633 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3634 const struct b43_phy_n_sfo_cfg *e,
3635 struct ieee80211_channel *new_channel)
3636 {
3637 struct b43_phy *phy = &dev->phy;
3638 struct b43_phy_n *nphy = dev->phy.n;
3639
3640 u16 old_band_5ghz;
3641 u32 tmp32;
3642
3643 old_band_5ghz =
3644 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3645 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3646 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3647 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3648 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3649 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3650 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3651 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3652 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3653 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3654 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3655 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3656 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3657 }
3658
3659 b43_chantab_phy_upload(dev, e);
3660
3661 if (new_channel->hw_value == 14) {
3662 b43_nphy_classifier(dev, 2, 0);
3663 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3664 } else {
3665 b43_nphy_classifier(dev, 2, 2);
3666 if (new_channel->band == IEEE80211_BAND_2GHZ)
3667 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3668 }
3669
3670 if (!nphy->txpwrctrl)
3671 b43_nphy_tx_power_fix(dev);
3672
3673 if (dev->phy.rev < 3)
3674 b43_nphy_adjust_lna_gain_table(dev);
3675
3676 b43_nphy_tx_lp_fbw(dev);
3677
3678 if (dev->phy.rev >= 3 && 0) {
3679 /* TODO */
3680 }
3681
3682 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3683
3684 if (phy->rev >= 3)
3685 b43_nphy_spur_workaround(dev);
3686 }
3687
3688 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3689 static int b43_nphy_set_channel(struct b43_wldev *dev,
3690 struct ieee80211_channel *channel,
3691 enum nl80211_channel_type channel_type)
3692 {
3693 struct b43_phy *phy = &dev->phy;
3694
3695 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3696 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3697
3698 u8 tmp;
3699
3700 if (dev->phy.rev >= 3) {
3701 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3702 channel->center_freq);
3703 if (!tabent_r3)
3704 return -ESRCH;
3705 } else {
3706 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3707 channel->hw_value);
3708 if (!tabent_r2)
3709 return -ESRCH;
3710 }
3711
3712 /* Channel is set later in common code, but we need to set it on our
3713 own to let this function's subcalls work properly. */
3714 phy->channel = channel->hw_value;
3715 phy->channel_freq = channel->center_freq;
3716
3717 if (b43_channel_type_is_40mhz(phy->channel_type) !=
3718 b43_channel_type_is_40mhz(channel_type))
3719 ; /* TODO: BMAC BW Set (channel_type) */
3720
3721 if (channel_type == NL80211_CHAN_HT40PLUS)
3722 b43_phy_set(dev, B43_NPHY_RXCTL,
3723 B43_NPHY_RXCTL_BSELU20);
3724 else if (channel_type == NL80211_CHAN_HT40MINUS)
3725 b43_phy_mask(dev, B43_NPHY_RXCTL,
3726 ~B43_NPHY_RXCTL_BSELU20);
3727
3728 if (dev->phy.rev >= 3) {
3729 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3730 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3731 b43_radio_2056_setup(dev, tabent_r3);
3732 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3733 } else {
3734 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3735 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3736 b43_radio_2055_setup(dev, tabent_r2);
3737 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3738 }
3739
3740 return 0;
3741 }
3742
3743 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3744 {
3745 struct b43_phy_n *nphy;
3746
3747 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3748 if (!nphy)
3749 return -ENOMEM;
3750 dev->phy.n = nphy;
3751
3752 return 0;
3753 }
3754
3755 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3756 {
3757 struct b43_phy *phy = &dev->phy;
3758 struct b43_phy_n *nphy = phy->n;
3759
3760 memset(nphy, 0, sizeof(*nphy));
3761
3762 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3763 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3764 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3765 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3766 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3767 }
3768
3769 static void b43_nphy_op_free(struct b43_wldev *dev)
3770 {
3771 struct b43_phy *phy = &dev->phy;
3772 struct b43_phy_n *nphy = phy->n;
3773
3774 kfree(nphy);
3775 phy->n = NULL;
3776 }
3777
3778 static int b43_nphy_op_init(struct b43_wldev *dev)
3779 {
3780 return b43_phy_initn(dev);
3781 }
3782
3783 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3784 {
3785 #if B43_DEBUG
3786 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3787 /* OFDM registers are onnly available on A/G-PHYs */
3788 b43err(dev->wl, "Invalid OFDM PHY access at "
3789 "0x%04X on N-PHY\n", offset);
3790 dump_stack();
3791 }
3792 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3793 /* Ext-G registers are only available on G-PHYs */
3794 b43err(dev->wl, "Invalid EXT-G PHY access at "
3795 "0x%04X on N-PHY\n", offset);
3796 dump_stack();
3797 }
3798 #endif /* B43_DEBUG */
3799 }
3800
3801 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3802 {
3803 check_phyreg(dev, reg);
3804 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3805 return b43_read16(dev, B43_MMIO_PHY_DATA);
3806 }
3807
3808 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3809 {
3810 check_phyreg(dev, reg);
3811 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3812 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3813 }
3814
3815 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3816 u16 set)
3817 {
3818 check_phyreg(dev, reg);
3819 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3820 b43_write16(dev, B43_MMIO_PHY_DATA,
3821 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3822 }
3823
3824 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3825 {
3826 /* Register 1 is a 32-bit register. */
3827 B43_WARN_ON(reg == 1);
3828 /* N-PHY needs 0x100 for read access */
3829 reg |= 0x100;
3830
3831 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3832 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3833 }
3834
3835 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3836 {
3837 /* Register 1 is a 32-bit register. */
3838 B43_WARN_ON(reg == 1);
3839
3840 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3841 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3842 }
3843
3844 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3845 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3846 bool blocked)
3847 {
3848 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3849 b43err(dev->wl, "MAC not suspended\n");
3850
3851 if (blocked) {
3852 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3853 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3854 if (dev->phy.rev >= 3) {
3855 b43_radio_mask(dev, 0x09, ~0x2);
3856
3857 b43_radio_write(dev, 0x204D, 0);
3858 b43_radio_write(dev, 0x2053, 0);
3859 b43_radio_write(dev, 0x2058, 0);
3860 b43_radio_write(dev, 0x205E, 0);
3861 b43_radio_mask(dev, 0x2062, ~0xF0);
3862 b43_radio_write(dev, 0x2064, 0);
3863
3864 b43_radio_write(dev, 0x304D, 0);
3865 b43_radio_write(dev, 0x3053, 0);
3866 b43_radio_write(dev, 0x3058, 0);
3867 b43_radio_write(dev, 0x305E, 0);
3868 b43_radio_mask(dev, 0x3062, ~0xF0);
3869 b43_radio_write(dev, 0x3064, 0);
3870 }
3871 } else {
3872 if (dev->phy.rev >= 3) {
3873 b43_radio_init2056(dev);
3874 b43_switch_channel(dev, dev->phy.channel);
3875 } else {
3876 b43_radio_init2055(dev);
3877 }
3878 }
3879 }
3880
3881 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3882 {
3883 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3884 on ? 0 : 0x7FFF);
3885 }
3886
3887 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3888 unsigned int new_channel)
3889 {
3890 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3891 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
3892
3893 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3894 if ((new_channel < 1) || (new_channel > 14))
3895 return -EINVAL;
3896 } else {
3897 if (new_channel > 200)
3898 return -EINVAL;
3899 }
3900
3901 return b43_nphy_set_channel(dev, channel, channel_type);
3902 }
3903
3904 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3905 {
3906 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3907 return 1;
3908 return 36;
3909 }
3910
3911 const struct b43_phy_operations b43_phyops_n = {
3912 .allocate = b43_nphy_op_allocate,
3913 .free = b43_nphy_op_free,
3914 .prepare_structs = b43_nphy_op_prepare_structs,
3915 .init = b43_nphy_op_init,
3916 .phy_read = b43_nphy_op_read,
3917 .phy_write = b43_nphy_op_write,
3918 .phy_maskset = b43_nphy_op_maskset,
3919 .radio_read = b43_nphy_op_radio_read,
3920 .radio_write = b43_nphy_op_radio_write,
3921 .software_rfkill = b43_nphy_op_software_rfkill,
3922 .switch_analog = b43_nphy_op_switch_analog,
3923 .switch_channel = b43_nphy_op_switch_channel,
3924 .get_default_chan = b43_nphy_op_get_default_chan,
3925 .recalc_txpower = b43_nphy_op_recalc_txpower,
3926 .adjust_txpower = b43_nphy_op_adjust_txpower,
3927 };
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