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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / wireless / ipw2x00 / ipw2200.h
blobd7d049c7a4fa93ae3be77d11632bda0a4c4863ac
1 /******************************************************************************
2
3 Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
7 published by the Free Software Foundation.
8
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 more details.
13
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc., 59
16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17
18 The full GNU General Public License is included in this distribution in the
19 file called LICENSE.
20
21 Contact Information:
22 Intel Linux Wireless <ilw@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25 ******************************************************************************/
26
27 #ifndef __ipw2200_h__
28 #define __ipw2200_h__
29
30 #define WEXT_USECHANNELS 1
31
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/init.h>
35 #include <linux/mutex.h>
36
37 #include <linux/pci.h>
38 #include <linux/netdevice.h>
39 #include <linux/ethtool.h>
40 #include <linux/skbuff.h>
41 #include <linux/etherdevice.h>
42 #include <linux/delay.h>
43 #include <linux/random.h>
44 #include <linux/dma-mapping.h>
45
46 #include <linux/firmware.h>
47 #include <linux/wireless.h>
48 #include <linux/jiffies.h>
49 #include <asm/io.h>
50
51 #include <net/lib80211.h>
52 #include <net/ieee80211_radiotap.h>
53
54 #define DRV_NAME "ipw2200"
55
56 #include <linux/workqueue.h>
57
58 #include "libipw.h"
59
60 /* Authentication and Association States */
61 enum connection_manager_assoc_states {
62 CMAS_INIT = 0,
63 CMAS_TX_AUTH_SEQ_1,
64 CMAS_RX_AUTH_SEQ_2,
65 CMAS_AUTH_SEQ_1_PASS,
66 CMAS_AUTH_SEQ_1_FAIL,
67 CMAS_TX_AUTH_SEQ_3,
68 CMAS_RX_AUTH_SEQ_4,
69 CMAS_AUTH_SEQ_2_PASS,
70 CMAS_AUTH_SEQ_2_FAIL,
71 CMAS_AUTHENTICATED,
72 CMAS_TX_ASSOC,
73 CMAS_RX_ASSOC_RESP,
74 CMAS_ASSOCIATED,
75 CMAS_LAST
76 };
77
78 #define IPW_WAIT (1<<0)
79 #define IPW_QUIET (1<<1)
80 #define IPW_ROAMING (1<<2)
81
82 #define IPW_POWER_MODE_CAM 0x00 //(always on)
83 #define IPW_POWER_INDEX_1 0x01
84 #define IPW_POWER_INDEX_2 0x02
85 #define IPW_POWER_INDEX_3 0x03
86 #define IPW_POWER_INDEX_4 0x04
87 #define IPW_POWER_INDEX_5 0x05
88 #define IPW_POWER_AC 0x06
89 #define IPW_POWER_BATTERY 0x07
90 #define IPW_POWER_LIMIT 0x07
91 #define IPW_POWER_MASK 0x0F
92 #define IPW_POWER_ENABLED 0x10
93 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
94
95 #define IPW_CMD_HOST_COMPLETE 2
96 #define IPW_CMD_POWER_DOWN 4
97 #define IPW_CMD_SYSTEM_CONFIG 6
98 #define IPW_CMD_MULTICAST_ADDRESS 7
99 #define IPW_CMD_SSID 8
100 #define IPW_CMD_ADAPTER_ADDRESS 11
101 #define IPW_CMD_PORT_TYPE 12
102 #define IPW_CMD_RTS_THRESHOLD 15
103 #define IPW_CMD_FRAG_THRESHOLD 16
104 #define IPW_CMD_POWER_MODE 17
105 #define IPW_CMD_WEP_KEY 18
106 #define IPW_CMD_TGI_TX_KEY 19
107 #define IPW_CMD_SCAN_REQUEST 20
108 #define IPW_CMD_ASSOCIATE 21
109 #define IPW_CMD_SUPPORTED_RATES 22
110 #define IPW_CMD_SCAN_ABORT 23
111 #define IPW_CMD_TX_FLUSH 24
112 #define IPW_CMD_QOS_PARAMETERS 25
113 #define IPW_CMD_SCAN_REQUEST_EXT 26
114 #define IPW_CMD_DINO_CONFIG 30
115 #define IPW_CMD_RSN_CAPABILITIES 31
116 #define IPW_CMD_RX_KEY 32
117 #define IPW_CMD_CARD_DISABLE 33
118 #define IPW_CMD_SEED_NUMBER 34
119 #define IPW_CMD_TX_POWER 35
120 #define IPW_CMD_COUNTRY_INFO 36
121 #define IPW_CMD_AIRONET_INFO 37
122 #define IPW_CMD_AP_TX_POWER 38
123 #define IPW_CMD_CCKM_INFO 39
124 #define IPW_CMD_CCX_VER_INFO 40
125 #define IPW_CMD_SET_CALIBRATION 41
126 #define IPW_CMD_SENSITIVITY_CALIB 42
127 #define IPW_CMD_RETRY_LIMIT 51
128 #define IPW_CMD_IPW_PRE_POWER_DOWN 58
129 #define IPW_CMD_VAP_BEACON_TEMPLATE 60
130 #define IPW_CMD_VAP_DTIM_PERIOD 61
131 #define IPW_CMD_EXT_SUPPORTED_RATES 62
132 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
133 #define IPW_CMD_VAP_QUIET_INTERVALS 64
134 #define IPW_CMD_VAP_CHANNEL_SWITCH 65
135 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66
136 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67
137 #define IPW_CMD_VAP_CF_PARAM_SET 68
138 #define IPW_CMD_VAP_SET_BEACONING_STATE 69
139 #define IPW_CMD_MEASUREMENT 80
140 #define IPW_CMD_POWER_CAPABILITY 81
141 #define IPW_CMD_SUPPORTED_CHANNELS 82
142 #define IPW_CMD_TPC_REPORT 83
143 #define IPW_CMD_WME_INFO 84
144 #define IPW_CMD_PRODUCTION_COMMAND 85
145 #define IPW_CMD_LINKSYS_EOU_INFO 90
146
147 #define RFD_SIZE 4
148 #define NUM_TFD_CHUNKS 6
149
150 #define TX_QUEUE_SIZE 32
151 #define RX_QUEUE_SIZE 32
152
153 #define DINO_CMD_WEP_KEY 0x08
154 #define DINO_CMD_TX 0x0B
155 #define DCT_ANTENNA_A 0x01
156 #define DCT_ANTENNA_B 0x02
157
158 #define IPW_A_MODE 0
159 #define IPW_B_MODE 1
160 #define IPW_G_MODE 2
161
162 /*
163 * TX Queue Flag Definitions
164 */
165
166 /* tx wep key definition */
167 #define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
168 #define DCT_WEP_KEY_64Bit 0x40
169 #define DCT_WEP_KEY_128Bit 0x80
170 #define DCT_WEP_KEY_128bitIV 0xC0
171 #define DCT_WEP_KEY_SIZE_MASK 0xC0
172
173 #define DCT_WEP_KEY_INDEX_MASK 0x0F
174 #define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
175
176 /* abort attempt if mgmt frame is rx'd */
177 #define DCT_FLAG_ABORT_MGMT 0x01
178
179 /* require CTS */
180 #define DCT_FLAG_CTS_REQUIRED 0x02
181
182 /* use short preamble */
183 #define DCT_FLAG_LONG_PREAMBLE 0x00
184 #define DCT_FLAG_SHORT_PREAMBLE 0x04
185
186 /* RTS/CTS first */
187 #define DCT_FLAG_RTS_REQD 0x08
188
189 /* dont calculate duration field */
190 #define DCT_FLAG_DUR_SET 0x10
191
192 /* even if MAC WEP set (allows pre-encrypt) */
193 #define DCT_FLAG_NO_WEP 0x20
194
195 /* overwrite TSF field */
196 #define DCT_FLAG_TSF_REQD 0x40
197
198 /* ACK rx is expected to follow */
199 #define DCT_FLAG_ACK_REQD 0x80
200
201 /* TX flags extension */
202 #define DCT_FLAG_EXT_MODE_CCK 0x01
203 #define DCT_FLAG_EXT_MODE_OFDM 0x00
204
205 #define DCT_FLAG_EXT_SECURITY_WEP 0x00
206 #define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP
207 #define DCT_FLAG_EXT_SECURITY_CKIP 0x04
208 #define DCT_FLAG_EXT_SECURITY_CCM 0x08
209 #define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
210 #define DCT_FLAG_EXT_SECURITY_MASK 0x0C
211
212 #define DCT_FLAG_EXT_QOS_ENABLED 0x10
213
214 #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
215 #define DCT_FLAG_EXT_HC_SIFS 0x20
216 #define DCT_FLAG_EXT_HC_PIFS 0x40
217
218 #define TX_RX_TYPE_MASK 0xFF
219 #define TX_FRAME_TYPE 0x00
220 #define TX_HOST_COMMAND_TYPE 0x01
221 #define RX_FRAME_TYPE 0x09
222 #define RX_HOST_NOTIFICATION_TYPE 0x03
223 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
224 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
225 #define TFD_NEED_IRQ_MASK 0x04
226
227 #define HOST_CMD_DINO_CONFIG 30
228
229 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
230 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
231 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
232 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
233 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
234 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
235 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
236 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
237 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
238 #define HOST_NOTIFICATION_TX_STATUS 19
239 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
240 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
241 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
242 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
243 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
244 #define HOST_NOTIFICATION_NOISE_STATS 25
245 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
246 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
247
248 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
249 #define IPW_MB_SCAN_CANCEL_THRESHOLD 3
250 #define IPW_MB_ROAMING_THRESHOLD_MIN 1
251 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
252 #define IPW_MB_ROAMING_THRESHOLD_MAX 30
253 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 3*IPW_MB_ROAMING_THRESHOLD_DEFAULT
254 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
255
256 #define MACADRR_BYTE_LEN 6
257
258 #define DCR_TYPE_AP 0x01
259 #define DCR_TYPE_WLAP 0x02
260 #define DCR_TYPE_MU_ESS 0x03
261 #define DCR_TYPE_MU_IBSS 0x04
262 #define DCR_TYPE_MU_PIBSS 0x05
263 #define DCR_TYPE_SNIFFER 0x06
264 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
265
266 /* QoS definitions */
267
268 #define CW_MIN_OFDM 15
269 #define CW_MAX_OFDM 1023
270 #define CW_MIN_CCK 31
271 #define CW_MAX_CCK 1023
272
273 #define QOS_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
274 #define QOS_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
275 #define QOS_TX2_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
276 #define QOS_TX3_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/4 - 1)
277
278 #define QOS_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
279 #define QOS_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
280 #define QOS_TX2_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
281 #define QOS_TX3_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/4 - 1)
282
283 #define QOS_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
284 #define QOS_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
285 #define QOS_TX2_CW_MAX_OFDM cpu_to_le16(CW_MIN_OFDM)
286 #define QOS_TX3_CW_MAX_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
287
288 #define QOS_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
289 #define QOS_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
290 #define QOS_TX2_CW_MAX_CCK cpu_to_le16(CW_MIN_CCK)
291 #define QOS_TX3_CW_MAX_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
292
293 #define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)
294 #define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)
295 #define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)
296 #define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)
297
298 #define QOS_TX0_ACM 0
299 #define QOS_TX1_ACM 0
300 #define QOS_TX2_ACM 0
301 #define QOS_TX3_ACM 0
302
303 #define QOS_TX0_TXOP_LIMIT_CCK 0
304 #define QOS_TX1_TXOP_LIMIT_CCK 0
305 #define QOS_TX2_TXOP_LIMIT_CCK cpu_to_le16(6016)
306 #define QOS_TX3_TXOP_LIMIT_CCK cpu_to_le16(3264)
307
308 #define QOS_TX0_TXOP_LIMIT_OFDM 0
309 #define QOS_TX1_TXOP_LIMIT_OFDM 0
310 #define QOS_TX2_TXOP_LIMIT_OFDM cpu_to_le16(3008)
311 #define QOS_TX3_TXOP_LIMIT_OFDM cpu_to_le16(1504)
312
313 #define DEF_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
314 #define DEF_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
315 #define DEF_TX2_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
316 #define DEF_TX3_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
317
318 #define DEF_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
319 #define DEF_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
320 #define DEF_TX2_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
321 #define DEF_TX3_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
322
323 #define DEF_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
324 #define DEF_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
325 #define DEF_TX2_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
326 #define DEF_TX3_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
327
328 #define DEF_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
329 #define DEF_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
330 #define DEF_TX2_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
331 #define DEF_TX3_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
332
333 #define DEF_TX0_AIFS 0
334 #define DEF_TX1_AIFS 0
335 #define DEF_TX2_AIFS 0
336 #define DEF_TX3_AIFS 0
337
338 #define DEF_TX0_ACM 0
339 #define DEF_TX1_ACM 0
340 #define DEF_TX2_ACM 0
341 #define DEF_TX3_ACM 0
342
343 #define DEF_TX0_TXOP_LIMIT_CCK 0
344 #define DEF_TX1_TXOP_LIMIT_CCK 0
345 #define DEF_TX2_TXOP_LIMIT_CCK 0
346 #define DEF_TX3_TXOP_LIMIT_CCK 0
347
348 #define DEF_TX0_TXOP_LIMIT_OFDM 0
349 #define DEF_TX1_TXOP_LIMIT_OFDM 0
350 #define DEF_TX2_TXOP_LIMIT_OFDM 0
351 #define DEF_TX3_TXOP_LIMIT_OFDM 0
352
353 #define QOS_QOS_SETS 3
354 #define QOS_PARAM_SET_ACTIVE 0
355 #define QOS_PARAM_SET_DEF_CCK 1
356 #define QOS_PARAM_SET_DEF_OFDM 2
357
358 #define CTRL_QOS_NO_ACK (0x0020)
359
360 #define IPW_TX_QUEUE_1 1
361 #define IPW_TX_QUEUE_2 2
362 #define IPW_TX_QUEUE_3 3
363 #define IPW_TX_QUEUE_4 4
364
365 /* QoS sturctures */
366 struct ipw_qos_info {
367 int qos_enable;
368 struct libipw_qos_parameters *def_qos_parm_OFDM;
369 struct libipw_qos_parameters *def_qos_parm_CCK;
370 u32 burst_duration_CCK;
371 u32 burst_duration_OFDM;
372 u16 qos_no_ack_mask;
373 int burst_enable;
374 };
375
376 /**************************************************************/
377 /**
378 * Generic queue structure
379 *
380 * Contains common data for Rx and Tx queues
381 */
382 struct clx2_queue {
383 int n_bd; /**< number of BDs in this queue */
384 int first_empty; /**< 1-st empty entry (index) */
385 int last_used; /**< last used entry (index) */
386 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
387 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
388 dma_addr_t dma_addr; /**< physical addr for BD's */
389 int low_mark; /**< low watermark, resume queue if free space more than this */
390 int high_mark; /**< high watermark, stop queue if free space less than this */
391 } __packed; /* XXX */
392
393 struct machdr32 {
394 __le16 frame_ctl;
395 __le16 duration; // watch out for endians!
396 u8 addr1[MACADRR_BYTE_LEN];
397 u8 addr2[MACADRR_BYTE_LEN];
398 u8 addr3[MACADRR_BYTE_LEN];
399 __le16 seq_ctrl; // more endians!
400 u8 addr4[MACADRR_BYTE_LEN];
401 __le16 qos_ctrl;
402 } __packed;
403
404 struct machdr30 {
405 __le16 frame_ctl;
406 __le16 duration; // watch out for endians!
407 u8 addr1[MACADRR_BYTE_LEN];
408 u8 addr2[MACADRR_BYTE_LEN];
409 u8 addr3[MACADRR_BYTE_LEN];
410 __le16 seq_ctrl; // more endians!
411 u8 addr4[MACADRR_BYTE_LEN];
412 } __packed;
413
414 struct machdr26 {
415 __le16 frame_ctl;
416 __le16 duration; // watch out for endians!
417 u8 addr1[MACADRR_BYTE_LEN];
418 u8 addr2[MACADRR_BYTE_LEN];
419 u8 addr3[MACADRR_BYTE_LEN];
420 __le16 seq_ctrl; // more endians!
421 __le16 qos_ctrl;
422 } __packed;
423
424 struct machdr24 {
425 __le16 frame_ctl;
426 __le16 duration; // watch out for endians!
427 u8 addr1[MACADRR_BYTE_LEN];
428 u8 addr2[MACADRR_BYTE_LEN];
429 u8 addr3[MACADRR_BYTE_LEN];
430 __le16 seq_ctrl; // more endians!
431 } __packed;
432
433 // TX TFD with 32 byte MAC Header
434 struct tx_tfd_32 {
435 struct machdr32 mchdr; // 32
436 __le32 uivplaceholder[2]; // 8
437 } __packed;
438
439 // TX TFD with 30 byte MAC Header
440 struct tx_tfd_30 {
441 struct machdr30 mchdr; // 30
442 u8 reserved[2]; // 2
443 __le32 uivplaceholder[2]; // 8
444 } __packed;
445
446 // tx tfd with 26 byte mac header
447 struct tx_tfd_26 {
448 struct machdr26 mchdr; // 26
449 u8 reserved1[2]; // 2
450 __le32 uivplaceholder[2]; // 8
451 u8 reserved2[4]; // 4
452 } __packed;
453
454 // tx tfd with 24 byte mac header
455 struct tx_tfd_24 {
456 struct machdr24 mchdr; // 24
457 __le32 uivplaceholder[2]; // 8
458 u8 reserved[8]; // 8
459 } __packed;
460
461 #define DCT_WEP_KEY_FIELD_LENGTH 16
462
463 struct tfd_command {
464 u8 index;
465 u8 length;
466 __le16 reserved;
467 u8 payload[0];
468 } __packed;
469
470 struct tfd_data {
471 /* Header */
472 __le32 work_area_ptr;
473 u8 station_number; /* 0 for BSS */
474 u8 reserved1;
475 __le16 reserved2;
476
477 /* Tx Parameters */
478 u8 cmd_id;
479 u8 seq_num;
480 __le16 len;
481 u8 priority;
482 u8 tx_flags;
483 u8 tx_flags_ext;
484 u8 key_index;
485 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
486 u8 rate;
487 u8 antenna;
488 __le16 next_packet_duration;
489 __le16 next_frag_len;
490 __le16 back_off_counter; //////txop;
491 u8 retrylimit;
492 __le16 cwcurrent;
493 u8 reserved3;
494
495 /* 802.11 MAC Header */
496 union {
497 struct tx_tfd_24 tfd_24;
498 struct tx_tfd_26 tfd_26;
499 struct tx_tfd_30 tfd_30;
500 struct tx_tfd_32 tfd_32;
501 } tfd;
502
503 /* Payload DMA info */
504 __le32 num_chunks;
505 __le32 chunk_ptr[NUM_TFD_CHUNKS];
506 __le16 chunk_len[NUM_TFD_CHUNKS];
507 } __packed;
508
509 struct txrx_control_flags {
510 u8 message_type;
511 u8 rx_seq_num;
512 u8 control_bits;
513 u8 reserved;
514 } __packed;
515
516 #define TFD_SIZE 128
517 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
518
519 struct tfd_frame {
520 struct txrx_control_flags control_flags;
521 union {
522 struct tfd_data data;
523 struct tfd_command cmd;
524 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
525 } u;
526 } __packed;
527
528 typedef void destructor_func(const void *);
529
530 /**
531 * Tx Queue for DMA. Queue consists of circular buffer of
532 * BD's and required locking structures.
533 */
534 struct clx2_tx_queue {
535 struct clx2_queue q;
536 struct tfd_frame *bd;
537 struct libipw_txb **txb;
538 };
539
540 /*
541 * RX related structures and functions
542 */
543 #define RX_FREE_BUFFERS 32
544 #define RX_LOW_WATERMARK 8
545
546 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
547 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
548 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
549
550 // Used for passing to driver number of successes and failures per rate
551 struct rate_histogram {
552 union {
553 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
554 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
555 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
556 } success;
557 union {
558 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
559 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
560 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
561 } failed;
562 } __packed;
563
564 /* statistics command response */
565 struct ipw_cmd_stats {
566 u8 cmd_id;
567 u8 seq_num;
568 __le16 good_sfd;
569 __le16 bad_plcp;
570 __le16 wrong_bssid;
571 __le16 valid_mpdu;
572 __le16 bad_mac_header;
573 __le16 reserved_frame_types;
574 __le16 rx_ina;
575 __le16 bad_crc32;
576 __le16 invalid_cts;
577 __le16 invalid_acks;
578 __le16 long_distance_ina_fina;
579 __le16 dsp_silence_unreachable;
580 __le16 accumulated_rssi;
581 __le16 rx_ovfl_frame_tossed;
582 __le16 rssi_silence_threshold;
583 __le16 rx_ovfl_frame_supplied;
584 __le16 last_rx_frame_signal;
585 __le16 last_rx_frame_noise;
586 __le16 rx_autodetec_no_ofdm;
587 __le16 rx_autodetec_no_barker;
588 __le16 reserved;
589 } __packed;
590
591 struct notif_channel_result {
592 u8 channel_num;
593 struct ipw_cmd_stats stats;
594 u8 uReserved;
595 } __packed;
596
597 #define SCAN_COMPLETED_STATUS_COMPLETE 1
598 #define SCAN_COMPLETED_STATUS_ABORTED 2
599
600 struct notif_scan_complete {
601 u8 scan_type;
602 u8 num_channels;
603 u8 status;
604 u8 reserved;
605 } __packed;
606
607 struct notif_frag_length {
608 __le16 frag_length;
609 __le16 reserved;
610 } __packed;
611
612 struct notif_beacon_state {
613 __le32 state;
614 __le32 number;
615 } __packed;
616
617 struct notif_tgi_tx_key {
618 u8 key_state;
619 u8 security_type;
620 u8 station_index;
621 u8 reserved;
622 } __packed;
623
624 #define SILENCE_OVER_THRESH (1)
625 #define SILENCE_UNDER_THRESH (2)
626
627 struct notif_link_deterioration {
628 struct ipw_cmd_stats stats;
629 u8 rate;
630 u8 modulation;
631 struct rate_histogram histogram;
632 u8 silence_notification_type; /* SILENCE_OVER/UNDER_THRESH */
633 __le16 silence_count;
634 } __packed;
635
636 struct notif_association {
637 u8 state;
638 } __packed;
639
640 struct notif_authenticate {
641 u8 state;
642 struct machdr24 addr;
643 __le16 status;
644 } __packed;
645
646 struct notif_calibration {
647 u8 data[104];
648 } __packed;
649
650 struct notif_noise {
651 __le32 value;
652 } __packed;
653
654 struct ipw_rx_notification {
655 u8 reserved[8];
656 u8 subtype;
657 u8 flags;
658 __le16 size;
659 union {
660 struct notif_association assoc;
661 struct notif_authenticate auth;
662 struct notif_channel_result channel_result;
663 struct notif_scan_complete scan_complete;
664 struct notif_frag_length frag_len;
665 struct notif_beacon_state beacon_state;
666 struct notif_tgi_tx_key tgi_tx_key;
667 struct notif_link_deterioration link_deterioration;
668 struct notif_calibration calibration;
669 struct notif_noise noise;
670 u8 raw[0];
671 } u;
672 } __packed;
673
674 struct ipw_rx_frame {
675 __le32 reserved1;
676 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
677 u8 received_channel; // The channel that this frame was received on.
678 // Note that for .11b this does not have to be
679 // the same as the channel that it was sent.
680 // Filled by LMAC
681 u8 frameStatus;
682 u8 rate;
683 u8 rssi;
684 u8 agc;
685 u8 rssi_dbm;
686 __le16 signal;
687 __le16 noise;
688 u8 antennaAndPhy;
689 u8 control; // control bit should be on in bg
690 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
691 // is identical)
692 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
693 __le16 length;
694 u8 data[0];
695 } __packed;
696
697 struct ipw_rx_header {
698 u8 message_type;
699 u8 rx_seq_num;
700 u8 control_bits;
701 u8 reserved;
702 } __packed;
703
704 struct ipw_rx_packet {
705 struct ipw_rx_header header;
706 union {
707 struct ipw_rx_frame frame;
708 struct ipw_rx_notification notification;
709 } u;
710 } __packed;
711
712 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
713 #define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \
714 sizeof(struct ipw_rx_frame))
715
716 struct ipw_rx_mem_buffer {
717 dma_addr_t dma_addr;
718 struct sk_buff *skb;
719 struct list_head list;
720 }; /* Not transferred over network, so not __packed */
721
722 struct ipw_rx_queue {
723 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
724 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
725 u32 processed; /* Internal index to last handled Rx packet */
726 u32 read; /* Shared index to newest available Rx buffer */
727 u32 write; /* Shared index to oldest written Rx packet */
728 u32 free_count; /* Number of pre-allocated buffers in rx_free */
729 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
730 struct list_head rx_free; /* Own an SKBs */
731 struct list_head rx_used; /* No SKB allocated */
732 spinlock_t lock;
733 }; /* Not transferred over network, so not __packed */
734
735 struct alive_command_responce {
736 u8 alive_command;
737 u8 sequence_number;
738 __le16 software_revision;
739 u8 device_identifier;
740 u8 reserved1[5];
741 __le16 reserved2;
742 __le16 reserved3;
743 __le16 clock_settle_time;
744 __le16 powerup_settle_time;
745 __le16 reserved4;
746 u8 time_stamp[5]; /* month, day, year, hours, minutes */
747 u8 ucode_valid;
748 } __packed;
749
750 #define IPW_MAX_RATES 12
751
752 struct ipw_rates {
753 u8 num_rates;
754 u8 rates[IPW_MAX_RATES];
755 } __packed;
756
757 struct command_block {
758 unsigned int control;
759 u32 source_addr;
760 u32 dest_addr;
761 unsigned int status;
762 } __packed;
763
764 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
765 struct fw_image_desc {
766 unsigned long last_cb_index;
767 unsigned long current_cb_index;
768 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
769 void *v_addr;
770 unsigned long p_addr;
771 unsigned long len;
772 };
773
774 struct ipw_sys_config {
775 u8 bt_coexistence;
776 u8 reserved1;
777 u8 answer_broadcast_ssid_probe;
778 u8 accept_all_data_frames;
779 u8 accept_non_directed_frames;
780 u8 exclude_unicast_unencrypted;
781 u8 disable_unicast_decryption;
782 u8 exclude_multicast_unencrypted;
783 u8 disable_multicast_decryption;
784 u8 antenna_diversity;
785 u8 pass_crc_to_host;
786 u8 dot11g_auto_detection;
787 u8 enable_cts_to_self;
788 u8 enable_multicast_filtering;
789 u8 bt_coexist_collision_thr;
790 u8 silence_threshold;
791 u8 accept_all_mgmt_bcpr;
792 u8 accept_all_mgmt_frames;
793 u8 pass_noise_stats_to_host;
794 u8 reserved3;
795 } __packed;
796
797 struct ipw_multicast_addr {
798 u8 num_of_multicast_addresses;
799 u8 reserved[3];
800 u8 mac1[6];
801 u8 mac2[6];
802 u8 mac3[6];
803 u8 mac4[6];
804 } __packed;
805
806 #define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
807 #define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
808
809 #define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
810 #define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
811 #define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
812
813 #define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
814 #define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
815 #define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
816 #define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
817 //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
818
819 struct ipw_wep_key {
820 u8 cmd_id;
821 u8 seq_num;
822 u8 key_index;
823 u8 key_size;
824 u8 key[16];
825 } __packed;
826
827 struct ipw_tgi_tx_key {
828 u8 key_id;
829 u8 security_type;
830 u8 station_index;
831 u8 flags;
832 u8 key[16];
833 __le32 tx_counter[2];
834 } __packed;
835
836 #define IPW_SCAN_CHANNELS 54
837
838 struct ipw_scan_request {
839 u8 scan_type;
840 __le16 dwell_time;
841 u8 channels_list[IPW_SCAN_CHANNELS];
842 u8 channels_reserved[3];
843 } __packed;
844
845 enum {
846 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
847 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
848 IPW_SCAN_ACTIVE_DIRECT_SCAN,
849 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
850 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
851 IPW_SCAN_TYPES
852 };
853
854 struct ipw_scan_request_ext {
855 __le32 full_scan_index;
856 u8 channels_list[IPW_SCAN_CHANNELS];
857 u8 scan_type[IPW_SCAN_CHANNELS / 2];
858 u8 reserved;
859 __le16 dwell_time[IPW_SCAN_TYPES];
860 } __packed;
861
862 static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
863 {
864 if (index % 2)
865 return scan->scan_type[index / 2] & 0x0F;
866 else
867 return (scan->scan_type[index / 2] & 0xF0) >> 4;
868 }
869
870 static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
871 u8 index, u8 scan_type)
872 {
873 if (index % 2)
874 scan->scan_type[index / 2] =
875 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
876 else
877 scan->scan_type[index / 2] =
878 (scan->scan_type[index / 2] & 0x0F) |
879 ((scan_type & 0x0F) << 4);
880 }
881
882 struct ipw_associate {
883 u8 channel;
884 #ifdef __LITTLE_ENDIAN_BITFIELD
885 u8 auth_type:4, auth_key:4;
886 #else
887 u8 auth_key:4, auth_type:4;
888 #endif
889 u8 assoc_type;
890 u8 reserved;
891 __le16 policy_support;
892 u8 preamble_length;
893 u8 ieee_mode;
894 u8 bssid[ETH_ALEN];
895 __le32 assoc_tsf_msw;
896 __le32 assoc_tsf_lsw;
897 __le16 capability;
898 __le16 listen_interval;
899 __le16 beacon_interval;
900 u8 dest[ETH_ALEN];
901 __le16 atim_window;
902 u8 smr;
903 u8 reserved1;
904 __le16 reserved2;
905 } __packed;
906
907 struct ipw_supported_rates {
908 u8 ieee_mode;
909 u8 num_rates;
910 u8 purpose;
911 u8 reserved;
912 u8 supported_rates[IPW_MAX_RATES];
913 } __packed;
914
915 struct ipw_rts_threshold {
916 __le16 rts_threshold;
917 __le16 reserved;
918 } __packed;
919
920 struct ipw_frag_threshold {
921 __le16 frag_threshold;
922 __le16 reserved;
923 } __packed;
924
925 struct ipw_retry_limit {
926 u8 short_retry_limit;
927 u8 long_retry_limit;
928 __le16 reserved;
929 } __packed;
930
931 struct ipw_dino_config {
932 __le32 dino_config_addr;
933 __le16 dino_config_size;
934 u8 dino_response;
935 u8 reserved;
936 } __packed;
937
938 struct ipw_aironet_info {
939 u8 id;
940 u8 length;
941 __le16 reserved;
942 } __packed;
943
944 struct ipw_rx_key {
945 u8 station_index;
946 u8 key_type;
947 u8 key_id;
948 u8 key_flag;
949 u8 key[16];
950 u8 station_address[6];
951 u8 key_index;
952 u8 reserved;
953 } __packed;
954
955 struct ipw_country_channel_info {
956 u8 first_channel;
957 u8 no_channels;
958 s8 max_tx_power;
959 } __packed;
960
961 struct ipw_country_info {
962 u8 id;
963 u8 length;
964 u8 country_str[3];
965 struct ipw_country_channel_info groups[7];
966 } __packed;
967
968 struct ipw_channel_tx_power {
969 u8 channel_number;
970 s8 tx_power;
971 } __packed;
972
973 #define SCAN_ASSOCIATED_INTERVAL (HZ)
974 #define SCAN_INTERVAL (HZ / 10)
975 #define MAX_A_CHANNELS 37
976 #define MAX_B_CHANNELS 14
977
978 struct ipw_tx_power {
979 u8 num_channels;
980 u8 ieee_mode;
981 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
982 } __packed;
983
984 struct ipw_rsn_capabilities {
985 u8 id;
986 u8 length;
987 __le16 version;
988 } __packed;
989
990 struct ipw_sensitivity_calib {
991 __le16 beacon_rssi_raw;
992 __le16 reserved;
993 } __packed;
994
995 /**
996 * Host command structure.
997 *
998 * On input, the following fields should be filled:
999 * - cmd
1000 * - len
1001 * - status_len
1002 * - param (if needed)
1003 *
1004 * On output,
1005 * - \a status contains status;
1006 * - \a param filled with status parameters.
1007 */
1008 struct ipw_cmd { /* XXX */
1009 u32 cmd; /**< Host command */
1010 u32 status;/**< Status */
1011 u32 status_len;
1012 /**< How many 32 bit parameters in the status */
1013 u32 len; /**< incoming parameters length, bytes */
1014 /**
1015 * command parameters.
1016 * There should be enough space for incoming and
1017 * outcoming parameters.
1018 * Incoming parameters listed 1-st, followed by outcoming params.
1019 * nParams=(len+3)/4+status_len
1020 */
1021 u32 param[0];
1022 } __packed;
1023
1024 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
1025
1026 #define STATUS_INT_ENABLED (1<<1)
1027 #define STATUS_RF_KILL_HW (1<<2)
1028 #define STATUS_RF_KILL_SW (1<<3)
1029 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
1030
1031 #define STATUS_INIT (1<<5)
1032 #define STATUS_AUTH (1<<6)
1033 #define STATUS_ASSOCIATED (1<<7)
1034 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
1035
1036 #define STATUS_ASSOCIATING (1<<8)
1037 #define STATUS_DISASSOCIATING (1<<9)
1038 #define STATUS_ROAMING (1<<10)
1039 #define STATUS_EXIT_PENDING (1<<11)
1040 #define STATUS_DISASSOC_PENDING (1<<12)
1041 #define STATUS_STATE_PENDING (1<<13)
1042
1043 #define STATUS_DIRECT_SCAN_PENDING (1<<19)
1044 #define STATUS_SCAN_PENDING (1<<20)
1045 #define STATUS_SCANNING (1<<21)
1046 #define STATUS_SCAN_ABORTING (1<<22)
1047 #define STATUS_SCAN_FORCED (1<<23)
1048
1049 #define STATUS_LED_LINK_ON (1<<24)
1050 #define STATUS_LED_ACT_ON (1<<25)
1051
1052 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
1053 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
1054 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
1055
1056 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
1057
1058 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
1059 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
1060 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
1061 #define CFG_CUSTOM_MAC (1<<3)
1062 #define CFG_PREAMBLE_LONG (1<<4)
1063 #define CFG_ADHOC_PERSIST (1<<5)
1064 #define CFG_ASSOCIATE (1<<6)
1065 #define CFG_FIXED_RATE (1<<7)
1066 #define CFG_ADHOC_CREATE (1<<8)
1067 #define CFG_NO_LED (1<<9)
1068 #define CFG_BACKGROUND_SCAN (1<<10)
1069 #define CFG_SPEED_SCAN (1<<11)
1070 #define CFG_NET_STATS (1<<12)
1071
1072 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
1073 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
1074
1075 #define MAX_STATIONS 32
1076 #define IPW_INVALID_STATION (0xff)
1077
1078 struct ipw_station_entry {
1079 u8 mac_addr[ETH_ALEN];
1080 u8 reserved;
1081 u8 support_mode;
1082 };
1083
1084 #define AVG_ENTRIES 8
1085 struct average {
1086 s16 entries[AVG_ENTRIES];
1087 u8 pos;
1088 u8 init;
1089 s32 sum;
1090 };
1091
1092 #define MAX_SPEED_SCAN 100
1093 #define IPW_IBSS_MAC_HASH_SIZE 31
1094
1095 struct ipw_ibss_seq {
1096 u8 mac[ETH_ALEN];
1097 u16 seq_num;
1098 u16 frag_num;
1099 unsigned long packet_time;
1100 struct list_head list;
1101 };
1102
1103 struct ipw_error_elem { /* XXX */
1104 u32 desc;
1105 u32 time;
1106 u32 blink1;
1107 u32 blink2;
1108 u32 link1;
1109 u32 link2;
1110 u32 data;
1111 };
1112
1113 struct ipw_event { /* XXX */
1114 u32 event;
1115 u32 time;
1116 u32 data;
1117 } __packed;
1118
1119 struct ipw_fw_error { /* XXX */
1120 unsigned long jiffies;
1121 u32 status;
1122 u32 config;
1123 u32 elem_len;
1124 u32 log_len;
1125 struct ipw_error_elem *elem;
1126 struct ipw_event *log;
1127 u8 payload[0];
1128 } __packed;
1129
1130 #ifdef CONFIG_IPW2200_PROMISCUOUS
1131
1132 enum ipw_prom_filter {
1133 IPW_PROM_CTL_HEADER_ONLY = (1 << 0),
1134 IPW_PROM_MGMT_HEADER_ONLY = (1 << 1),
1135 IPW_PROM_DATA_HEADER_ONLY = (1 << 2),
1136 IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */
1137 IPW_PROM_NO_TX = (1 << 4),
1138 IPW_PROM_NO_RX = (1 << 5),
1139 IPW_PROM_NO_CTL = (1 << 6),
1140 IPW_PROM_NO_MGMT = (1 << 7),
1141 IPW_PROM_NO_DATA = (1 << 8),
1142 };
1143
1144 struct ipw_priv;
1145 struct ipw_prom_priv {
1146 struct ipw_priv *priv;
1147 struct libipw_device *ieee;
1148 enum ipw_prom_filter filter;
1149 int tx_packets;
1150 int rx_packets;
1151 };
1152 #endif
1153
1154 #if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS)
1155 /* Magic struct that slots into the radiotap header -- no reason
1156 * to build this manually element by element, we can write it much
1157 * more efficiently than we can parse it. ORDER MATTERS HERE
1158 *
1159 * When sent to us via the simulated Rx interface in sysfs, the entire
1160 * structure is provided regardless of any bits unset.
1161 */
1162 struct ipw_rt_hdr {
1163 struct ieee80211_radiotap_header rt_hdr;
1164 u64 rt_tsf; /* TSF */ /* XXX */
1165 u8 rt_flags; /* radiotap packet flags */
1166 u8 rt_rate; /* rate in 500kb/s */
1167 __le16 rt_channel; /* channel in mhz */
1168 __le16 rt_chbitmask; /* channel bitfield */
1169 s8 rt_dbmsignal; /* signal in dbM, kluged to signed */
1170 s8 rt_dbmnoise;
1171 u8 rt_antenna; /* antenna number */
1172 u8 payload[0]; /* payload... */
1173 } __packed;
1174 #endif
1175
1176 struct ipw_priv {
1177 /* ieee device used by generic ieee processing code */
1178 struct libipw_device *ieee;
1179
1180 spinlock_t lock;
1181 spinlock_t irq_lock;
1182 struct mutex mutex;
1183
1184 /* basic pci-network driver stuff */
1185 struct pci_dev *pci_dev;
1186 struct net_device *net_dev;
1187
1188 #ifdef CONFIG_IPW2200_PROMISCUOUS
1189 /* Promiscuous mode */
1190 struct ipw_prom_priv *prom_priv;
1191 struct net_device *prom_net_dev;
1192 #endif
1193
1194 /* pci hardware address support */
1195 void __iomem *hw_base;
1196 unsigned long hw_len;
1197
1198 struct fw_image_desc sram_desc;
1199
1200 /* result of ucode download */
1201 struct alive_command_responce dino_alive;
1202
1203 wait_queue_head_t wait_command_queue;
1204 wait_queue_head_t wait_state;
1205
1206 /* Rx and Tx DMA processing queues */
1207 struct ipw_rx_queue *rxq;
1208 struct clx2_tx_queue txq_cmd;
1209 struct clx2_tx_queue txq[4];
1210 u32 status;
1211 u32 config;
1212 u32 capability;
1213
1214 struct average average_missed_beacons;
1215 s16 exp_avg_rssi;
1216 s16 exp_avg_noise;
1217 u32 port_type;
1218 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1219 int rx_pend_max; /**< maximum pending buffers for one IRQ */
1220 u32 hcmd_seq; /**< sequence number for hcmd */
1221 u32 disassociate_threshold;
1222 u32 roaming_threshold;
1223
1224 struct ipw_associate assoc_request;
1225 struct libipw_network *assoc_network;
1226
1227 unsigned long ts_scan_abort;
1228 struct ipw_supported_rates rates;
1229 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1230 struct ipw_rates supp; /**< software defined */
1231 struct ipw_rates extended; /**< use for corresp. IE, AP only */
1232
1233 struct notif_link_deterioration last_link_deterioration; /** for statistics */
1234 struct ipw_cmd *hcmd; /**< host command currently executed */
1235
1236 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1237 u32 tsf_bcn[2]; /**< TSF from latest beacon */
1238
1239 struct notif_calibration calib; /**< last calibration */
1240
1241 /* ordinal interface with firmware */
1242 u32 table0_addr;
1243 u32 table0_len;
1244 u32 table1_addr;
1245 u32 table1_len;
1246 u32 table2_addr;
1247 u32 table2_len;
1248
1249 /* context information */
1250 u8 essid[IW_ESSID_MAX_SIZE];
1251 u8 essid_len;
1252 u8 nick[IW_ESSID_MAX_SIZE];
1253 u16 rates_mask;
1254 u8 channel;
1255 struct ipw_sys_config sys_config;
1256 u32 power_mode;
1257 u8 bssid[ETH_ALEN];
1258 u16 rts_threshold;
1259 u8 mac_addr[ETH_ALEN];
1260 u8 num_stations;
1261 u8 stations[MAX_STATIONS][ETH_ALEN];
1262 u8 short_retry_limit;
1263 u8 long_retry_limit;
1264
1265 u32 notif_missed_beacons;
1266
1267 /* Statistics and counters normalized with each association */
1268 u32 last_missed_beacons;
1269 u32 last_tx_packets;
1270 u32 last_rx_packets;
1271 u32 last_tx_failures;
1272 u32 last_rx_err;
1273 u32 last_rate;
1274
1275 u32 missed_adhoc_beacons;
1276 u32 missed_beacons;
1277 u32 rx_packets;
1278 u32 tx_packets;
1279 u32 quality;
1280
1281 u8 speed_scan[MAX_SPEED_SCAN];
1282 u8 speed_scan_pos;
1283
1284 u16 last_seq_num;
1285 u16 last_frag_num;
1286 unsigned long last_packet_time;
1287 struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];
1288
1289 /* eeprom */
1290 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1291 u8 country[4];
1292 int eeprom_delay;
1293
1294 struct iw_statistics wstats;
1295
1296 struct iw_public_data wireless_data;
1297
1298 int user_requested_scan;
1299 u8 direct_scan_ssid[IW_ESSID_MAX_SIZE];
1300 u8 direct_scan_ssid_len;
1301
1302 struct workqueue_struct *workqueue;
1303
1304 struct delayed_work adhoc_check;
1305 struct work_struct associate;
1306 struct work_struct disassociate;
1307 struct work_struct system_config;
1308 struct work_struct rx_replenish;
1309 struct delayed_work request_scan;
1310 struct delayed_work request_direct_scan;
1311 struct delayed_work request_passive_scan;
1312 struct delayed_work scan_event;
1313 struct work_struct adapter_restart;
1314 struct delayed_work rf_kill;
1315 struct work_struct up;
1316 struct work_struct down;
1317 struct delayed_work gather_stats;
1318 struct work_struct abort_scan;
1319 struct work_struct roam;
1320 struct delayed_work scan_check;
1321 struct work_struct link_up;
1322 struct work_struct link_down;
1323
1324 struct tasklet_struct irq_tasklet;
1325
1326 /* LED related variables and work_struct */
1327 u8 nic_type;
1328 u32 led_activity_on;
1329 u32 led_activity_off;
1330 u32 led_association_on;
1331 u32 led_association_off;
1332 u32 led_ofdm_on;
1333 u32 led_ofdm_off;
1334
1335 struct delayed_work led_link_on;
1336 struct delayed_work led_link_off;
1337 struct delayed_work led_act_off;
1338 struct work_struct merge_networks;
1339
1340 struct ipw_cmd_log *cmdlog;
1341 int cmdlog_len;
1342 int cmdlog_pos;
1343
1344 #define IPW_2200BG 1
1345 #define IPW_2915ABG 2
1346 u8 adapter;
1347
1348 s8 tx_power;
1349
1350 /* Track time in suspend */
1351 unsigned long suspend_at;
1352 unsigned long suspend_time;
1353
1354 #ifdef CONFIG_PM
1355 u32 pm_state[16];
1356 #endif
1357
1358 struct ipw_fw_error *error;
1359
1360 /* network state */
1361
1362 /* Used to pass the current INTA value from ISR to Tasklet */
1363 u32 isr_inta;
1364
1365 /* QoS */
1366 struct ipw_qos_info qos_data;
1367 struct work_struct qos_activate;
1368 /*********************************/
1369
1370 /* debugging info */
1371 u32 indirect_dword;
1372 u32 direct_dword;
1373 u32 indirect_byte;
1374 }; /*ipw_priv */
1375
1376 /* debug macros */
1377
1378 /* Debug and printf string expansion helpers for printing bitfields */
1379 #define BIT_FMT8 "%c%c%c%c-%c%c%c%c"
1380 #define BIT_FMT16 BIT_FMT8 ":" BIT_FMT8
1381 #define BIT_FMT32 BIT_FMT16 " " BIT_FMT16
1382
1383 #define BITC(x,y) (((x>>y)&1)?'1':'0')
1384 #define BIT_ARG8(x) \
1385 BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\
1386 BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)
1387
1388 #define BIT_ARG16(x) \
1389 BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\
1390 BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\
1391 BIT_ARG8(x)
1392
1393 #define BIT_ARG32(x) \
1394 BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\
1395 BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\
1396 BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\
1397 BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\
1398 BIT_ARG16(x)
1399
1400
1401 #define IPW_DEBUG(level, fmt, args...) \
1402 do { if (ipw_debug_level & (level)) \
1403 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1404 in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1405
1406 #ifdef CONFIG_IPW2200_DEBUG
1407 #define IPW_LL_DEBUG(level, fmt, args...) \
1408 do { if (ipw_debug_level & (level)) \
1409 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1410 in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1411 #else
1412 #define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)
1413 #endif /* CONFIG_IPW2200_DEBUG */
1414
1415 /*
1416 * To use the debug system;
1417 *
1418 * If you are defining a new debug classification, simply add it to the #define
1419 * list here in the form of:
1420 *
1421 * #define IPW_DL_xxxx VALUE
1422 *
1423 * shifting value to the left one bit from the previous entry. xxxx should be
1424 * the name of the classification (for example, WEP)
1425 *
1426 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1427 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1428 * to send output to that classification.
1429 *
1430 * To add your debug level to the list of levels seen when you perform
1431 *
1432 * % cat /proc/net/ipw/debug_level
1433 *
1434 * you simply need to add your entry to the ipw_debug_levels array.
1435 *
1436 * If you do not see debug_level in /proc/net/ipw then you do not have
1437 * CONFIG_IPW2200_DEBUG defined in your kernel configuration
1438 *
1439 */
1440
1441 #define IPW_DL_ERROR (1<<0)
1442 #define IPW_DL_WARNING (1<<1)
1443 #define IPW_DL_INFO (1<<2)
1444 #define IPW_DL_WX (1<<3)
1445 #define IPW_DL_HOST_COMMAND (1<<5)
1446 #define IPW_DL_STATE (1<<6)
1447
1448 #define IPW_DL_NOTIF (1<<10)
1449 #define IPW_DL_SCAN (1<<11)
1450 #define IPW_DL_ASSOC (1<<12)
1451 #define IPW_DL_DROP (1<<13)
1452 #define IPW_DL_IOCTL (1<<14)
1453
1454 #define IPW_DL_MANAGE (1<<15)
1455 #define IPW_DL_FW (1<<16)
1456 #define IPW_DL_RF_KILL (1<<17)
1457 #define IPW_DL_FW_ERRORS (1<<18)
1458
1459 #define IPW_DL_LED (1<<19)
1460
1461 #define IPW_DL_ORD (1<<20)
1462
1463 #define IPW_DL_FRAG (1<<21)
1464 #define IPW_DL_WEP (1<<22)
1465 #define IPW_DL_TX (1<<23)
1466 #define IPW_DL_RX (1<<24)
1467 #define IPW_DL_ISR (1<<25)
1468 #define IPW_DL_FW_INFO (1<<26)
1469 #define IPW_DL_IO (1<<27)
1470 #define IPW_DL_TRACE (1<<28)
1471
1472 #define IPW_DL_STATS (1<<29)
1473 #define IPW_DL_MERGE (1<<30)
1474 #define IPW_DL_QOS (1<<31)
1475
1476 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1477 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1478 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1479
1480 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1481 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1482 #define IPW_DEBUG_TRACE(f, a...) IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a)
1483 #define IPW_DEBUG_RX(f, a...) IPW_LL_DEBUG(IPW_DL_RX, f, ## a)
1484 #define IPW_DEBUG_TX(f, a...) IPW_LL_DEBUG(IPW_DL_TX, f, ## a)
1485 #define IPW_DEBUG_ISR(f, a...) IPW_LL_DEBUG(IPW_DL_ISR, f, ## a)
1486 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1487 #define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a)
1488 #define IPW_DEBUG_WEP(f, a...) IPW_LL_DEBUG(IPW_DL_WEP, f, ## a)
1489 #define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1490 #define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a)
1491 #define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a)
1492 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1493 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1494 #define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a)
1495 #define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a)
1496 #define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a)
1497 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1498 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1499 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1500 #define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a)
1501 #define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a)
1502 #define IPW_DEBUG_QOS(f, a...) IPW_LL_DEBUG(IPW_DL_QOS, f, ## a)
1503
1504 #include <linux/ctype.h>
1505
1506 /*
1507 * Register bit definitions
1508 */
1509
1510 #define IPW_INTA_RW 0x00000008
1511 #define IPW_INTA_MASK_R 0x0000000C
1512 #define IPW_INDIRECT_ADDR 0x00000010
1513 #define IPW_INDIRECT_DATA 0x00000014
1514 #define IPW_AUTOINC_ADDR 0x00000018
1515 #define IPW_AUTOINC_DATA 0x0000001C
1516 #define IPW_RESET_REG 0x00000020
1517 #define IPW_GP_CNTRL_RW 0x00000024
1518
1519 #define IPW_READ_INT_REGISTER 0xFF4
1520
1521 #define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
1522
1523 #define IPW_REGISTER_DOMAIN1_END 0x00001000
1524 #define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
1525
1526 #define IPW_SHARED_LOWER_BOUND 0x00000200
1527 #define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1528
1529 #define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
1530 #define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
1531
1532 #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1533 #define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1534 #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1535
1536 /*
1537 * RESET Register Bit Indexes
1538 */
1539 #define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1540 #define IPW_START_STANDBY (1<<2)
1541 #define IPW_ACTIVITY_LED (1<<4)
1542 #define IPW_ASSOCIATED_LED (1<<5)
1543 #define IPW_OFDM_LED (1<<6)
1544 #define IPW_RESET_REG_SW_RESET (1<<7)
1545 #define IPW_RESET_REG_MASTER_DISABLED (1<<8)
1546 #define IPW_RESET_REG_STOP_MASTER (1<<9)
1547 #define IPW_GATE_ODMA (1<<25)
1548 #define IPW_GATE_IDMA (1<<26)
1549 #define IPW_ARC_KESHET_CONFIG (1<<27)
1550 #define IPW_GATE_ADMA (1<<29)
1551
1552 #define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1553 #define IPW_DOMAIN_0_END 0x1000
1554 #define CLX_MEM_BAR_SIZE 0x1000
1555
1556 /* Dino/baseband control registers bits */
1557
1558 #define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
1559 #define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
1560 #define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
1561 #define IPW_BASEBAND_CONTROL_STATUS 0X00200000
1562 #define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
1563 #define IPW_BASEBAND_RX_FIFO_READ 0X00200004
1564 #define IPW_BASEBAND_CONTROL_STORE 0X00200010
1565
1566 #define IPW_INTERNAL_CMD_EVENT 0X00300004
1567 #define IPW_BASEBAND_POWER_DOWN 0x00000001
1568
1569 #define IPW_MEM_HALT_AND_RESET 0x003000e0
1570
1571 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1572 #define IPW_BIT_HALT_RESET_ON 0x80000000
1573 #define IPW_BIT_HALT_RESET_OFF 0x00000000
1574
1575 #define CB_LAST_VALID 0x20000000
1576 #define CB_INT_ENABLED 0x40000000
1577 #define CB_VALID 0x80000000
1578 #define CB_SRC_LE 0x08000000
1579 #define CB_DEST_LE 0x04000000
1580 #define CB_SRC_AUTOINC 0x00800000
1581 #define CB_SRC_IO_GATED 0x00400000
1582 #define CB_DEST_AUTOINC 0x00080000
1583 #define CB_SRC_SIZE_LONG 0x00200000
1584 #define CB_DEST_SIZE_LONG 0x00020000
1585
1586 /* DMA DEFINES */
1587
1588 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1589 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1590 #define DMA_CB_START 0x00000100
1591
1592 #define IPW_SHARED_SRAM_SIZE 0x00030000
1593 #define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
1594 #define CB_MAX_LENGTH 0x1FFF
1595
1596 #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1597 #define IPW_EEPROM_IMAGE_SIZE 0x100
1598
1599 /* DMA defs */
1600 #define IPW_DMA_I_CURRENT_CB 0x003000D0
1601 #define IPW_DMA_O_CURRENT_CB 0x003000D4
1602 #define IPW_DMA_I_DMA_CONTROL 0x003000A4
1603 #define IPW_DMA_I_CB_BASE 0x003000A0
1604
1605 #define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
1606 #define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
1607 #define IPW_TX_QUEUE_0_BD_BASE 0x00000208
1608 #define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
1609 #define IPW_TX_QUEUE_1_BD_BASE 0x00000210
1610 #define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
1611 #define IPW_TX_QUEUE_2_BD_BASE 0x00000218
1612 #define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
1613 #define IPW_TX_QUEUE_3_BD_BASE 0x00000220
1614 #define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
1615 #define IPW_RX_BD_BASE 0x00000240
1616 #define IPW_RX_BD_SIZE 0x00000244
1617 #define IPW_RFDS_TABLE_LOWER 0x00000500
1618
1619 #define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
1620 #define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
1621 #define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
1622 #define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
1623 #define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
1624 #define IPW_RX_READ_INDEX (0x000002A0)
1625
1626 #define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1627 #define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1628 #define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1629 #define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1630 #define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1631 #define IPW_RX_WRITE_INDEX (0x00000FA0)
1632
1633 /*
1634 * EEPROM Related Definitions
1635 */
1636
1637 #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1638 #define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
1639 #define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
1640 #define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
1641 #define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
1642
1643 #define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
1644 #define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
1645 #define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
1646 #define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
1647 #define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
1648 #define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
1649
1650 #define MSB 1
1651 #define LSB 0
1652 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1653
1654 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1655 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1656
1657 /* EEPROM access by BYTE */
1658 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1659 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1660 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1661 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1662 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1663 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1664 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1665 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1666 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1667 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1668
1669 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset */
1670 #define EEPROM_NIC_TYPE_0 0
1671 #define EEPROM_NIC_TYPE_1 1
1672 #define EEPROM_NIC_TYPE_2 2
1673 #define EEPROM_NIC_TYPE_3 3
1674 #define EEPROM_NIC_TYPE_4 4
1675
1676 /* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */
1677 #define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
1678 #define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
1679 #define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
1680
1681 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1682 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1683 #define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
1684 #define EEPROM_BIT_SK (1<<0)
1685 #define EEPROM_BIT_CS (1<<1)
1686 #define EEPROM_BIT_DI (1<<2)
1687 #define EEPROM_BIT_DO (1<<4)
1688
1689 #define EEPROM_CMD_READ 0x2
1690
1691 /* Interrupts masks */
1692 #define IPW_INTA_NONE 0x00000000
1693
1694 #define IPW_INTA_BIT_RX_TRANSFER 0x00000002
1695 #define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
1696 #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1697
1698 //Inta Bits for CF
1699 #define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
1700 #define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
1701 #define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
1702 #define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
1703 #define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
1704
1705 #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1706
1707 #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1708 #define IPW_INTA_BIT_POWER_DOWN 0x00200000
1709
1710 #define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1711 #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1712 #define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
1713 #define IPW_INTA_BIT_FATAL_ERROR 0x40000000
1714 #define IPW_INTA_BIT_PARITY_ERROR 0x80000000
1715
1716 /* Interrupts enabled at init time. */
1717 #define IPW_INTA_MASK_ALL \
1718 (IPW_INTA_BIT_TX_QUEUE_1 | \
1719 IPW_INTA_BIT_TX_QUEUE_2 | \
1720 IPW_INTA_BIT_TX_QUEUE_3 | \
1721 IPW_INTA_BIT_TX_QUEUE_4 | \
1722 IPW_INTA_BIT_TX_CMD_QUEUE | \
1723 IPW_INTA_BIT_RX_TRANSFER | \
1724 IPW_INTA_BIT_FATAL_ERROR | \
1725 IPW_INTA_BIT_PARITY_ERROR | \
1726 IPW_INTA_BIT_STATUS_CHANGE | \
1727 IPW_INTA_BIT_FW_INITIALIZATION_DONE | \
1728 IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1729 IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1730 IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1731 IPW_INTA_BIT_POWER_DOWN | \
1732 IPW_INTA_BIT_RF_KILL_DONE )
1733
1734 /* FW event log definitions */
1735 #define EVENT_ELEM_SIZE (3 * sizeof(u32))
1736 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1737
1738 /* FW error log definitions */
1739 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1740 #define ERROR_START_OFFSET (1 * sizeof(u32))
1741
1742 /* TX power level (dbm) */
1743 #define IPW_TX_POWER_MIN -12
1744 #define IPW_TX_POWER_MAX 20
1745 #define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX
1746
1747 enum {
1748 IPW_FW_ERROR_OK = 0,
1749 IPW_FW_ERROR_FAIL,
1750 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1751 IPW_FW_ERROR_MEMORY_OVERFLOW,
1752 IPW_FW_ERROR_BAD_PARAM,
1753 IPW_FW_ERROR_BAD_CHECKSUM,
1754 IPW_FW_ERROR_NMI_INTERRUPT,
1755 IPW_FW_ERROR_BAD_DATABASE,
1756 IPW_FW_ERROR_ALLOC_FAIL,
1757 IPW_FW_ERROR_DMA_UNDERRUN,
1758 IPW_FW_ERROR_DMA_STATUS,
1759 IPW_FW_ERROR_DINO_ERROR,
1760 IPW_FW_ERROR_EEPROM_ERROR,
1761 IPW_FW_ERROR_SYSASSERT,
1762 IPW_FW_ERROR_FATAL_ERROR
1763 };
1764
1765 #define AUTH_OPEN 0
1766 #define AUTH_SHARED_KEY 1
1767 #define AUTH_LEAP 2
1768 #define AUTH_IGNORE 3
1769
1770 #define HC_ASSOCIATE 0
1771 #define HC_REASSOCIATE 1
1772 #define HC_DISASSOCIATE 2
1773 #define HC_IBSS_START 3
1774 #define HC_IBSS_RECONF 4
1775 #define HC_DISASSOC_QUIET 5
1776
1777 #define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01)
1778
1779 #define IPW_RATE_CAPABILITIES 1
1780 #define IPW_RATE_CONNECT 0
1781
1782 /*
1783 * Rate values and masks
1784 */
1785 #define IPW_TX_RATE_1MB 0x0A
1786 #define IPW_TX_RATE_2MB 0x14
1787 #define IPW_TX_RATE_5MB 0x37
1788 #define IPW_TX_RATE_6MB 0x0D
1789 #define IPW_TX_RATE_9MB 0x0F
1790 #define IPW_TX_RATE_11MB 0x6E
1791 #define IPW_TX_RATE_12MB 0x05
1792 #define IPW_TX_RATE_18MB 0x07
1793 #define IPW_TX_RATE_24MB 0x09
1794 #define IPW_TX_RATE_36MB 0x0B
1795 #define IPW_TX_RATE_48MB 0x01
1796 #define IPW_TX_RATE_54MB 0x03
1797
1798 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1799 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1800
1801 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1802 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1803 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1804 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1805 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1806 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1807 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1808 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1809
1810 /*
1811 * Table 0 Entries (all entries are 32 bits)
1812 */
1813 enum {
1814 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1815 IPW_ORD_STAT_FRAG_TRESHOLD,
1816 IPW_ORD_STAT_RTS_THRESHOLD,
1817 IPW_ORD_STAT_TX_HOST_REQUESTS,
1818 IPW_ORD_STAT_TX_HOST_COMPLETE,
1819 IPW_ORD_STAT_TX_DIR_DATA,
1820 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1821 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1822 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1823 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1824 /* Hole */
1825
1826 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1827 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1828 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1829 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1830 IPW_ORD_STAT_TX_DIR_DATA_G_9,
1831 IPW_ORD_STAT_TX_DIR_DATA_G_11,
1832 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1833 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1834 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1835 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1836 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1837 IPW_ORD_STAT_TX_DIR_DATA_G_54,
1838 IPW_ORD_STAT_TX_NON_DIR_DATA,
1839 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1840 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1841 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1842 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1843 /* Hole */
1844
1845 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1846 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1847 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1848 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1849 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1850 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1851 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1852 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1853 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1854 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1855 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1856 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1857 IPW_ORD_STAT_TX_RETRY,
1858 IPW_ORD_STAT_TX_FAILURE,
1859 IPW_ORD_STAT_RX_ERR_CRC,
1860 IPW_ORD_STAT_RX_ERR_ICV,
1861 IPW_ORD_STAT_RX_NO_BUFFER,
1862 IPW_ORD_STAT_FULL_SCANS,
1863 IPW_ORD_STAT_PARTIAL_SCANS,
1864 IPW_ORD_STAT_TGH_ABORTED_SCANS,
1865 IPW_ORD_STAT_TX_TOTAL_BYTES,
1866 IPW_ORD_STAT_CURR_RSSI_RAW,
1867 IPW_ORD_STAT_RX_BEACON,
1868 IPW_ORD_STAT_MISSED_BEACONS,
1869 IPW_ORD_TABLE_0_LAST
1870 };
1871
1872 #define IPW_RSSI_TO_DBM 112
1873
1874 /* Table 1 Entries
1875 */
1876 enum {
1877 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1878 };
1879
1880 /*
1881 * Table 2 Entries
1882 *
1883 * FW_VERSION: 16 byte string
1884 * FW_DATE: 16 byte string (only 14 bytes used)
1885 * UCODE_VERSION: 4 byte version code
1886 * UCODE_DATE: 5 bytes code code
1887 * ADDAPTER_MAC: 6 byte MAC address
1888 * RTC: 4 byte clock
1889 */
1890 enum {
1891 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1892 IPW_ORD_STAT_FW_DATE,
1893 IPW_ORD_STAT_UCODE_VERSION,
1894 IPW_ORD_STAT_UCODE_DATE,
1895 IPW_ORD_STAT_ADAPTER_MAC,
1896 IPW_ORD_STAT_RTC,
1897 IPW_ORD_TABLE_2_LAST
1898 };
1899
1900 /* Table 3 */
1901 enum {
1902 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1903 IPW_ORD_STAT_TX_PACKET_FAILURE,
1904 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1905 IPW_ORD_STAT_TX_PACKET_ABORTED,
1906 IPW_ORD_TABLE_3_LAST
1907 };
1908
1909 /* Table 4 */
1910 enum {
1911 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1912 };
1913
1914 /* Table 5 */
1915 enum {
1916 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1917 IPW_ORD_STAT_AP_ASSNS,
1918 IPW_ORD_STAT_ROAM,
1919 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1920 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1921 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1922 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1923 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1924 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1925 IPW_ORD_STAT_LINK_UP,
1926 IPW_ORD_STAT_LINK_DOWN,
1927 IPW_ORD_ANTENNA_DIVERSITY,
1928 IPW_ORD_CURR_FREQ,
1929 IPW_ORD_TABLE_5_LAST
1930 };
1931
1932 /* Table 6 */
1933 enum {
1934 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1935 IPW_ORD_CURR_BSSID,
1936 IPW_ORD_CURR_SSID,
1937 IPW_ORD_TABLE_6_LAST
1938 };
1939
1940 /* Table 7 */
1941 enum {
1942 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1943 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1944 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1945 IPW_ORD_STAT_CURR_RSSI_DBM,
1946 IPW_ORD_TABLE_7_LAST
1947 };
1948
1949 #define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
1950 #define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
1951 #define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
1952 #define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
1953 #define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
1954 #define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
1955 #define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
1956
1957 struct ipw_fixed_rate {
1958 __le16 tx_rates;
1959 __le16 reserved;
1960 } __packed;
1961
1962 #define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1963
1964 struct host_cmd {
1965 u8 cmd;
1966 u8 len;
1967 u16 reserved;
1968 u32 *param;
1969 } __packed; /* XXX */
1970
1971 struct cmdlog_host_cmd {
1972 u8 cmd;
1973 u8 len;
1974 __le16 reserved;
1975 char param[124];
1976 } __packed;
1977
1978 struct ipw_cmd_log {
1979 unsigned long jiffies;
1980 int retcode;
1981 struct cmdlog_host_cmd cmd;
1982 };
1983
1984 /* SysConfig command parameters ... */
1985 /* bt_coexistence param */
1986 #define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
1987 #define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
1988 #define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
1989 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
1990 #define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
1991
1992 /* clear-to-send to self param */
1993 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00
1994 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x01
1995 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1996
1997 /* Antenna diversity param (h/w can select best antenna, based on signal) */
1998 #define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
1999 #define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
2000 #define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
2001 #define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */
2002
2003 /*
2004 * The definitions below were lifted off the ipw2100 driver, which only
2005 * supports 'b' mode, so I'm sure these are not exactly correct.
2006 *
2007 * Somebody fix these!!
2008 */
2009 #define REG_MIN_CHANNEL 0
2010 #define REG_MAX_CHANNEL 14
2011
2012 #define REG_CHANNEL_MASK 0x00003FFF
2013 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
2014
2015 #define IPW_MAX_CONFIG_RETRIES 10
2016
2017 #endif /* __ipw2200_h__ */
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