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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / wireless / iwlwifi / iwl-agn-tx.c
blob24a11b8f73bc1f707de2a5b528e61d7c7b4c6b82
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-sta.h"
38 #include "iwl-io.h"
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
41 #include "iwl-agn.h"
42
43 /*
44 * mac80211 queues, ACs, hardware queues, FIFOs.
45 *
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
47 *
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
50 *
51 * VO 0
52 * VI 1
53 * BE 2
54 * BK 3
55 *
56 *
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
63 *
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
66 * mapping.
67 */
68
69 static const u8 tid_to_ac[] = {
70 IEEE80211_AC_BE,
71 IEEE80211_AC_BK,
72 IEEE80211_AC_BK,
73 IEEE80211_AC_BE,
74 IEEE80211_AC_VI,
75 IEEE80211_AC_VI,
76 IEEE80211_AC_VO,
77 IEEE80211_AC_VO
78 };
79
80 static inline int get_ac_from_tid(u16 tid)
81 {
82 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
83 return tid_to_ac[tid];
84
85 /* no support for TIDs 8-15 yet */
86 return -EINVAL;
87 }
88
89 static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
90 {
91 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
92 return ctx->ac_to_fifo[tid_to_ac[tid]];
93
94 /* no support for TIDs 8-15 yet */
95 return -EINVAL;
96 }
97
98 /**
99 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
100 */
101 void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
102 struct iwl_tx_queue *txq,
103 u16 byte_cnt)
104 {
105 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
106 int write_ptr = txq->q.write_ptr;
107 int txq_id = txq->q.id;
108 u8 sec_ctl = 0;
109 u8 sta_id = 0;
110 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
111 __le16 bc_ent;
112
113 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
114
115 if (txq_id != priv->cmd_queue) {
116 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
117 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
118
119 switch (sec_ctl & TX_CMD_SEC_MSK) {
120 case TX_CMD_SEC_CCM:
121 len += CCMP_MIC_LEN;
122 break;
123 case TX_CMD_SEC_TKIP:
124 len += TKIP_ICV_LEN;
125 break;
126 case TX_CMD_SEC_WEP:
127 len += WEP_IV_LEN + WEP_ICV_LEN;
128 break;
129 }
130 }
131
132 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
133
134 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
135
136 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
137 scd_bc_tbl[txq_id].
138 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
139 }
140
141 void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
142 struct iwl_tx_queue *txq)
143 {
144 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
145 int txq_id = txq->q.id;
146 int read_ptr = txq->q.read_ptr;
147 u8 sta_id = 0;
148 __le16 bc_ent;
149
150 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
151
152 if (txq_id != priv->cmd_queue)
153 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
154
155 bc_ent = cpu_to_le16(1 | (sta_id << 12));
156 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
157
158 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
159 scd_bc_tbl[txq_id].
160 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
161 }
162
163 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
164 u16 txq_id)
165 {
166 u32 tbl_dw_addr;
167 u32 tbl_dw;
168 u16 scd_q2ratid;
169
170 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
171
172 tbl_dw_addr = priv->scd_base_addr +
173 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
174
175 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
176
177 if (txq_id & 0x1)
178 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
179 else
180 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
181
182 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
183
184 return 0;
185 }
186
187 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
188 {
189 /* Simply stop the queue, but don't change any configuration;
190 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
191 iwl_write_prph(priv,
192 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
193 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
194 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
195 }
196
197 void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
198 int txq_id, u32 index)
199 {
200 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
201 (index & 0xff) | (txq_id << 8));
202 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
203 }
204
205 void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
206 struct iwl_tx_queue *txq,
207 int tx_fifo_id, int scd_retry)
208 {
209 int txq_id = txq->q.id;
210 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
211
212 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
213 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
214 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
215 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
216 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
217
218 txq->sched_retry = scd_retry;
219
220 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
221 active ? "Activate" : "Deactivate",
222 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
223 }
224
225 int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
226 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
227 {
228 unsigned long flags;
229 u16 ra_tid;
230 int ret;
231
232 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
233 (IWLAGN_FIRST_AMPDU_QUEUE +
234 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
235 IWL_WARN(priv,
236 "queue number out of range: %d, must be %d to %d\n",
237 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
238 IWLAGN_FIRST_AMPDU_QUEUE +
239 priv->cfg->base_params->num_of_ampdu_queues - 1);
240 return -EINVAL;
241 }
242
243 ra_tid = BUILD_RAxTID(sta_id, tid);
244
245 /* Modify device's station table to Tx this TID */
246 ret = iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
247 if (ret)
248 return ret;
249
250 spin_lock_irqsave(&priv->lock, flags);
251
252 /* Stop this Tx queue before configuring it */
253 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
254
255 /* Map receiver-address / traffic-ID to this queue */
256 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
257
258 /* Set this queue as a chain-building queue */
259 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
260
261 /* enable aggregations for the queue */
262 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
263
264 /* Place first TFD at index corresponding to start sequence number.
265 * Assumes that ssn_idx is valid (!= 0xFFF) */
266 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
267 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
268 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
269
270 /* Set up Tx window size and frame limit for this queue */
271 iwl_write_targ_mem(priv, priv->scd_base_addr +
272 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
273 sizeof(u32),
274 ((SCD_WIN_SIZE <<
275 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
276 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
277 ((SCD_FRAME_LIMIT <<
278 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
279 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
280
281 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
282
283 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
284 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
285
286 spin_unlock_irqrestore(&priv->lock, flags);
287
288 return 0;
289 }
290
291 int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
292 u16 ssn_idx, u8 tx_fifo)
293 {
294 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
295 (IWLAGN_FIRST_AMPDU_QUEUE +
296 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
297 IWL_ERR(priv,
298 "queue number out of range: %d, must be %d to %d\n",
299 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
300 IWLAGN_FIRST_AMPDU_QUEUE +
301 priv->cfg->base_params->num_of_ampdu_queues - 1);
302 return -EINVAL;
303 }
304
305 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
306
307 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
308
309 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
310 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
311 /* supposes that ssn_idx is valid (!= 0xFFF) */
312 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
313
314 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
315 iwl_txq_ctx_deactivate(priv, txq_id);
316 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
317
318 return 0;
319 }
320
321 /*
322 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
323 * must be called under priv->lock and mac access
324 */
325 void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
326 {
327 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
328 }
329
330 /*
331 * handle build REPLY_TX command notification.
332 */
333 static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
334 struct sk_buff *skb,
335 struct iwl_tx_cmd *tx_cmd,
336 struct ieee80211_tx_info *info,
337 struct ieee80211_hdr *hdr,
338 u8 std_id)
339 {
340 __le16 fc = hdr->frame_control;
341 __le32 tx_flags = tx_cmd->tx_flags;
342
343 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
344 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
345 tx_flags |= TX_CMD_FLG_ACK_MSK;
346 if (ieee80211_is_mgmt(fc))
347 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
348 if (ieee80211_is_probe_resp(fc) &&
349 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
350 tx_flags |= TX_CMD_FLG_TSF_MSK;
351 } else {
352 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
353 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
354 }
355
356 if (ieee80211_is_back_req(fc))
357 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
358 else if (info->band == IEEE80211_BAND_2GHZ &&
359 priv->cfg->bt_params &&
360 priv->cfg->bt_params->advanced_bt_coexist &&
361 (ieee80211_is_auth(fc) || ieee80211_is_assoc_req(fc) ||
362 ieee80211_is_reassoc_req(fc) ||
363 skb->protocol == cpu_to_be16(ETH_P_PAE)))
364 tx_flags |= TX_CMD_FLG_IGNORE_BT;
365
366
367 tx_cmd->sta_id = std_id;
368 if (ieee80211_has_morefrags(fc))
369 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
370
371 if (ieee80211_is_data_qos(fc)) {
372 u8 *qc = ieee80211_get_qos_ctl(hdr);
373 tx_cmd->tid_tspec = qc[0] & 0xf;
374 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
375 } else {
376 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
377 }
378
379 priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
380
381 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
382 if (ieee80211_is_mgmt(fc)) {
383 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
384 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
385 else
386 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
387 } else {
388 tx_cmd->timeout.pm_frame_timeout = 0;
389 }
390
391 tx_cmd->driver_txop = 0;
392 tx_cmd->tx_flags = tx_flags;
393 tx_cmd->next_frame_len = 0;
394 }
395
396 #define RTS_DFAULT_RETRY_LIMIT 60
397
398 static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
399 struct iwl_tx_cmd *tx_cmd,
400 struct ieee80211_tx_info *info,
401 __le16 fc)
402 {
403 u32 rate_flags;
404 int rate_idx;
405 u8 rts_retry_limit;
406 u8 data_retry_limit;
407 u8 rate_plcp;
408
409 /* Set retry limit on DATA packets and Probe Responses*/
410 if (ieee80211_is_probe_resp(fc))
411 data_retry_limit = 3;
412 else
413 data_retry_limit = IWLAGN_DEFAULT_TX_RETRY;
414 tx_cmd->data_retry_limit = data_retry_limit;
415
416 /* Set retry limit on RTS packets */
417 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
418 if (data_retry_limit < rts_retry_limit)
419 rts_retry_limit = data_retry_limit;
420 tx_cmd->rts_retry_limit = rts_retry_limit;
421
422 /* DATA packets will use the uCode station table for rate/antenna
423 * selection */
424 if (ieee80211_is_data(fc)) {
425 tx_cmd->initial_rate_index = 0;
426 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
427 return;
428 }
429
430 /**
431 * If the current TX rate stored in mac80211 has the MCS bit set, it's
432 * not really a TX rate. Thus, we use the lowest supported rate for
433 * this band. Also use the lowest supported rate if the stored rate
434 * index is invalid.
435 */
436 rate_idx = info->control.rates[0].idx;
437 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
438 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
439 rate_idx = rate_lowest_index(&priv->bands[info->band],
440 info->control.sta);
441 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
442 if (info->band == IEEE80211_BAND_5GHZ)
443 rate_idx += IWL_FIRST_OFDM_RATE;
444 /* Get PLCP rate for tx_cmd->rate_n_flags */
445 rate_plcp = iwl_rates[rate_idx].plcp;
446 /* Zero out flags for this packet */
447 rate_flags = 0;
448
449 /* Set CCK flag as needed */
450 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
451 rate_flags |= RATE_MCS_CCK_MSK;
452
453 /* Set up antennas */
454 if (priv->cfg->bt_params &&
455 priv->cfg->bt_params->advanced_bt_coexist &&
456 priv->bt_full_concurrent) {
457 /* operated as 1x1 in full concurrency mode */
458 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
459 first_antenna(priv->hw_params.valid_tx_ant));
460 } else
461 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
462 priv->hw_params.valid_tx_ant);
463 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
464
465 /* Set the rate in the TX cmd */
466 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
467 }
468
469 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
470 struct ieee80211_tx_info *info,
471 struct iwl_tx_cmd *tx_cmd,
472 struct sk_buff *skb_frag,
473 int sta_id)
474 {
475 struct ieee80211_key_conf *keyconf = info->control.hw_key;
476
477 switch (keyconf->cipher) {
478 case WLAN_CIPHER_SUITE_CCMP:
479 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
480 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
481 if (info->flags & IEEE80211_TX_CTL_AMPDU)
482 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
483 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
484 break;
485
486 case WLAN_CIPHER_SUITE_TKIP:
487 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
488 ieee80211_get_tkip_key(keyconf, skb_frag,
489 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
490 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
491 break;
492
493 case WLAN_CIPHER_SUITE_WEP104:
494 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
495 /* fall through */
496 case WLAN_CIPHER_SUITE_WEP40:
497 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
498 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
499
500 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
501
502 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
503 "with key %d\n", keyconf->keyidx);
504 break;
505
506 default:
507 IWL_ERR(priv, "Unknown encode cipher %x\n", keyconf->cipher);
508 break;
509 }
510 }
511
512 /*
513 * start REPLY_TX command process
514 */
515 int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
516 {
517 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
518 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
519 struct ieee80211_sta *sta = info->control.sta;
520 struct iwl_station_priv *sta_priv = NULL;
521 struct iwl_tx_queue *txq;
522 struct iwl_queue *q;
523 struct iwl_device_cmd *out_cmd;
524 struct iwl_cmd_meta *out_meta;
525 struct iwl_tx_cmd *tx_cmd;
526 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
527 int txq_id;
528 dma_addr_t phys_addr;
529 dma_addr_t txcmd_phys;
530 dma_addr_t scratch_phys;
531 u16 len, firstlen, secondlen;
532 u16 seq_number = 0;
533 __le16 fc;
534 u8 hdr_len;
535 u8 sta_id;
536 u8 wait_write_ptr = 0;
537 u8 tid = 0;
538 u8 *qc = NULL;
539 unsigned long flags;
540 bool is_agg = false;
541
542 if (info->control.vif)
543 ctx = iwl_rxon_ctx_from_vif(info->control.vif);
544
545 spin_lock_irqsave(&priv->lock, flags);
546 if (iwl_is_rfkill(priv)) {
547 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
548 goto drop_unlock;
549 }
550
551 fc = hdr->frame_control;
552
553 #ifdef CONFIG_IWLWIFI_DEBUG
554 if (ieee80211_is_auth(fc))
555 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
556 else if (ieee80211_is_assoc_req(fc))
557 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
558 else if (ieee80211_is_reassoc_req(fc))
559 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
560 #endif
561
562 hdr_len = ieee80211_hdrlen(fc);
563
564 /* Find index into station table for destination station */
565 sta_id = iwl_sta_id_or_broadcast(priv, ctx, info->control.sta);
566 if (sta_id == IWL_INVALID_STATION) {
567 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
568 hdr->addr1);
569 goto drop_unlock;
570 }
571
572 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
573
574 if (sta)
575 sta_priv = (void *)sta->drv_priv;
576
577 if (sta_priv && sta_priv->asleep &&
578 (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) {
579 /*
580 * This sends an asynchronous command to the device,
581 * but we can rely on it being processed before the
582 * next frame is processed -- and the next frame to
583 * this station is the one that will consume this
584 * counter.
585 * For now set the counter to just 1 since we do not
586 * support uAPSD yet.
587 */
588 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
589 }
590
591 /*
592 * Send this frame after DTIM -- there's a special queue
593 * reserved for this for contexts that support AP mode.
594 */
595 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
596 txq_id = ctx->mcast_queue;
597 /*
598 * The microcode will clear the more data
599 * bit in the last frame it transmits.
600 */
601 hdr->frame_control |=
602 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
603 } else
604 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
605
606 /* irqs already disabled/saved above when locking priv->lock */
607 spin_lock(&priv->sta_lock);
608
609 if (ieee80211_is_data_qos(fc)) {
610 qc = ieee80211_get_qos_ctl(hdr);
611 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
612 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
613 spin_unlock(&priv->sta_lock);
614 goto drop_unlock;
615 }
616 seq_number = priv->stations[sta_id].tid[tid].seq_number;
617 seq_number &= IEEE80211_SCTL_SEQ;
618 hdr->seq_ctrl = hdr->seq_ctrl &
619 cpu_to_le16(IEEE80211_SCTL_FRAG);
620 hdr->seq_ctrl |= cpu_to_le16(seq_number);
621 seq_number += 0x10;
622 /* aggregation is on for this <sta,tid> */
623 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
624 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
625 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
626 is_agg = true;
627 }
628 }
629
630 txq = &priv->txq[txq_id];
631 q = &txq->q;
632
633 if (unlikely(iwl_queue_space(q) < q->high_mark)) {
634 spin_unlock(&priv->sta_lock);
635 goto drop_unlock;
636 }
637
638 if (ieee80211_is_data_qos(fc)) {
639 priv->stations[sta_id].tid[tid].tfds_in_queue++;
640 if (!ieee80211_has_morefrags(fc))
641 priv->stations[sta_id].tid[tid].seq_number = seq_number;
642 }
643
644 spin_unlock(&priv->sta_lock);
645
646 /* Set up driver data for this TFD */
647 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
648 txq->txb[q->write_ptr].skb = skb;
649 txq->txb[q->write_ptr].ctx = ctx;
650
651 /* Set up first empty entry in queue's array of Tx/cmd buffers */
652 out_cmd = txq->cmd[q->write_ptr];
653 out_meta = &txq->meta[q->write_ptr];
654 tx_cmd = &out_cmd->cmd.tx;
655 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
656 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
657
658 /*
659 * Set up the Tx-command (not MAC!) header.
660 * Store the chosen Tx queue and TFD index within the sequence field;
661 * after Tx, uCode's Tx response will return this value so driver can
662 * locate the frame within the tx queue and do post-tx processing.
663 */
664 out_cmd->hdr.cmd = REPLY_TX;
665 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
666 INDEX_TO_SEQ(q->write_ptr)));
667
668 /* Copy MAC header from skb into command buffer */
669 memcpy(tx_cmd->hdr, hdr, hdr_len);
670
671
672 /* Total # bytes to be transmitted */
673 len = (u16)skb->len;
674 tx_cmd->len = cpu_to_le16(len);
675
676 if (info->control.hw_key)
677 iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
678
679 /* TODO need this for burst mode later on */
680 iwlagn_tx_cmd_build_basic(priv, skb, tx_cmd, info, hdr, sta_id);
681 iwl_dbg_log_tx_data_frame(priv, len, hdr);
682
683 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
684
685 iwl_update_stats(priv, true, fc, len);
686 /*
687 * Use the first empty entry in this queue's command buffer array
688 * to contain the Tx command and MAC header concatenated together
689 * (payload data will be in another buffer).
690 * Size of this varies, due to varying MAC header length.
691 * If end is not dword aligned, we'll have 2 extra bytes at the end
692 * of the MAC header (device reads on dword boundaries).
693 * We'll tell device about this padding later.
694 */
695 len = sizeof(struct iwl_tx_cmd) +
696 sizeof(struct iwl_cmd_header) + hdr_len;
697 firstlen = (len + 3) & ~3;
698
699 /* Tell NIC about any 2-byte padding after MAC header */
700 if (firstlen != len)
701 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
702
703 /* Physical address of this Tx command's header (not MAC header!),
704 * within command buffer array. */
705 txcmd_phys = pci_map_single(priv->pci_dev,
706 &out_cmd->hdr, firstlen,
707 PCI_DMA_BIDIRECTIONAL);
708 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
709 dma_unmap_len_set(out_meta, len, firstlen);
710 /* Add buffer containing Tx command and MAC(!) header to TFD's
711 * first entry */
712 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
713 txcmd_phys, firstlen, 1, 0);
714
715 if (!ieee80211_has_morefrags(hdr->frame_control)) {
716 txq->need_update = 1;
717 } else {
718 wait_write_ptr = 1;
719 txq->need_update = 0;
720 }
721
722 /* Set up TFD's 2nd entry to point directly to remainder of skb,
723 * if any (802.11 null frames have no payload). */
724 secondlen = skb->len - hdr_len;
725 if (secondlen > 0) {
726 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
727 secondlen, PCI_DMA_TODEVICE);
728 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
729 phys_addr, secondlen,
730 0, 0);
731 }
732
733 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
734 offsetof(struct iwl_tx_cmd, scratch);
735
736 /* take back ownership of DMA buffer to enable update */
737 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
738 firstlen, PCI_DMA_BIDIRECTIONAL);
739 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
740 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
741
742 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
743 le16_to_cpu(out_cmd->hdr.sequence));
744 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
745 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
746 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
747
748 /* Set up entry for this TFD in Tx byte-count array */
749 if (info->flags & IEEE80211_TX_CTL_AMPDU)
750 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
751 le16_to_cpu(tx_cmd->len));
752
753 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
754 firstlen, PCI_DMA_BIDIRECTIONAL);
755
756 trace_iwlwifi_dev_tx(priv,
757 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
758 sizeof(struct iwl_tfd),
759 &out_cmd->hdr, firstlen,
760 skb->data + hdr_len, secondlen);
761
762 /* Tell device the write index *just past* this latest filled TFD */
763 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
764 iwl_txq_update_write_ptr(priv, txq);
765 spin_unlock_irqrestore(&priv->lock, flags);
766
767 /*
768 * At this point the frame is "transmitted" successfully
769 * and we will get a TX status notification eventually,
770 * regardless of the value of ret. "ret" only indicates
771 * whether or not we should update the write pointer.
772 */
773
774 /*
775 * Avoid atomic ops if it isn't an associated client.
776 * Also, if this is a packet for aggregation, don't
777 * increase the counter because the ucode will stop
778 * aggregation queues when their respective station
779 * goes to sleep.
780 */
781 if (sta_priv && sta_priv->client && !is_agg)
782 atomic_inc(&sta_priv->pending_frames);
783
784 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
785 if (wait_write_ptr) {
786 spin_lock_irqsave(&priv->lock, flags);
787 txq->need_update = 1;
788 iwl_txq_update_write_ptr(priv, txq);
789 spin_unlock_irqrestore(&priv->lock, flags);
790 } else {
791 iwl_stop_queue(priv, txq);
792 }
793 }
794
795 return 0;
796
797 drop_unlock:
798 spin_unlock_irqrestore(&priv->lock, flags);
799 return -1;
800 }
801
802 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
803 struct iwl_dma_ptr *ptr, size_t size)
804 {
805 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
806 GFP_KERNEL);
807 if (!ptr->addr)
808 return -ENOMEM;
809 ptr->size = size;
810 return 0;
811 }
812
813 static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
814 struct iwl_dma_ptr *ptr)
815 {
816 if (unlikely(!ptr->addr))
817 return;
818
819 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
820 memset(ptr, 0, sizeof(*ptr));
821 }
822
823 /**
824 * iwlagn_hw_txq_ctx_free - Free TXQ Context
825 *
826 * Destroy all TX DMA queues and structures
827 */
828 void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
829 {
830 int txq_id;
831
832 /* Tx queues */
833 if (priv->txq) {
834 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
835 if (txq_id == priv->cmd_queue)
836 iwl_cmd_queue_free(priv);
837 else
838 iwl_tx_queue_free(priv, txq_id);
839 }
840 iwlagn_free_dma_ptr(priv, &priv->kw);
841
842 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
843
844 /* free tx queue structure */
845 iwl_free_txq_mem(priv);
846 }
847
848 /**
849 * iwlagn_txq_ctx_alloc - allocate TX queue context
850 * Allocate all Tx DMA structures and initialize them
851 *
852 * @param priv
853 * @return error code
854 */
855 int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
856 {
857 int ret;
858 int txq_id, slots_num;
859 unsigned long flags;
860
861 /* Free all tx/cmd queues and keep-warm buffer */
862 iwlagn_hw_txq_ctx_free(priv);
863
864 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
865 priv->hw_params.scd_bc_tbls_size);
866 if (ret) {
867 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
868 goto error_bc_tbls;
869 }
870 /* Alloc keep-warm buffer */
871 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
872 if (ret) {
873 IWL_ERR(priv, "Keep Warm allocation failed\n");
874 goto error_kw;
875 }
876
877 /* allocate tx queue structure */
878 ret = iwl_alloc_txq_mem(priv);
879 if (ret)
880 goto error;
881
882 spin_lock_irqsave(&priv->lock, flags);
883
884 /* Turn off all Tx DMA fifos */
885 priv->cfg->ops->lib->txq_set_sched(priv, 0);
886
887 /* Tell NIC where to find the "keep warm" buffer */
888 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
889
890 spin_unlock_irqrestore(&priv->lock, flags);
891
892 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
893 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
894 slots_num = (txq_id == priv->cmd_queue) ?
895 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
896 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
897 txq_id);
898 if (ret) {
899 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
900 goto error;
901 }
902 }
903
904 return ret;
905
906 error:
907 iwlagn_hw_txq_ctx_free(priv);
908 iwlagn_free_dma_ptr(priv, &priv->kw);
909 error_kw:
910 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
911 error_bc_tbls:
912 return ret;
913 }
914
915 void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
916 {
917 int txq_id, slots_num;
918 unsigned long flags;
919
920 spin_lock_irqsave(&priv->lock, flags);
921
922 /* Turn off all Tx DMA fifos */
923 priv->cfg->ops->lib->txq_set_sched(priv, 0);
924
925 /* Tell NIC where to find the "keep warm" buffer */
926 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
927
928 spin_unlock_irqrestore(&priv->lock, flags);
929
930 /* Alloc and init all Tx queues, including the command queue (#4) */
931 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
932 slots_num = txq_id == priv->cmd_queue ?
933 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
934 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
935 }
936 }
937
938 /**
939 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
940 */
941 void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
942 {
943 int ch;
944 unsigned long flags;
945
946 /* Turn off all Tx DMA fifos */
947 spin_lock_irqsave(&priv->lock, flags);
948
949 priv->cfg->ops->lib->txq_set_sched(priv, 0);
950
951 /* Stop each Tx DMA channel, and wait for it to be idle */
952 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
953 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
954 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
955 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
956 1000))
957 IWL_ERR(priv, "Failing on timeout while stopping"
958 " DMA channel %d [0x%08x]", ch,
959 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
960 }
961 spin_unlock_irqrestore(&priv->lock, flags);
962 }
963
964 /*
965 * Find first available (lowest unused) Tx Queue, mark it "active".
966 * Called only when finding queue for aggregation.
967 * Should never return anything < 7, because they should already
968 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
969 */
970 static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv)
971 {
972 int txq_id;
973
974 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
975 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
976 return txq_id;
977 return -1;
978 }
979
980 int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
981 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
982 {
983 int sta_id;
984 int tx_fifo;
985 int txq_id;
986 int ret;
987 unsigned long flags;
988 struct iwl_tid_data *tid_data;
989
990 tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
991 if (unlikely(tx_fifo < 0))
992 return tx_fifo;
993
994 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
995 __func__, sta->addr, tid);
996
997 sta_id = iwl_sta_id(sta);
998 if (sta_id == IWL_INVALID_STATION) {
999 IWL_ERR(priv, "Start AGG on invalid station\n");
1000 return -ENXIO;
1001 }
1002 if (unlikely(tid >= MAX_TID_COUNT))
1003 return -EINVAL;
1004
1005 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1006 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1007 return -ENXIO;
1008 }
1009
1010 txq_id = iwlagn_txq_ctx_activate_free(priv);
1011 if (txq_id == -1) {
1012 IWL_ERR(priv, "No free aggregation queue available\n");
1013 return -ENXIO;
1014 }
1015
1016 spin_lock_irqsave(&priv->sta_lock, flags);
1017 tid_data = &priv->stations[sta_id].tid[tid];
1018 *ssn = SEQ_TO_SN(tid_data->seq_number);
1019 tid_data->agg.txq_id = txq_id;
1020 iwl_set_swq_id(&priv->txq[txq_id], get_ac_from_tid(tid), txq_id);
1021 spin_unlock_irqrestore(&priv->sta_lock, flags);
1022
1023 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1024 sta_id, tid, *ssn);
1025 if (ret)
1026 return ret;
1027
1028 spin_lock_irqsave(&priv->sta_lock, flags);
1029 tid_data = &priv->stations[sta_id].tid[tid];
1030 if (tid_data->tfds_in_queue == 0) {
1031 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1032 tid_data->agg.state = IWL_AGG_ON;
1033 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1034 } else {
1035 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1036 tid_data->tfds_in_queue);
1037 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1038 }
1039 spin_unlock_irqrestore(&priv->sta_lock, flags);
1040 return ret;
1041 }
1042
1043 int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
1044 struct ieee80211_sta *sta, u16 tid)
1045 {
1046 int tx_fifo_id, txq_id, sta_id, ssn;
1047 struct iwl_tid_data *tid_data;
1048 int write_ptr, read_ptr;
1049 unsigned long flags;
1050
1051 tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1052 if (unlikely(tx_fifo_id < 0))
1053 return tx_fifo_id;
1054
1055 sta_id = iwl_sta_id(sta);
1056
1057 if (sta_id == IWL_INVALID_STATION) {
1058 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1059 return -ENXIO;
1060 }
1061
1062 spin_lock_irqsave(&priv->sta_lock, flags);
1063
1064 tid_data = &priv->stations[sta_id].tid[tid];
1065 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1066 txq_id = tid_data->agg.txq_id;
1067
1068 switch (priv->stations[sta_id].tid[tid].agg.state) {
1069 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1070 /*
1071 * This can happen if the peer stops aggregation
1072 * again before we've had a chance to drain the
1073 * queue we selected previously, i.e. before the
1074 * session was really started completely.
1075 */
1076 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1077 goto turn_off;
1078 case IWL_AGG_ON:
1079 break;
1080 default:
1081 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1082 }
1083
1084 write_ptr = priv->txq[txq_id].q.write_ptr;
1085 read_ptr = priv->txq[txq_id].q.read_ptr;
1086
1087 /* The queue is not empty */
1088 if (write_ptr != read_ptr) {
1089 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1090 priv->stations[sta_id].tid[tid].agg.state =
1091 IWL_EMPTYING_HW_QUEUE_DELBA;
1092 spin_unlock_irqrestore(&priv->sta_lock, flags);
1093 return 0;
1094 }
1095
1096 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1097 turn_off:
1098 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1099
1100 /* do not restore/save irqs */
1101 spin_unlock(&priv->sta_lock);
1102 spin_lock(&priv->lock);
1103
1104 /*
1105 * the only reason this call can fail is queue number out of range,
1106 * which can happen if uCode is reloaded and all the station
1107 * information are lost. if it is outside the range, there is no need
1108 * to deactivate the uCode queue, just return "success" to allow
1109 * mac80211 to clean up it own data.
1110 */
1111 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1112 tx_fifo_id);
1113 spin_unlock_irqrestore(&priv->lock, flags);
1114
1115 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1116
1117 return 0;
1118 }
1119
1120 int iwlagn_txq_check_empty(struct iwl_priv *priv,
1121 int sta_id, u8 tid, int txq_id)
1122 {
1123 struct iwl_queue *q = &priv->txq[txq_id].q;
1124 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1125 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1126 struct iwl_rxon_context *ctx;
1127
1128 ctx = &priv->contexts[priv->stations[sta_id].ctxid];
1129
1130 lockdep_assert_held(&priv->sta_lock);
1131
1132 switch (priv->stations[sta_id].tid[tid].agg.state) {
1133 case IWL_EMPTYING_HW_QUEUE_DELBA:
1134 /* We are reclaiming the last packet of the */
1135 /* aggregated HW queue */
1136 if ((txq_id == tid_data->agg.txq_id) &&
1137 (q->read_ptr == q->write_ptr)) {
1138 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1139 int tx_fifo = get_fifo_from_tid(ctx, tid);
1140 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1141 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1142 ssn, tx_fifo);
1143 tid_data->agg.state = IWL_AGG_OFF;
1144 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1145 }
1146 break;
1147 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1148 /* We are reclaiming the last packet of the queue */
1149 if (tid_data->tfds_in_queue == 0) {
1150 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1151 tid_data->agg.state = IWL_AGG_ON;
1152 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1153 }
1154 break;
1155 }
1156
1157 return 0;
1158 }
1159
1160 static void iwlagn_non_agg_tx_status(struct iwl_priv *priv,
1161 struct iwl_rxon_context *ctx,
1162 const u8 *addr1)
1163 {
1164 struct ieee80211_sta *sta;
1165 struct iwl_station_priv *sta_priv;
1166
1167 rcu_read_lock();
1168 sta = ieee80211_find_sta(ctx->vif, addr1);
1169 if (sta) {
1170 sta_priv = (void *)sta->drv_priv;
1171 /* avoid atomic ops if this isn't a client */
1172 if (sta_priv->client &&
1173 atomic_dec_return(&sta_priv->pending_frames) == 0)
1174 ieee80211_sta_block_awake(priv->hw, sta, false);
1175 }
1176 rcu_read_unlock();
1177 }
1178
1179 static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info,
1180 bool is_agg)
1181 {
1182 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
1183
1184 if (!is_agg)
1185 iwlagn_non_agg_tx_status(priv, tx_info->ctx, hdr->addr1);
1186
1187 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
1188 }
1189
1190 int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1191 {
1192 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1193 struct iwl_queue *q = &txq->q;
1194 struct iwl_tx_info *tx_info;
1195 int nfreed = 0;
1196 struct ieee80211_hdr *hdr;
1197
1198 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1199 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1200 "is out of range [0-%d] %d %d.\n", txq_id,
1201 index, q->n_bd, q->write_ptr, q->read_ptr);
1202 return 0;
1203 }
1204
1205 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1206 q->read_ptr != index;
1207 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1208
1209 tx_info = &txq->txb[txq->q.read_ptr];
1210 iwlagn_tx_status(priv, tx_info,
1211 txq_id >= IWLAGN_FIRST_AMPDU_QUEUE);
1212
1213 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1214 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1215 nfreed++;
1216 tx_info->skb = NULL;
1217
1218 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1219 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1220
1221 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1222 }
1223 return nfreed;
1224 }
1225
1226 /**
1227 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1228 *
1229 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1230 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1231 */
1232 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1233 struct iwl_ht_agg *agg,
1234 struct iwl_compressed_ba_resp *ba_resp)
1235
1236 {
1237 int i, sh, ack;
1238 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1239 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1240 int successes = 0;
1241 struct ieee80211_tx_info *info;
1242
1243 if (unlikely(!agg->wait_for_ba)) {
1244 if (unlikely(ba_resp->bitmap))
1245 IWL_ERR(priv, "Received BA when not expected\n");
1246 return -EINVAL;
1247 }
1248
1249 /* Mark that the expected block-ack response arrived */
1250 agg->wait_for_ba = 0;
1251 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1252
1253 /* Calculate shift to align block-ack bits with our Tx window bits */
1254 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1255 if (sh < 0) /* tbw something is wrong with indices */
1256 sh += 0x100;
1257
1258 if (agg->frame_count > (64 - sh)) {
1259 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1260 return -1;
1261 }
1262 if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
1263 /*
1264 * sent and ack information provided by uCode
1265 * use it instead of figure out ourself
1266 */
1267 if (ba_resp->txed_2_done > ba_resp->txed) {
1268 IWL_DEBUG_TX_REPLY(priv,
1269 "bogus sent(%d) and ack(%d) count\n",
1270 ba_resp->txed, ba_resp->txed_2_done);
1271 /*
1272 * set txed_2_done = txed,
1273 * so it won't impact rate scale
1274 */
1275 ba_resp->txed = ba_resp->txed_2_done;
1276 }
1277 IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n",
1278 ba_resp->txed, ba_resp->txed_2_done);
1279 } else {
1280 u64 bitmap, sent_bitmap;
1281
1282 /* don't use 64-bit values for now */
1283 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1284
1285 /* check for success or failure according to the
1286 * transmitted bitmap and block-ack bitmap */
1287 sent_bitmap = bitmap & agg->bitmap;
1288
1289 /* For each frame attempted in aggregation,
1290 * update driver's record of tx frame's status. */
1291 i = 0;
1292 while (sent_bitmap) {
1293 ack = sent_bitmap & 1ULL;
1294 successes += ack;
1295 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1296 ack ? "ACK" : "NACK", i,
1297 (agg->start_idx + i) & 0xff,
1298 agg->start_idx + i);
1299 sent_bitmap >>= 1;
1300 ++i;
1301 }
1302
1303 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n",
1304 (unsigned long long)bitmap);
1305 }
1306
1307 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
1308 memset(&info->status, 0, sizeof(info->status));
1309 info->flags |= IEEE80211_TX_STAT_ACK;
1310 info->flags |= IEEE80211_TX_STAT_AMPDU;
1311 if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
1312 info->status.ampdu_ack_len = ba_resp->txed_2_done;
1313 info->status.ampdu_len = ba_resp->txed;
1314
1315 } else {
1316 info->status.ampdu_ack_len = successes;
1317 info->status.ampdu_len = agg->frame_count;
1318 }
1319 iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1320
1321 return 0;
1322 }
1323
1324 /**
1325 * translate ucode response to mac80211 tx status control values
1326 */
1327 void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
1328 struct ieee80211_tx_info *info)
1329 {
1330 struct ieee80211_tx_rate *r = &info->control.rates[0];
1331
1332 info->antenna_sel_tx =
1333 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1334 if (rate_n_flags & RATE_MCS_HT_MSK)
1335 r->flags |= IEEE80211_TX_RC_MCS;
1336 if (rate_n_flags & RATE_MCS_GF_MSK)
1337 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1338 if (rate_n_flags & RATE_MCS_HT40_MSK)
1339 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1340 if (rate_n_flags & RATE_MCS_DUP_MSK)
1341 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1342 if (rate_n_flags & RATE_MCS_SGI_MSK)
1343 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1344 r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1345 }
1346
1347 /**
1348 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1349 *
1350 * Handles block-acknowledge notification from device, which reports success
1351 * of frames sent via aggregation.
1352 */
1353 void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
1354 struct iwl_rx_mem_buffer *rxb)
1355 {
1356 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1357 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1358 struct iwl_tx_queue *txq = NULL;
1359 struct iwl_ht_agg *agg;
1360 int index;
1361 int sta_id;
1362 int tid;
1363 unsigned long flags;
1364
1365 /* "flow" corresponds to Tx queue */
1366 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1367
1368 /* "ssn" is start of block-ack Tx window, corresponds to index
1369 * (in Tx queue's circular buffer) of first TFD/frame in window */
1370 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1371
1372 if (scd_flow >= priv->hw_params.max_txq_num) {
1373 IWL_ERR(priv,
1374 "BUG_ON scd_flow is bigger than number of queues\n");
1375 return;
1376 }
1377
1378 txq = &priv->txq[scd_flow];
1379 sta_id = ba_resp->sta_id;
1380 tid = ba_resp->tid;
1381 agg = &priv->stations[sta_id].tid[tid].agg;
1382 if (unlikely(agg->txq_id != scd_flow)) {
1383 /*
1384 * FIXME: this is a uCode bug which need to be addressed,
1385 * log the information and return for now!
1386 * since it is possible happen very often and in order
1387 * not to fill the syslog, don't enable the logging by default
1388 */
1389 IWL_DEBUG_TX_REPLY(priv,
1390 "BA scd_flow %d does not match txq_id %d\n",
1391 scd_flow, agg->txq_id);
1392 return;
1393 }
1394
1395 /* Find index just before block-ack window */
1396 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1397
1398 spin_lock_irqsave(&priv->sta_lock, flags);
1399
1400 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1401 "sta_id = %d\n",
1402 agg->wait_for_ba,
1403 (u8 *) &ba_resp->sta_addr_lo32,
1404 ba_resp->sta_id);
1405 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1406 "%d, scd_ssn = %d\n",
1407 ba_resp->tid,
1408 ba_resp->seq_ctl,
1409 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1410 ba_resp->scd_flow,
1411 ba_resp->scd_ssn);
1412 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n",
1413 agg->start_idx,
1414 (unsigned long long)agg->bitmap);
1415
1416 /* Update driver's record of ACK vs. not for each frame in window */
1417 iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1418
1419 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1420 * block-ack window (we assume that they've been successfully
1421 * transmitted ... if not, it's too late anyway). */
1422 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1423 /* calculate mac80211 ampdu sw queue to wake */
1424 int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index);
1425 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1426
1427 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1428 priv->mac80211_registered &&
1429 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1430 iwl_wake_queue(priv, txq);
1431
1432 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
1433 }
1434
1435 spin_unlock_irqrestore(&priv->sta_lock, flags);
1436 }
1437
1438 #ifdef CONFIG_IWLWIFI_DEBUG
1439 const char *iwl_get_tx_fail_reason(u32 status)
1440 {
1441 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
1442 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
1443
1444 switch (status & TX_STATUS_MSK) {
1445 case TX_STATUS_SUCCESS:
1446 return "SUCCESS";
1447 TX_STATUS_POSTPONE(DELAY);
1448 TX_STATUS_POSTPONE(FEW_BYTES);
1449 TX_STATUS_POSTPONE(BT_PRIO);
1450 TX_STATUS_POSTPONE(QUIET_PERIOD);
1451 TX_STATUS_POSTPONE(CALC_TTAK);
1452 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
1453 TX_STATUS_FAIL(SHORT_LIMIT);
1454 TX_STATUS_FAIL(LONG_LIMIT);
1455 TX_STATUS_FAIL(FIFO_UNDERRUN);
1456 TX_STATUS_FAIL(DRAIN_FLOW);
1457 TX_STATUS_FAIL(RFKILL_FLUSH);
1458 TX_STATUS_FAIL(LIFE_EXPIRE);
1459 TX_STATUS_FAIL(DEST_PS);
1460 TX_STATUS_FAIL(HOST_ABORTED);
1461 TX_STATUS_FAIL(BT_RETRY);
1462 TX_STATUS_FAIL(STA_INVALID);
1463 TX_STATUS_FAIL(FRAG_DROPPED);
1464 TX_STATUS_FAIL(TID_DISABLE);
1465 TX_STATUS_FAIL(FIFO_FLUSHED);
1466 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
1467 TX_STATUS_FAIL(PASSIVE_NO_RX);
1468 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
1469 }
1470
1471 return "UNKNOWN";
1472
1473 #undef TX_STATUS_FAIL
1474 #undef TX_STATUS_POSTPONE
1475 }
1476 #endif /* CONFIG_IWLWIFI_DEBUG */
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