| blob | b493306a7eede0888af2cccef613c6612b579514 |
1 /*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt2500usb
23 Abstract: Data structures and registers for the rt2500usb module.
24 Supported chipsets: RT2570.
25 */
27 #ifndef RT2500USB_H
28 #define RT2500USB_H
30 /*
31 * RF chip defines.
32 */
33 #define RF2522 0x0000
34 #define RF2523 0x0001
35 #define RF2524 0x0002
36 #define RF2525 0x0003
37 #define RF2525E 0x0005
38 #define RF5222 0x0010
40 /*
41 * RT2570 version
42 */
43 #define RT2570_VERSION_B 2
44 #define RT2570_VERSION_C 3
45 #define RT2570_VERSION_D 4
47 /*
48 * Signal information.
49 * Default offset is required for RSSI <-> dBm conversion.
50 */
51 #define DEFAULT_RSSI_OFFSET 120
53 /*
54 * Register layout information.
55 */
56 #define CSR_REG_BASE 0x0400
57 #define CSR_REG_SIZE 0x0100
58 #define EEPROM_BASE 0x0000
59 #define EEPROM_SIZE 0x006a
60 #define BBP_BASE 0x0000
61 #define BBP_SIZE 0x0060
62 #define RF_BASE 0x0004
63 #define RF_SIZE 0x0010
65 /*
66 * Number of TX queues.
67 */
68 #define NUM_TX_QUEUES 2
70 /*
71 * Control/Status Registers(CSR).
72 * Some values are set in TU, whereas 1 TU == 1024 us.
73 */
75 /*
76 * MAC_CSR0: ASIC revision number.
77 */
78 #define MAC_CSR0 0x0400
80 /*
81 * MAC_CSR1: System control.
82 * SOFT_RESET: Software reset, 1: reset, 0: normal.
83 * BBP_RESET: Hardware reset, 1: reset, 0, release.
84 * HOST_READY: Host ready after initialization.
85 */
86 #define MAC_CSR1 0x0402
87 #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
88 #define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
89 #define MAC_CSR1_HOST_READY FIELD16(0x00000004)
91 /*
92 * MAC_CSR2: STA MAC register 0.
93 */
94 #define MAC_CSR2 0x0404
95 #define MAC_CSR2_BYTE0 FIELD16(0x00ff)
96 #define MAC_CSR2_BYTE1 FIELD16(0xff00)
98 /*
99 * MAC_CSR3: STA MAC register 1.
100 */
101 #define MAC_CSR3 0x0406
102 #define MAC_CSR3_BYTE2 FIELD16(0x00ff)
103 #define MAC_CSR3_BYTE3 FIELD16(0xff00)
105 /*
106 * MAC_CSR4: STA MAC register 2.
107 */
108 #define MAC_CSR4 0X0408
109 #define MAC_CSR4_BYTE4 FIELD16(0x00ff)
110 #define MAC_CSR4_BYTE5 FIELD16(0xff00)
112 /*
113 * MAC_CSR5: BSSID register 0.
114 */
115 #define MAC_CSR5 0x040a
116 #define MAC_CSR5_BYTE0 FIELD16(0x00ff)
117 #define MAC_CSR5_BYTE1 FIELD16(0xff00)
119 /*
120 * MAC_CSR6: BSSID register 1.
121 */
122 #define MAC_CSR6 0x040c
123 #define MAC_CSR6_BYTE2 FIELD16(0x00ff)
124 #define MAC_CSR6_BYTE3 FIELD16(0xff00)
126 /*
127 * MAC_CSR7: BSSID register 2.
128 */
129 #define MAC_CSR7 0x040e
130 #define MAC_CSR7_BYTE4 FIELD16(0x00ff)
131 #define MAC_CSR7_BYTE5 FIELD16(0xff00)
133 /*
134 * MAC_CSR8: Max frame length.
135 */
136 #define MAC_CSR8 0x0410
137 #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
139 /*
140 * Misc MAC_CSR registers.
141 * MAC_CSR9: Timer control.
142 * MAC_CSR10: Slot time.
143 * MAC_CSR11: SIFS.
144 * MAC_CSR12: EIFS.
145 * MAC_CSR13: Power mode0.
146 * MAC_CSR14: Power mode1.
147 * MAC_CSR15: Power saving transition0
148 * MAC_CSR16: Power saving transition1
149 */
150 #define MAC_CSR9 0x0412
151 #define MAC_CSR10 0x0414
152 #define MAC_CSR11 0x0416
153 #define MAC_CSR12 0x0418
154 #define MAC_CSR13 0x041a
155 #define MAC_CSR14 0x041c
156 #define MAC_CSR15 0x041e
157 #define MAC_CSR16 0x0420
159 /*
160 * MAC_CSR17: Manual power control / status register.
161 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
162 * SET_STATE: Set state. Write 1 to trigger, self cleared.
163 * BBP_DESIRE_STATE: BBP desired state.
164 * RF_DESIRE_STATE: RF desired state.
165 * BBP_CURRENT_STATE: BBP current state.
166 * RF_CURRENT_STATE: RF current state.
167 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
168 */
169 #define MAC_CSR17 0x0422
170 #define MAC_CSR17_SET_STATE FIELD16(0x0001)
171 #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
172 #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
173 #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
174 #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
175 #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
177 /*
178 * MAC_CSR18: Wakeup timer register.
179 * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
180 * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
181 * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
182 */
183 #define MAC_CSR18 0x0424
184 #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
185 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
186 #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
188 /*
189 * MAC_CSR19: GPIO control register.
190 */
191 #define MAC_CSR19 0x0426
192 #define MAC_CSR19_BIT0 FIELD32(0x0001)
193 #define MAC_CSR19_BIT1 FIELD32(0x0002)
194 #define MAC_CSR19_BIT2 FIELD32(0x0004)
195 #define MAC_CSR19_BIT3 FIELD32(0x0008)
196 #define MAC_CSR19_BIT4 FIELD32(0x0010)
197 #define MAC_CSR19_BIT5 FIELD32(0x0020)
198 #define MAC_CSR19_BIT6 FIELD32(0x0040)
199 #define MAC_CSR19_BIT7 FIELD32(0x0080)
201 /*
202 * MAC_CSR20: LED control register.
203 * ACTIVITY: 0: idle, 1: active.
204 * LINK: 0: linkoff, 1: linkup.
205 * ACTIVITY_POLARITY: 0: active low, 1: active high.
206 */
207 #define MAC_CSR20 0x0428
208 #define MAC_CSR20_ACTIVITY FIELD16(0x0001)
209 #define MAC_CSR20_LINK FIELD16(0x0002)
210 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
212 /*
213 * MAC_CSR21: LED control register.
214 * ON_PERIOD: On period, default 70ms.
215 * OFF_PERIOD: Off period, default 30ms.
216 */
217 #define MAC_CSR21 0x042a
218 #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
219 #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
221 /*
222 * MAC_CSR22: Collision window control register.
223 */
224 #define MAC_CSR22 0x042c
226 /*
227 * Transmit related CSRs.
228 * Some values are set in TU, whereas 1 TU == 1024 us.
229 */
231 /*
232 * TXRX_CSR0: Security control register.
233 */
234 #define TXRX_CSR0 0x0440
235 #define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
236 #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
237 #define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
239 /*
240 * TXRX_CSR1: TX configuration.
241 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
242 * TSF_OFFSET: TSF offset in MAC header.
243 * AUTO_SEQUENCE: Let ASIC control frame sequence number.
244 */
245 #define TXRX_CSR1 0x0442
246 #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
247 #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
248 #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
250 /*
251 * TXRX_CSR2: RX control.
252 * DISABLE_RX: Disable rx engine.
253 * DROP_CRC: Drop crc error.
254 * DROP_PHYSICAL: Drop physical error.
255 * DROP_CONTROL: Drop control frame.
256 * DROP_NOT_TO_ME: Drop not to me unicast frame.
257 * DROP_TODS: Drop frame tods bit is true.
258 * DROP_VERSION_ERROR: Drop version error frame.
259 * DROP_MCAST: Drop multicast frames.
260 * DROP_BCAST: Drop broadcast frames.
261 */
262 #define TXRX_CSR2 0x0444
263 #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
264 #define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
265 #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
266 #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
267 #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
268 #define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
269 #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
270 #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
271 #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
273 /*
274 * RX BBP ID registers
275 * TXRX_CSR3: CCK RX BBP ID.
276 * TXRX_CSR4: OFDM RX BBP ID.
277 */
278 #define TXRX_CSR3 0x0446
279 #define TXRX_CSR4 0x0448
281 /*
282 * TXRX_CSR5: CCK TX BBP ID0.
283 */
284 #define TXRX_CSR5 0x044a
285 #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
286 #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
287 #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
288 #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
290 /*
291 * TXRX_CSR6: CCK TX BBP ID1.
292 */
293 #define TXRX_CSR6 0x044c
294 #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
295 #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
296 #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
297 #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
299 /*
300 * TXRX_CSR7: OFDM TX BBP ID0.
301 */
302 #define TXRX_CSR7 0x044e
303 #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
304 #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
305 #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
306 #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
308 /*
309 * TXRX_CSR8: OFDM TX BBP ID1.
310 */
311 #define TXRX_CSR8 0x0450
312 #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
313 #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
314 #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
315 #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
317 /*
318 * TXRX_CSR9: TX ACK time-out.
319 */
320 #define TXRX_CSR9 0x0452
322 /*
323 * TXRX_CSR10: Auto responder control.
324 */
325 #define TXRX_CSR10 0x0454
326 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
328 /*
329 * TXRX_CSR11: Auto responder basic rate.
330 */
331 #define TXRX_CSR11 0x0456
333 /*
334 * ACK/CTS time registers.
335 */
336 #define TXRX_CSR12 0x0458
337 #define TXRX_CSR13 0x045a
338 #define TXRX_CSR14 0x045c
339 #define TXRX_CSR15 0x045e
340 #define TXRX_CSR16 0x0460
341 #define TXRX_CSR17 0x0462
343 /*
344 * TXRX_CSR18: Synchronization control register.
345 */
346 #define TXRX_CSR18 0x0464
347 #define TXRX_CSR18_OFFSET FIELD16(0x000f)
348 #define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
350 /*
351 * TXRX_CSR19: Synchronization control register.
352 * TSF_COUNT: Enable TSF auto counting.
353 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
354 * TBCN: Enable Tbcn with reload value.
355 * BEACON_GEN: Enable beacon generator.
356 */
357 #define TXRX_CSR19 0x0466
358 #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
359 #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
360 #define TXRX_CSR19_TBCN FIELD16(0x0008)
361 #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
363 /*
364 * TXRX_CSR20: Tx BEACON offset time control register.
365 * OFFSET: In units of usec.
366 * BCN_EXPECT_WINDOW: Default: 2^CWmin
367 */
368 #define TXRX_CSR20 0x0468
369 #define TXRX_CSR20_OFFSET FIELD16(0x1fff)
370 #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
372 /*
373 * TXRX_CSR21
374 */
375 #define TXRX_CSR21 0x046a
377 /*
378 * Encryption related CSRs.
379 *
380 */
382 /*
383 * SEC_CSR0: Shared key 0, word 0
384 * SEC_CSR1: Shared key 0, word 1
385 * SEC_CSR2: Shared key 0, word 2
386 * SEC_CSR3: Shared key 0, word 3
387 * SEC_CSR4: Shared key 0, word 4
388 * SEC_CSR5: Shared key 0, word 5
389 * SEC_CSR6: Shared key 0, word 6
390 * SEC_CSR7: Shared key 0, word 7
391 */
392 #define SEC_CSR0 0x0480
393 #define SEC_CSR1 0x0482
394 #define SEC_CSR2 0x0484
395 #define SEC_CSR3 0x0486
396 #define SEC_CSR4 0x0488
397 #define SEC_CSR5 0x048a
398 #define SEC_CSR6 0x048c
399 #define SEC_CSR7 0x048e
401 /*
402 * SEC_CSR8: Shared key 1, word 0
403 * SEC_CSR9: Shared key 1, word 1
404 * SEC_CSR10: Shared key 1, word 2
405 * SEC_CSR11: Shared key 1, word 3
406 * SEC_CSR12: Shared key 1, word 4
407 * SEC_CSR13: Shared key 1, word 5
408 * SEC_CSR14: Shared key 1, word 6
409 * SEC_CSR15: Shared key 1, word 7
410 */
411 #define SEC_CSR8 0x0490
412 #define SEC_CSR9 0x0492
413 #define SEC_CSR10 0x0494
414 #define SEC_CSR11 0x0496
415 #define SEC_CSR12 0x0498
416 #define SEC_CSR13 0x049a
417 #define SEC_CSR14 0x049c
418 #define SEC_CSR15 0x049e
420 /*
421 * SEC_CSR16: Shared key 2, word 0
422 * SEC_CSR17: Shared key 2, word 1
423 * SEC_CSR18: Shared key 2, word 2
424 * SEC_CSR19: Shared key 2, word 3
425 * SEC_CSR20: Shared key 2, word 4
426 * SEC_CSR21: Shared key 2, word 5
427 * SEC_CSR22: Shared key 2, word 6
428 * SEC_CSR23: Shared key 2, word 7
429 */
430 #define SEC_CSR16 0x04a0
431 #define SEC_CSR17 0x04a2
432 #define SEC_CSR18 0X04A4
433 #define SEC_CSR19 0x04a6
434 #define SEC_CSR20 0x04a8
435 #define SEC_CSR21 0x04aa
436 #define SEC_CSR22 0x04ac
437 #define SEC_CSR23 0x04ae
439 /*
440 * SEC_CSR24: Shared key 3, word 0
441 * SEC_CSR25: Shared key 3, word 1
442 * SEC_CSR26: Shared key 3, word 2
443 * SEC_CSR27: Shared key 3, word 3
444 * SEC_CSR28: Shared key 3, word 4
445 * SEC_CSR29: Shared key 3, word 5
446 * SEC_CSR30: Shared key 3, word 6
447 * SEC_CSR31: Shared key 3, word 7
448 */
449 #define SEC_CSR24 0x04b0
450 #define SEC_CSR25 0x04b2
451 #define SEC_CSR26 0x04b4
452 #define SEC_CSR27 0x04b6
453 #define SEC_CSR28 0x04b8
454 #define SEC_CSR29 0x04ba
455 #define SEC_CSR30 0x04bc
456 #define SEC_CSR31 0x04be
458 #define KEY_ENTRY(__idx) \
459 ( SEC_CSR0 + ((__idx) * 16) )
461 /*
462 * PHY control registers.
463 */
465 /*
466 * PHY_CSR0: RF switching timing control.
467 */
468 #define PHY_CSR0 0x04c0
470 /*
471 * PHY_CSR1: TX PA configuration.
472 */
473 #define PHY_CSR1 0x04c2
475 /*
476 * MAC configuration registers.
477 */
479 /*
480 * PHY_CSR2: TX MAC configuration.
481 * NOTE: Both register fields are complete dummy,
482 * documentation and legacy drivers are unclear un
483 * what this register means or what fields exists.
484 */
485 #define PHY_CSR2 0x04c4
486 #define PHY_CSR2_LNA FIELD16(0x0002)
487 #define PHY_CSR2_LNA_MODE FIELD16(0x3000)
489 /*
490 * PHY_CSR3: RX MAC configuration.
491 */
492 #define PHY_CSR3 0x04c6
494 /*
495 * PHY_CSR4: Interface configuration.
496 */
497 #define PHY_CSR4 0x04c8
498 #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
500 /*
501 * BBP pre-TX registers.
502 * PHY_CSR5: BBP pre-TX CCK.
503 */
504 #define PHY_CSR5 0x04ca
505 #define PHY_CSR5_CCK FIELD16(0x0003)
506 #define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
508 /*
509 * BBP pre-TX registers.
510 * PHY_CSR6: BBP pre-TX OFDM.
511 */
512 #define PHY_CSR6 0x04cc
513 #define PHY_CSR6_OFDM FIELD16(0x0003)
514 #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
516 /*
517 * PHY_CSR7: BBP access register 0.
518 * BBP_DATA: BBP data.
519 * BBP_REG_ID: BBP register ID.
520 * BBP_READ_CONTROL: 0: write, 1: read.
521 */
522 #define PHY_CSR7 0x04ce
523 #define PHY_CSR7_DATA FIELD16(0x00ff)
524 #define PHY_CSR7_REG_ID FIELD16(0x7f00)
525 #define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
527 /*
528 * PHY_CSR8: BBP access register 1.
529 * BBP_BUSY: ASIC is busy execute BBP programming.
530 */
531 #define PHY_CSR8 0x04d0
532 #define PHY_CSR8_BUSY FIELD16(0x0001)
534 /*
535 * PHY_CSR9: RF access register.
536 * RF_VALUE: Register value + id to program into rf/if.
537 */
538 #define PHY_CSR9 0x04d2
539 #define PHY_CSR9_RF_VALUE FIELD16(0xffff)
541 /*
542 * PHY_CSR10: RF access register.
543 * RF_VALUE: Register value + id to program into rf/if.
544 * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
545 * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
546 * RF_PLL_LD: Rf pll_ld status.
547 * RF_BUSY: 1: asic is busy execute rf programming.
548 */
549 #define PHY_CSR10 0x04d4
550 #define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
551 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
552 #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
553 #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
554 #define PHY_CSR10_RF_BUSY FIELD16(0x8000)
556 /*
557 * STA_CSR0: FCS error count.
558 * FCS_ERROR: FCS error count, cleared when read.
559 */
560 #define STA_CSR0 0x04e0
561 #define STA_CSR0_FCS_ERROR FIELD16(0xffff)
563 /*
564 * STA_CSR1: PLCP error count.
565 */
566 #define STA_CSR1 0x04e2
568 /*
569 * STA_CSR2: LONG error count.
570 */
571 #define STA_CSR2 0x04e4
573 /*
574 * STA_CSR3: CCA false alarm.
575 * FALSE_CCA_ERROR: False CCA error count, cleared when read.
576 */
577 #define STA_CSR3 0x04e6
578 #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
580 /*
581 * STA_CSR4: RX FIFO overflow.
582 */
583 #define STA_CSR4 0x04e8
585 /*
586 * STA_CSR5: Beacon sent counter.
587 */
588 #define STA_CSR5 0x04ea
590 /*
591 * Statistics registers
592 */
593 #define STA_CSR6 0x04ec
594 #define STA_CSR7 0x04ee
595 #define STA_CSR8 0x04f0
596 #define STA_CSR9 0x04f2
597 #define STA_CSR10 0x04f4
599 /*
600 * BBP registers.
601 * The wordsize of the BBP is 8 bits.
602 */
604 /*
605 * R2: TX antenna control
606 */
607 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
608 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
610 /*
611 * R14: RX antenna control
612 */
613 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
614 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
616 /*
617 * RF registers.
618 */
620 /*
621 * RF 1
622 */
623 #define RF1_TUNER FIELD32(0x00020000)
625 /*
626 * RF 3
627 */
628 #define RF3_TUNER FIELD32(0x00000100)
629 #define RF3_TXPOWER FIELD32(0x00003e00)
631 /*
632 * EEPROM contents.
633 */
635 /*
636 * HW MAC address.
637 */
638 #define EEPROM_MAC_ADDR_0 0x0002
639 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
640 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
641 #define EEPROM_MAC_ADDR1 0x0003
642 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
643 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
644 #define EEPROM_MAC_ADDR_2 0x0004
645 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
646 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
648 /*
649 * EEPROM antenna.
650 * ANTENNA_NUM: Number of antenna's.
651 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
652 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
653 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
654 * DYN_TXAGC: Dynamic TX AGC control.
655 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
656 * RF_TYPE: Rf_type of this adapter.
657 */
658 #define EEPROM_ANTENNA 0x000b
659 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
660 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
661 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
662 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
663 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
664 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
665 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
667 /*
668 * EEPROM NIC config.
669 * CARDBUS_ACCEL: 0: enable, 1: disable.
670 * DYN_BBP_TUNE: 0: enable, 1: disable.
671 * CCK_TX_POWER: CCK TX power compensation.
672 */
673 #define EEPROM_NIC 0x000c
674 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
675 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
676 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
678 /*
679 * EEPROM geography.
680 * GEO: Default geography setting for device.
681 */
682 #define EEPROM_GEOGRAPHY 0x000d
683 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
685 /*
686 * EEPROM BBP.
687 */
688 #define EEPROM_BBP_START 0x000e
689 #define EEPROM_BBP_SIZE 16
690 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
691 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
693 /*
694 * EEPROM TXPOWER
695 */
696 #define EEPROM_TXPOWER_START 0x001e
697 #define EEPROM_TXPOWER_SIZE 7
698 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
699 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
701 /*
702 * EEPROM Tuning threshold
703 */
704 #define EEPROM_BBPTUNE 0x0030
705 #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
707 /*
708 * EEPROM BBP R24 Tuning.
709 */
710 #define EEPROM_BBPTUNE_R24 0x0031
711 #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
712 #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
714 /*
715 * EEPROM BBP R25 Tuning.
716 */
717 #define EEPROM_BBPTUNE_R25 0x0032
718 #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
719 #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
721 /*
722 * EEPROM BBP R24 Tuning.
723 */
724 #define EEPROM_BBPTUNE_R61 0x0033
725 #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
726 #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
728 /*
729 * EEPROM BBP VGC Tuning.
730 */
731 #define EEPROM_BBPTUNE_VGC 0x0034
732 #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
733 #define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00)
735 /*
736 * EEPROM BBP R17 Tuning.
737 */
738 #define EEPROM_BBPTUNE_R17 0x0035
739 #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
740 #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
742 /*
743 * RSSI <-> dBm offset calibration
744 */
745 #define EEPROM_CALIBRATE_OFFSET 0x0036
746 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
748 /*
749 * DMA descriptor defines.
750 */
751 #define TXD_DESC_SIZE ( 5 * sizeof(__le32) )
752 #define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
754 /*
755 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
756 */
758 /*
759 * Word0
760 */
761 #define TXD_W0_PACKET_ID FIELD32(0x0000000f)
762 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
763 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
764 #define TXD_W0_ACK FIELD32(0x00000200)
765 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
766 #define TXD_W0_OFDM FIELD32(0x00000800)
767 #define TXD_W0_NEW_SEQ FIELD32(0x00001000)
768 #define TXD_W0_IFS FIELD32(0x00006000)
769 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
770 #define TXD_W0_CIPHER FIELD32(0x20000000)
771 #define TXD_W0_KEY_ID FIELD32(0xc0000000)
773 /*
774 * Word1
775 */
776 #define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
777 #define TXD_W1_AIFS FIELD32(0x000000c0)
778 #define TXD_W1_CWMIN FIELD32(0x00000f00)
779 #define TXD_W1_CWMAX FIELD32(0x0000f000)
781 /*
782 * Word2: PLCP information
783 */
784 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
785 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
786 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
787 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
789 /*
790 * Word3
791 */
792 #define TXD_W3_IV FIELD32(0xffffffff)
794 /*
795 * Word4
796 */
797 #define TXD_W4_EIV FIELD32(0xffffffff)
799 /*
800 * RX descriptor format for RX Ring.
801 */
803 /*
804 * Word0
805 */
806 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
807 #define RXD_W0_MULTICAST FIELD32(0x00000004)
808 #define RXD_W0_BROADCAST FIELD32(0x00000008)
809 #define RXD_W0_MY_BSS FIELD32(0x00000010)
810 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
811 #define RXD_W0_OFDM FIELD32(0x00000040)
812 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
813 #define RXD_W0_CIPHER FIELD32(0x00000100)
814 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
815 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
817 /*
818 * Word1
819 */
820 #define RXD_W1_RSSI FIELD32(0x000000ff)
821 #define RXD_W1_SIGNAL FIELD32(0x0000ff00)
823 /*
824 * Word2
825 */
826 #define RXD_W2_IV FIELD32(0xffffffff)
828 /*
829 * Word3
830 */
831 #define RXD_W3_EIV FIELD32(0xffffffff)
833 /*
834 * Macros for converting txpower from EEPROM to mac80211 value
835 * and from mac80211 value to register value.
836 */
837 #define MIN_TXPOWER 0
838 #define MAX_TXPOWER 31
839 #define DEFAULT_TXPOWER 24
841 #define TXPOWER_FROM_DEV(__txpower) \
842 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
844 #define TXPOWER_TO_DEV(__txpower) \
845 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)