drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00pci.h"
  45 #include "rt2x00soc.h"
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800pci.h"
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static int modparam_nohwcrypt = 0;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  58 {
  59         unsigned int i;
  60         u32 reg;
  61
  62         /*
  63          * SOC devices don't support MCU requests.
  64          */
  65         if (rt2x00_is_soc(rt2x00dev))
  66                 return;
  67
  68         for (i = 0; i < 200; i++) {
  69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  70
  71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  75                         break;
  76
  77                 udelay(REGISTER_BUSY_DELAY);
  78         }
  79
  80         if (i == 200)
  81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  82
  83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  85 }
  86
  87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  89 {
  90         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
  91
  92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  93
  94         iounmap(base_addr);
  95 }
  96 #else
  97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  98 {
  99 }
 100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
 101
 102 #ifdef CONFIG_PCI
 103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 104 {
 105         struct rt2x00_dev *rt2x00dev = eeprom->data;
 106         u32 reg;
 107
 108         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 109
 110         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 111         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 112         eeprom->reg_data_clock =
 113             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 114         eeprom->reg_chip_select =
 115             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 116 }
 117
 118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 119 {
 120         struct rt2x00_dev *rt2x00dev = eeprom->data;
 121         u32 reg = 0;
 122
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 126                            !!eeprom->reg_data_clock);
 127         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 128                            !!eeprom->reg_chip_select);
 129
 130         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 131 }
 132
 133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 134 {
 135         struct eeprom_93cx6 eeprom;
 136         u32 reg;
 137
 138         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 139
 140         eeprom.data = rt2x00dev;
 141         eeprom.register_read = rt2800pci_eepromregister_read;
 142         eeprom.register_write = rt2800pci_eepromregister_write;
 143         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 144         {
 145         case 0:
 146                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 147                 break;
 148         case 1:
 149                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 150                 break;
 151         default:
 152                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 153                 break;
 154         }
 155         eeprom.reg_data_in = 0;
 156         eeprom.reg_data_out = 0;
 157         eeprom.reg_data_clock = 0;
 158         eeprom.reg_chip_select = 0;
 159
 160         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 161                                EEPROM_SIZE / sizeof(u16));
 162 }
 163
 164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 165 {
 166         return rt2800_efuse_detect(rt2x00dev);
 167 }
 168
 169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 170 {
 171         rt2800_read_eeprom_efuse(rt2x00dev);
 172 }
 173 #else
 174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 175 {
 176 }
 177
 178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 179 {
 180         return 0;
 181 }
 182
 183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 184 {
 185 }
 186 #endif /* CONFIG_PCI */
 187
 188 /*
 189  * Queue handlers.
 190  */
 191 static void rt2800pci_start_queue(struct data_queue *queue)
 192 {
 193         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 194         u32 reg;
 195
 196         switch (queue->qid) {
 197         case QID_RX:
 198                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 199                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 200                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 201                 break;
 202         case QID_BEACON:
 203                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 204                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 205                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 206                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 207                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 208                 break;
 209         default:
 210                 break;
 211         };
 212 }
 213
 214 static void rt2800pci_kick_queue(struct data_queue *queue)
 215 {
 216         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 217         struct queue_entry *entry;
 218
 219         switch (queue->qid) {
 220         case QID_AC_VO:
 221         case QID_AC_VI:
 222         case QID_AC_BE:
 223         case QID_AC_BK:
 224                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 225                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
 226                 break;
 227         case QID_MGMT:
 228                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 229                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
 230                 break;
 231         default:
 232                 break;
 233         }
 234 }
 235
 236 static void rt2800pci_stop_queue(struct data_queue *queue)
 237 {
 238         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 239         u32 reg;
 240
 241         switch (queue->qid) {
 242         case QID_RX:
 243                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 244                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 245                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 246                 break;
 247         case QID_BEACON:
 248                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 249                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
 250                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
 251                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 252                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 253                 break;
 254         default:
 255                 break;
 256         }
 257 }
 258
 259 /*
 260  * Firmware functions
 261  */
 262 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 263 {
 264         return FIRMWARE_RT2860;
 265 }
 266
 267 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 268                                     const u8 *data, const size_t len)
 269 {
 270         u32 reg;
 271
 272         /*
 273          * enable Host program ram write selection
 274          */
 275         reg = 0;
 276         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 277         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 278
 279         /*
 280          * Write firmware to device.
 281          */
 282         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 283                                    data, len);
 284
 285         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 286         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 287
 288         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 289         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 290
 291         return 0;
 292 }
 293
 294 /*
 295  * Initialization functions.
 296  */
 297 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 298 {
 299         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 300         u32 word;
 301
 302         if (entry->queue->qid == QID_RX) {
 303                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 304
 305                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 306         } else {
 307                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 308
 309                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 310         }
 311 }
 312
 313 static void rt2800pci_clear_entry(struct queue_entry *entry)
 314 {
 315         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 316         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 317         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 318         u32 word;
 319
 320         if (entry->queue->qid == QID_RX) {
 321                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 322                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 323                 rt2x00_desc_write(entry_priv->desc, 0, word);
 324
 325                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 326                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 327                 rt2x00_desc_write(entry_priv->desc, 1, word);
 328
 329                 /*
 330                  * Set RX IDX in register to inform hardware that we have
 331                  * handled this entry and it is available for reuse again.
 332                  */
 333                 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
 334                                       entry->entry_idx);
 335         } else {
 336                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 337                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 338                 rt2x00_desc_write(entry_priv->desc, 1, word);
 339         }
 340 }
 341
 342 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 343 {
 344         struct queue_entry_priv_pci *entry_priv;
 345         u32 reg;
 346
 347         /*
 348          * Initialize registers.
 349          */
 350         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 351         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 352         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 353         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 354         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 355
 356         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 357         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 358         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 359         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 360         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 361
 362         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 363         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 364         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 365         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 366         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 367
 368         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 369         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 370         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 371         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 372         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 373
 374         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 375         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 376         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 377         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 378         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 379
 380         /*
 381          * Enable global DMA configuration
 382          */
 383         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 384         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 385         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 386         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 387         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 388
 389         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 390
 391         return 0;
 392 }
 393
 394 /*
 395  * Device state switch handlers.
 396  */
 397 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 398                                  enum dev_state state)
 399 {
 400         int mask = (state == STATE_RADIO_IRQ_ON) ||
 401                    (state == STATE_RADIO_IRQ_ON_ISR);
 402         u32 reg;
 403
 404         /*
 405          * When interrupts are being enabled, the interrupt registers
 406          * should clear the register to assure a clean state.
 407          */
 408         if (state == STATE_RADIO_IRQ_ON) {
 409                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 410                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 411         }
 412
 413         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 414         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
 415         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
 416         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 417         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
 418         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
 419         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
 420         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
 421         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
 422         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
 423         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
 424         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
 425         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 426         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 427         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 428         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 429         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
 430         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
 431         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
 432         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 433 }
 434
 435 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 436 {
 437         u32 reg;
 438
 439         /*
 440          * Reset DMA indexes
 441          */
 442         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 443         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 444         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 445         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 446         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 447         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 448         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 449         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 450         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 451
 452         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 453         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 454
 455         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 456
 457         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 458         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 459         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 460         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 461
 462         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 463
 464         return 0;
 465 }
 466
 467 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 468 {
 469         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 470                      rt2800pci_init_queues(rt2x00dev)))
 471                 return -EIO;
 472
 473         return rt2800_enable_radio(rt2x00dev);
 474 }
 475
 476 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 477 {
 478         u32 reg;
 479
 480         rt2800_disable_radio(rt2x00dev);
 481
 482         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 483
 484         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 485         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 486         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 487         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 488         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 489         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 490         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 491         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 492         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 493
 494         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 495         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 496 }
 497
 498 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 499                                enum dev_state state)
 500 {
 501         /*
 502          * Always put the device to sleep (even when we intend to wakeup!)
 503          * if the device is booting and wasn't asleep it will return
 504          * failure when attempting to wakeup.
 505          */
 506         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
 507
 508         if (state == STATE_AWAKE) {
 509                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 510                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 511         }
 512
 513         return 0;
 514 }
 515
 516 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 517                                       enum dev_state state)
 518 {
 519         int retval = 0;
 520
 521         switch (state) {
 522         case STATE_RADIO_ON:
 523                 /*
 524                  * Before the radio can be enabled, the device first has
 525                  * to be woken up. After that it needs a bit of time
 526                  * to be fully awake and then the radio can be enabled.
 527                  */
 528                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 529                 msleep(1);
 530                 retval = rt2800pci_enable_radio(rt2x00dev);
 531                 break;
 532         case STATE_RADIO_OFF:
 533                 /*
 534                  * After the radio has been disabled, the device should
 535                  * be put to sleep for powersaving.
 536                  */
 537                 rt2800pci_disable_radio(rt2x00dev);
 538                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 539                 break;
 540         case STATE_RADIO_IRQ_ON:
 541         case STATE_RADIO_IRQ_ON_ISR:
 542         case STATE_RADIO_IRQ_OFF:
 543         case STATE_RADIO_IRQ_OFF_ISR:
 544                 rt2800pci_toggle_irq(rt2x00dev, state);
 545                 break;
 546         case STATE_DEEP_SLEEP:
 547         case STATE_SLEEP:
 548         case STATE_STANDBY:
 549         case STATE_AWAKE:
 550                 retval = rt2800pci_set_state(rt2x00dev, state);
 551                 break;
 552         default:
 553                 retval = -ENOTSUPP;
 554                 break;
 555         }
 556
 557         if (unlikely(retval))
 558                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 559                       state, retval);
 560
 561         return retval;
 562 }
 563
 564 /*
 565  * TX descriptor initialization
 566  */
 567 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 568 {
 569         return (__le32 *) entry->skb->data;
 570 }
 571
 572 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 573                                     struct txentry_desc *txdesc)
 574 {
 575         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 576         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 577         __le32 *txd = entry_priv->desc;
 578         u32 word;
 579
 580         /*
 581          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 582          * must contains a TXWI structure + 802.11 header + padding + 802.11
 583          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 584          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 585          * data. It means that LAST_SEC0 is always 0.
 586          */
 587
 588         /*
 589          * Initialize TX descriptor
 590          */
 591         rt2x00_desc_read(txd, 0, &word);
 592         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 593         rt2x00_desc_write(txd, 0, word);
 594
 595         rt2x00_desc_read(txd, 1, &word);
 596         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
 597         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 598                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 599         rt2x00_set_field32(&word, TXD_W1_BURST,
 600                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 601         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 602         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 603         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 604         rt2x00_desc_write(txd, 1, word);
 605
 606         rt2x00_desc_read(txd, 2, &word);
 607         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 608                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 609         rt2x00_desc_write(txd, 2, word);
 610
 611         rt2x00_desc_read(txd, 3, &word);
 612         rt2x00_set_field32(&word, TXD_W3_WIV,
 613                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 614         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 615         rt2x00_desc_write(txd, 3, word);
 616
 617         /*
 618          * Register descriptor details in skb frame descriptor.
 619          */
 620         skbdesc->desc = txd;
 621         skbdesc->desc_len = TXD_DESC_SIZE;
 622 }
 623
 624 /*
 625  * RX control handlers
 626  */
 627 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 628                                   struct rxdone_entry_desc *rxdesc)
 629 {
 630         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 631         __le32 *rxd = entry_priv->desc;
 632         u32 word;
 633
 634         rt2x00_desc_read(rxd, 3, &word);
 635
 636         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 637                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 638
 639         /*
 640          * Unfortunately we don't know the cipher type used during
 641          * decryption. This prevents us from correct providing
 642          * correct statistics through debugfs.
 643          */
 644         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 645
 646         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 647                 /*
 648                  * Hardware has stripped IV/EIV data from 802.11 frame during
 649                  * decryption. Unfortunately the descriptor doesn't contain
 650                  * any fields with the EIV/IV data either, so they can't
 651                  * be restored by rt2x00lib.
 652                  */
 653                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 654
 655                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 656                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 657                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 658                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 659         }
 660
 661         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 662                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 663
 664         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 665                 rxdesc->dev_flags |= RXDONE_L2PAD;
 666
 667         /*
 668          * Process the RXWI structure that is at the start of the buffer.
 669          */
 670         rt2800_process_rxwi(entry, rxdesc);
 671 }
 672
 673 /*
 674  * Interrupt functions.
 675  */
 676 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 677 {
 678         struct ieee80211_conf conf = { .flags = 0 };
 679         struct rt2x00lib_conf libconf = { .conf = &conf };
 680
 681         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 682 }
 683
 684 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 685 {
 686         struct data_queue *queue;
 687         struct queue_entry *entry;
 688         u32 status;
 689         u8 qid;
 690
 691         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
 692                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
 693                 if (qid >= QID_RX) {
 694                         /*
 695                          * Unknown queue, this shouldn't happen. Just drop
 696                          * this tx status.
 697                          */
 698                         WARNING(rt2x00dev, "Got TX status report with "
 699                                            "unexpected pid %u, dropping\n", qid);
 700                         break;
 701                 }
 702
 703                 queue = rt2x00queue_get_queue(rt2x00dev, qid);
 704                 if (unlikely(queue == NULL)) {
 705                         /*
 706                          * The queue is NULL, this shouldn't happen. Stop
 707                          * processing here and drop the tx status
 708                          */
 709                         WARNING(rt2x00dev, "Got TX status for an unavailable "
 710                                            "queue %u, dropping\n", qid);
 711                         break;
 712                 }
 713
 714                 if (rt2x00queue_empty(queue)) {
 715                         /*
 716                          * The queue is empty. Stop processing here
 717                          * and drop the tx status.
 718                          */
 719                         WARNING(rt2x00dev, "Got TX status for an empty "
 720                                            "queue %u, dropping\n", qid);
 721                         break;
 722                 }
 723
 724                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 725                 rt2800_txdone_entry(entry, status);
 726         }
 727 }
 728
 729 static void rt2800pci_txstatus_tasklet(unsigned long data)
 730 {
 731         rt2800pci_txdone((struct rt2x00_dev *)data);
 732 }
 733
 734 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
 735 {
 736         struct rt2x00_dev *rt2x00dev = dev_instance;
 737         u32 reg = rt2x00dev->irqvalue[0];
 738
 739         /*
 740          * 1 - Pre TBTT interrupt.
 741          */
 742         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 743                 rt2x00lib_pretbtt(rt2x00dev);
 744
 745         /*
 746          * 2 - Beacondone interrupt.
 747          */
 748         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 749                 rt2x00lib_beacondone(rt2x00dev);
 750
 751         /*
 752          * 3 - Rx ring done interrupt.
 753          */
 754         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 755                 rt2x00pci_rxdone(rt2x00dev);
 756
 757         /*
 758          * 4 - Auto wakeup interrupt.
 759          */
 760         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 761                 rt2800pci_wakeup(rt2x00dev);
 762
 763         /* Enable interrupts again. */
 764         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 765                                               STATE_RADIO_IRQ_ON_ISR);
 766
 767         return IRQ_HANDLED;
 768 }
 769
 770 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
 771 {
 772         u32 status;
 773         int i;
 774
 775         /*
 776          * The TX_FIFO_STATUS interrupt needs special care. We should
 777          * read TX_STA_FIFO but we should do it immediately as otherwise
 778          * the register can overflow and we would lose status reports.
 779          *
 780          * Hence, read the TX_STA_FIFO register and copy all tx status
 781          * reports into a kernel FIFO which is handled in the txstatus
 782          * tasklet. We use a tasklet to process the tx status reports
 783          * because we can schedule the tasklet multiple times (when the
 784          * interrupt fires again during tx status processing).
 785          *
 786          * Furthermore we don't disable the TX_FIFO_STATUS
 787          * interrupt here but leave it enabled so that the TX_STA_FIFO
 788          * can also be read while the interrupt thread gets executed.
 789          *
 790          * Since we have only one producer and one consumer we don't
 791          * need to lock the kfifo.
 792          */
 793         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 794                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
 795
 796                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
 797                         break;
 798
 799                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
 800                         WARNING(rt2x00dev, "TX status FIFO overrun,"
 801                                 "drop tx status report.\n");
 802                         break;
 803                 }
 804         }
 805
 806         /* Schedule the tasklet for processing the tx status. */
 807         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 808 }
 809
 810 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 811 {
 812         struct rt2x00_dev *rt2x00dev = dev_instance;
 813         u32 reg;
 814         irqreturn_t ret = IRQ_HANDLED;
 815
 816         /* Read status and ACK all interrupts */
 817         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 818         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 819
 820         if (!reg)
 821                 return IRQ_NONE;
 822
 823         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 824                 return IRQ_HANDLED;
 825
 826         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
 827                 rt2800pci_txstatus_interrupt(rt2x00dev);
 828
 829         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
 830             rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
 831             rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
 832             rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
 833                 /*
 834                  * All other interrupts are handled in the interrupt thread.
 835                  * Store irqvalue for use in the interrupt thread.
 836                  */
 837                 rt2x00dev->irqvalue[0] = reg;
 838
 839                 /*
 840                  * Disable interrupts, will be enabled again in the
 841                  * interrupt thread.
 842                 */
 843                 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 844                                                       STATE_RADIO_IRQ_OFF_ISR);
 845
 846                 /*
 847                  * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
 848                  * tx status reports.
 849                  */
 850                 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 851                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 852                 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 853
 854                 ret = IRQ_WAKE_THREAD;
 855         }
 856
 857         return ret;
 858 }
 859
 860 /*
 861  * Device probe functions.
 862  */
 863 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 864 {
 865         /*
 866          * Read EEPROM into buffer
 867          */
 868         if (rt2x00_is_soc(rt2x00dev))
 869                 rt2800pci_read_eeprom_soc(rt2x00dev);
 870         else if (rt2800pci_efuse_detect(rt2x00dev))
 871                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 872         else
 873                 rt2800pci_read_eeprom_pci(rt2x00dev);
 874
 875         return rt2800_validate_eeprom(rt2x00dev);
 876 }
 877
 878 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
 879 {
 880         int retval;
 881
 882         /*
 883          * Allocate eeprom data.
 884          */
 885         retval = rt2800pci_validate_eeprom(rt2x00dev);
 886         if (retval)
 887                 return retval;
 888
 889         retval = rt2800_init_eeprom(rt2x00dev);
 890         if (retval)
 891                 return retval;
 892
 893         /*
 894          * Initialize hw specifications.
 895          */
 896         retval = rt2800_probe_hw_mode(rt2x00dev);
 897         if (retval)
 898                 return retval;
 899
 900         /*
 901          * This device has multiple filters for control frames
 902          * and has a separate filter for PS Poll frames.
 903          */
 904         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
 905         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
 906
 907         /*
 908          * This device has a pre tbtt interrupt and thus fetches
 909          * a new beacon directly prior to transmission.
 910          */
 911         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
 912
 913         /*
 914          * This device requires firmware.
 915          */
 916         if (!rt2x00_is_soc(rt2x00dev))
 917                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
 918         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
 919         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
 920         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
 921         __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
 922         if (!modparam_nohwcrypt)
 923                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 924         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
 925
 926         /*
 927          * Set the rssi offset.
 928          */
 929         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
 930
 931         return 0;
 932 }
 933
 934 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
 935         .tx                     = rt2x00mac_tx,
 936         .start                  = rt2x00mac_start,
 937         .stop                   = rt2x00mac_stop,
 938         .add_interface          = rt2x00mac_add_interface,
 939         .remove_interface       = rt2x00mac_remove_interface,
 940         .config                 = rt2x00mac_config,
 941         .configure_filter       = rt2x00mac_configure_filter,
 942         .set_key                = rt2x00mac_set_key,
 943         .sw_scan_start          = rt2x00mac_sw_scan_start,
 944         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
 945         .get_stats              = rt2x00mac_get_stats,
 946         .get_tkip_seq           = rt2800_get_tkip_seq,
 947         .set_rts_threshold      = rt2800_set_rts_threshold,
 948         .bss_info_changed       = rt2x00mac_bss_info_changed,
 949         .conf_tx                = rt2800_conf_tx,
 950         .get_tsf                = rt2800_get_tsf,
 951         .rfkill_poll            = rt2x00mac_rfkill_poll,
 952         .ampdu_action           = rt2800_ampdu_action,
 953         .flush                  = rt2x00mac_flush,
 954         .get_survey             = rt2800_get_survey,
 955 };
 956
 957 static const struct rt2800_ops rt2800pci_rt2800_ops = {
 958         .register_read          = rt2x00pci_register_read,
 959         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
 960         .register_write         = rt2x00pci_register_write,
 961         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
 962         .register_multiread     = rt2x00pci_register_multiread,
 963         .register_multiwrite    = rt2x00pci_register_multiwrite,
 964         .regbusy_read           = rt2x00pci_regbusy_read,
 965         .drv_write_firmware     = rt2800pci_write_firmware,
 966         .drv_init_registers     = rt2800pci_init_registers,
 967         .drv_get_txwi           = rt2800pci_get_txwi,
 968 };
 969
 970 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
 971         .irq_handler            = rt2800pci_interrupt,
 972         .irq_handler_thread     = rt2800pci_interrupt_thread,
 973         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
 974         .probe_hw               = rt2800pci_probe_hw,
 975         .get_firmware_name      = rt2800pci_get_firmware_name,
 976         .check_firmware         = rt2800_check_firmware,
 977         .load_firmware          = rt2800_load_firmware,
 978         .initialize             = rt2x00pci_initialize,
 979         .uninitialize           = rt2x00pci_uninitialize,
 980         .get_entry_state        = rt2800pci_get_entry_state,
 981         .clear_entry            = rt2800pci_clear_entry,
 982         .set_device_state       = rt2800pci_set_device_state,
 983         .rfkill_poll            = rt2800_rfkill_poll,
 984         .link_stats             = rt2800_link_stats,
 985         .reset_tuner            = rt2800_reset_tuner,
 986         .link_tuner             = rt2800_link_tuner,
 987         .start_queue            = rt2800pci_start_queue,
 988         .kick_queue             = rt2800pci_kick_queue,
 989         .stop_queue             = rt2800pci_stop_queue,
 990         .write_tx_desc          = rt2800pci_write_tx_desc,
 991         .write_tx_data          = rt2800_write_tx_data,
 992         .write_beacon           = rt2800_write_beacon,
 993         .fill_rxdone            = rt2800pci_fill_rxdone,
 994         .config_shared_key      = rt2800_config_shared_key,
 995         .config_pairwise_key    = rt2800_config_pairwise_key,
 996         .config_filter          = rt2800_config_filter,
 997         .config_intf            = rt2800_config_intf,
 998         .config_erp             = rt2800_config_erp,
 999         .config_ant             = rt2800_config_ant,
1000         .config                 = rt2800_config,
1001 };
1002
1003 static const struct data_queue_desc rt2800pci_queue_rx = {
1004         .entry_num              = 128,
1005         .data_size              = AGGREGATION_SIZE,
1006         .desc_size              = RXD_DESC_SIZE,
1007         .priv_size              = sizeof(struct queue_entry_priv_pci),
1008 };
1009
1010 static const struct data_queue_desc rt2800pci_queue_tx = {
1011         .entry_num              = 64,
1012         .data_size              = AGGREGATION_SIZE,
1013         .desc_size              = TXD_DESC_SIZE,
1014         .priv_size              = sizeof(struct queue_entry_priv_pci),
1015 };
1016
1017 static const struct data_queue_desc rt2800pci_queue_bcn = {
1018         .entry_num              = 8,
1019         .data_size              = 0, /* No DMA required for beacons */
1020         .desc_size              = TXWI_DESC_SIZE,
1021         .priv_size              = sizeof(struct queue_entry_priv_pci),
1022 };
1023
1024 static const struct rt2x00_ops rt2800pci_ops = {
1025         .name                   = KBUILD_MODNAME,
1026         .max_sta_intf           = 1,
1027         .max_ap_intf            = 8,
1028         .eeprom_size            = EEPROM_SIZE,
1029         .rf_size                = RF_SIZE,
1030         .tx_queues              = NUM_TX_QUEUES,
1031         .extra_tx_headroom      = TXWI_DESC_SIZE,
1032         .rx                     = &rt2800pci_queue_rx,
1033         .tx                     = &rt2800pci_queue_tx,
1034         .bcn                    = &rt2800pci_queue_bcn,
1035         .lib                    = &rt2800pci_rt2x00_ops,
1036         .drv                    = &rt2800pci_rt2800_ops,
1037         .hw                     = &rt2800pci_mac80211_ops,
1038 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1039         .debugfs                = &rt2800_rt2x00debug,
1040 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1041 };
1042
1043 /*
1044  * RT2800pci module information.
1045  */
1046 #ifdef CONFIG_PCI
1047 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1048         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1049         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1050         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1051         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1052         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1053         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1054         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1055         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1056         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1057         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1058         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1059         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1060         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1061         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1062         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1063         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1064 #ifdef CONFIG_RT2800PCI_RT33XX
1065         { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1066 #endif
1067 #ifdef CONFIG_RT2800PCI_RT35XX
1068         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1069         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1070         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1071         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1072         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1073 #endif
1074         { 0, }
1075 };
1076 #endif /* CONFIG_PCI */
1077
1078 MODULE_AUTHOR(DRV_PROJECT);
1079 MODULE_VERSION(DRV_VERSION);
1080 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1081 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1082 #ifdef CONFIG_PCI
1083 MODULE_FIRMWARE(FIRMWARE_RT2860);
1084 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1085 #endif /* CONFIG_PCI */
1086 MODULE_LICENSE("GPL");
1087
1088 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1089 static int rt2800soc_probe(struct platform_device *pdev)
1090 {
1091         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1092 }
1093
1094 static struct platform_driver rt2800soc_driver = {
1095         .driver         = {
1096                 .name           = "rt2800_wmac",
1097                 .owner          = THIS_MODULE,
1098                 .mod_name       = KBUILD_MODNAME,
1099         },
1100         .probe          = rt2800soc_probe,
1101         .remove         = __devexit_p(rt2x00soc_remove),
1102         .suspend        = rt2x00soc_suspend,
1103         .resume         = rt2x00soc_resume,
1104 };
1105 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1106
1107 #ifdef CONFIG_PCI
1108 static struct pci_driver rt2800pci_driver = {
1109         .name           = KBUILD_MODNAME,
1110         .id_table       = rt2800pci_device_table,
1111         .probe          = rt2x00pci_probe,
1112         .remove         = __devexit_p(rt2x00pci_remove),
1113         .suspend        = rt2x00pci_suspend,
1114         .resume         = rt2x00pci_resume,
1115 };
1116 #endif /* CONFIG_PCI */
1117
1118 static int __init rt2800pci_init(void)
1119 {
1120         int ret = 0;
1121
1122 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1123         ret = platform_driver_register(&rt2800soc_driver);
1124         if (ret)
1125                 return ret;
1126 #endif
1127 #ifdef CONFIG_PCI
1128         ret = pci_register_driver(&rt2800pci_driver);
1129         if (ret) {
1130 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1131                 platform_driver_unregister(&rt2800soc_driver);
1132 #endif
1133                 return ret;
1134         }
1135 #endif
1136
1137         return ret;
1138 }
1139
1140 static void __exit rt2800pci_exit(void)
1141 {
1142 #ifdef CONFIG_PCI
1143         pci_unregister_driver(&rt2800pci_driver);
1144 #endif
1145 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1146         platform_driver_unregister(&rt2800soc_driver);
1147 #endif
1148 }
1149
1150 module_init(rt2800pci_init);
1151 module_exit(rt2800pci_exit);