2 * This file is part of wl1251
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 #ifndef __WL1251_ACX_H__
24 #define __WL1251_ACX_H__
29 /* Target's information element */
31 struct wl1251_cmd_header cmd
;
33 /* acx (or information element) header */
36 /* payload length (not including headers */
40 struct acx_error_counter
{
41 struct acx_header header
;
43 /* The number of PLCP errors since the last time this */
44 /* information element was interrogated. This field is */
45 /* automatically cleared when it is interrogated.*/
48 /* The number of FCS errors since the last time this */
49 /* information element was interrogated. This field is */
50 /* automatically cleared when it is interrogated.*/
53 /* The number of MPDUs without PLCP header errors received*/
54 /* since the last time this information element was interrogated. */
55 /* This field is automatically cleared when it is interrogated.*/
58 /* the number of missed sequence numbers in the squentially */
59 /* values of frames seq numbers */
64 struct acx_header header
;
67 * The WiLink firmware version, an ASCII string x.x.x.x,
68 * that uniquely identifies the current firmware.
69 * The left most digit is incremented each time a
70 * significant change is made to the firmware, such as
71 * code redesign or new platform support.
72 * The second digit is incremented when major enhancements
73 * are added or major fixes are made.
74 * The third digit is incremented for each GA release.
75 * The fourth digit is incremented for each build.
76 * The first two digits identify a firmware release version,
77 * in other words, a unique set of features.
78 * The first three digits identify a GA release.
83 * This 4 byte field specifies the WiLink hardware version.
84 * bits 0 - 15: Reserved.
85 * bits 16 - 23: Version ID - The WiLink version ID
86 * (1 = first spin, 2 = second spin, and so on).
87 * bits 24 - 31: Chip ID - The WiLink chip ID.
92 enum wl1251_psm_mode
{
99 /* Extreme low power */
103 struct acx_sleep_auth
{
104 struct acx_header header
;
106 /* The sleep level authorization of the device. */
107 /* 0 - Always active*/
108 /* 1 - Power down mode: light / fast sleep*/
109 /* 2 - ELP mode: Deep / Max sleep*/
115 HOSTIF_PCI_MASTER_HOST_INDIRECT
,
116 HOSTIF_PCI_MASTER_HOST_DIRECT
,
119 HOSTIF_DONTCARE
= 0xFF
122 #define DEFAULT_UCAST_PRIORITY 0
123 #define DEFAULT_RX_Q_PRIORITY 0
124 #define DEFAULT_NUM_STATIONS 1
125 #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
126 #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
127 #define TRACE_BUFFER_MAX_SIZE 256
129 #define DP_RX_PACKET_RING_CHUNK_SIZE 1600
130 #define DP_TX_PACKET_RING_CHUNK_SIZE 1600
131 #define DP_RX_PACKET_RING_CHUNK_NUM 2
132 #define DP_TX_PACKET_RING_CHUNK_NUM 2
133 #define DP_TX_COMPLETE_TIME_OUT 20
134 #define FW_TX_CMPLT_BLOCK_SIZE 16
136 struct acx_data_path_params
{
137 struct acx_header header
;
139 u16 rx_packet_ring_chunk_size
;
140 u16 tx_packet_ring_chunk_size
;
142 u8 rx_packet_ring_chunk_num
;
143 u8 tx_packet_ring_chunk_num
;
146 * Maximum number of packets that can be gathered
147 * in the TX complete ring before an interrupt
150 u8 tx_complete_threshold
;
152 /* Number of pending TX complete entries in cyclic ring.*/
153 u8 tx_complete_ring_depth
;
156 * Max num microseconds since a packet enters the TX
157 * complete ring until an interrupt is generated.
159 u32 tx_complete_timeout
;
163 struct acx_data_path_params_resp
{
164 struct acx_header header
;
166 u16 rx_packet_ring_chunk_size
;
167 u16 tx_packet_ring_chunk_size
;
169 u8 rx_packet_ring_chunk_num
;
170 u8 tx_packet_ring_chunk_num
;
174 u32 rx_packet_ring_addr
;
175 u32 tx_packet_ring_addr
;
180 u32 tx_complete_addr
;
183 #define TX_MSDU_LIFETIME_MIN 0
184 #define TX_MSDU_LIFETIME_MAX 3000
185 #define TX_MSDU_LIFETIME_DEF 512
186 #define RX_MSDU_LIFETIME_MIN 0
187 #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
188 #define RX_MSDU_LIFETIME_DEF 512000
190 struct acx_rx_msdu_lifetime
{
191 struct acx_header header
;
194 * The maximum amount of time, in TU, before the
195 * firmware discards the MSDU.
201 * RX Config Options Table
205 * 13 Copy RX Status - when set, write three receive status words
206 * to top of rx'd MPDUs.
207 * When cleared, do not write three status words (added rev 1.5)
209 * 11 RX Complete upon FCS error - when set, give rx complete
210 * interrupt for FCS errors, after the rx filtering, e.g. unicast
211 * frames not to us with FCS error will not generate an interrupt.
212 * 10 SSID Filter Enable - When set, the WiLink discards all beacon,
213 * probe request, and probe response frames with an SSID that does
214 * not match the SSID specified by the host in the START/JOIN
216 * When clear, the WiLink receives frames with any SSID.
217 * 9 Broadcast Filter Enable - When set, the WiLink discards all
218 * broadcast frames. When clear, the WiLink receives all received
221 * 5 BSSID Filter Enable - When set, the WiLink discards any frames
222 * with a BSSID that does not match the BSSID specified by the
224 * When clear, the WiLink receives frames from any BSSID.
225 * 4 MAC Addr Filter - When set, the WiLink discards any frames
226 * with a destination address that does not match the MAC address
228 * When clear, the WiLink receives frames destined to any MAC
230 * 3 Promiscuous - When set, the WiLink receives all valid frames
231 * (i.e., all frames that pass the FCS check).
232 * When clear, only frames that pass the other filters specified
234 * 2 FCS - When set, the WiLink includes the FCS with the received
236 * When cleared, the FCS is discarded.
237 * 1 PLCP header - When set, write all data from baseband to frame
238 * buffer including PHY header.
239 * 0 Reserved - Always equal to 0.
241 * RX Filter Options Table
244 * 31:12 Reserved - Always equal to 0.
245 * 11 Association - When set, the WiLink receives all association
246 * related frames (association request/response, reassocation
247 * request/response, and disassociation). When clear, these frames
249 * 10 Auth/De auth - When set, the WiLink receives all authentication
250 * and de-authentication frames. When clear, these frames are
252 * 9 Beacon - When set, the WiLink receives all beacon frames.
253 * When clear, these frames are discarded.
254 * 8 Contention Free - When set, the WiLink receives all contention
256 * When clear, these frames are discarded.
257 * 7 Control - When set, the WiLink receives all control frames.
258 * When clear, these frames are discarded.
259 * 6 Data - When set, the WiLink receives all data frames.
260 * When clear, these frames are discarded.
261 * 5 FCS Error - When set, the WiLink receives frames that have FCS
263 * When clear, these frames are discarded.
264 * 4 Management - When set, the WiLink receives all management
266 * When clear, these frames are discarded.
267 * 3 Probe Request - When set, the WiLink receives all probe request
269 * When clear, these frames are discarded.
270 * 2 Probe Response - When set, the WiLink receives all probe
272 * When clear, these frames are discarded.
273 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
275 * When clear, these frames are discarded.
276 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames
277 * that have reserved frame types and sub types as defined by the
278 * 802.11 specification.
279 * When clear, these frames are discarded.
281 struct acx_rx_config
{
282 struct acx_header header
;
293 QOS_HIGHEST_AC_INDEX
= QOS_AC_VO
,
296 #define MAX_NUM_OF_AC (QOS_HIGHEST_AC_INDEX+1)
297 #define FIRST_AC_INDEX QOS_AC_BE
298 #define MAX_NUM_OF_802_1d_TAGS 8
299 #define AC_PARAMS_MAX_TSID 15
300 #define MAX_APSD_CONF 0xffff
302 #define QOS_TX_HIGH_MIN (0)
303 #define QOS_TX_HIGH_MAX (100)
305 #define QOS_TX_HIGH_BK_DEF (25)
306 #define QOS_TX_HIGH_BE_DEF (35)
307 #define QOS_TX_HIGH_VI_DEF (35)
308 #define QOS_TX_HIGH_VO_DEF (35)
310 #define QOS_TX_LOW_BK_DEF (15)
311 #define QOS_TX_LOW_BE_DEF (25)
312 #define QOS_TX_LOW_VI_DEF (25)
313 #define QOS_TX_LOW_VO_DEF (25)
315 struct acx_tx_queue_qos_config
{
316 struct acx_header header
;
321 /* Max number of blocks allowd in the queue */
324 /* Lowest memory blocks guaranteed for this queue */
328 struct acx_packet_detection
{
329 struct acx_header header
;
338 DEFAULT_SLOT_TIME
= SLOT_TIME_SHORT
,
339 MAX_SLOT_TIMES
= 0xFF
342 #define STATION_WONE_INDEX 0
345 struct acx_header header
;
347 u8 wone_index
; /* Reserved */
353 #define ADDRESS_GROUP_MAX (8)
354 #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ADDRESS_GROUP_MAX)
356 struct acx_dot11_grp_addr_tbl
{
357 struct acx_header header
;
362 u8 mac_table
[ADDRESS_GROUP_MAX_LEN
];
366 #define RX_TIMEOUT_PS_POLL_MIN 0
367 #define RX_TIMEOUT_PS_POLL_MAX (200000)
368 #define RX_TIMEOUT_PS_POLL_DEF (15)
369 #define RX_TIMEOUT_UPSD_MIN 0
370 #define RX_TIMEOUT_UPSD_MAX (200000)
371 #define RX_TIMEOUT_UPSD_DEF (15)
373 struct acx_rx_timeout
{
374 struct acx_header header
;
377 * The longest time the STA will wait to receive
378 * traffic from the AP after a PS-poll has been
384 * The longest time the STA will wait to receive
385 * traffic from the AP after a frame has been sent
386 * from an UPSD enabled queue.
391 #define RTS_THRESHOLD_MIN 0
392 #define RTS_THRESHOLD_MAX 4096
393 #define RTS_THRESHOLD_DEF 2347
395 struct acx_rts_threshold
{
396 struct acx_header header
;
402 struct acx_beacon_filter_option
{
403 struct acx_header header
;
408 * The number of beacons without the unicast TIM
409 * bit set that the firmware buffers before
410 * signaling the host about ready frames.
411 * When set to 0 and the filter is enabled, beacons
412 * without the unicast TIM bit set are dropped.
419 * ACXBeaconFilterEntry (not 221)
420 * Byte Offset Size (Bytes) Definition
421 * =========== ============ ==========
423 * 1 1 Treatment bit mask
425 * ACXBeaconFilterEntry (221)
426 * Byte Offset Size (Bytes) Definition
427 * =========== ============ ==========
429 * 1 1 Treatment bit mask
435 * Treatment bit mask - The information element handling:
436 * bit 0 - The information element is compared and transferred
438 * bit 1 - The information element is transferred to the host
439 * with each appearance or disappearance.
440 * Note that both bits can be set at the same time.
442 #define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
443 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
444 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
445 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
446 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
447 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
448 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
449 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
451 #define BEACON_RULE_PASS_ON_CHANGE BIT(0)
452 #define BEACON_RULE_PASS_ON_APPEARANCE BIT(1)
454 #define BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN (37)
456 struct acx_beacon_filter_ie_table
{
457 struct acx_header header
;
461 u8 table
[BEACON_FILTER_TABLE_MAX_SIZE
];
464 #define SYNCH_FAIL_DEFAULT_THRESHOLD 10 /* number of beacons */
465 #define NO_BEACON_DEFAULT_TIMEOUT (500) /* in microseconds */
467 struct acx_conn_monit_params
{
468 struct acx_header header
;
470 u32 synch_fail_thold
; /* number of beacons missed */
471 u32 bss_lose_timeout
; /* number of TU's from synch fail */
477 SG_SENSE_NO_ACTIVITY
,
481 struct acx_bt_wlan_coex
{
482 struct acx_header header
;
487 * 2 -> sense no active mode, i.e.
488 * an interrupt is sent upon
490 * 3 -> PTA is switched on in response
491 * to the interrupt sending.
497 #define PTA_ANTENNA_TYPE_DEF (0)
498 #define PTA_BT_HP_MAXTIME_DEF (2000)
499 #define PTA_WLAN_HP_MAX_TIME_DEF (5000)
500 #define PTA_SENSE_DISABLE_TIMER_DEF (1350)
501 #define PTA_PROTECTIVE_RX_TIME_DEF (1500)
502 #define PTA_PROTECTIVE_TX_TIME_DEF (1500)
503 #define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000)
504 #define PTA_SIGNALING_TYPE_DEF (1)
505 #define PTA_AFH_LEVERAGE_ON_DEF (0)
506 #define PTA_NUMBER_QUIET_CYCLE_DEF (0)
507 #define PTA_MAX_NUM_CTS_DEF (3)
508 #define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2)
509 #define PTA_NUMBER_OF_BT_PACKETS_DEF (2)
510 #define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500)
511 #define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000)
512 #define PTA_CYCLE_TIME_FAST_DEF (8700)
513 #define PTA_RX_FOR_AVALANCHE_DEF (5)
514 #define PTA_ELP_HP_DEF (0)
515 #define PTA_ANTI_STARVE_PERIOD_DEF (500)
516 #define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4)
517 #define PTA_ALLOW_PA_SD_DEF (1)
518 #define PTA_TIME_BEFORE_BEACON_DEF (6300)
519 #define PTA_HPDM_MAX_TIME_DEF (1600)
520 #define PTA_TIME_OUT_NEXT_WLAN_DEF (2550)
521 #define PTA_AUTO_MODE_NO_CTS_DEF (0)
522 #define PTA_BT_HP_RESPECTED_DEF (3)
523 #define PTA_WLAN_RX_MIN_RATE_DEF (24)
524 #define PTA_ACK_MODE_DEF (1)
526 struct acx_bt_wlan_coex_param
{
527 struct acx_header header
;
530 * The minimum rate of a received WLAN packet in the STA,
531 * during protective mode, of which a new BT-HP request
532 * during this Rx will always be respected and gain the antenna.
536 /* Max time the BT HP will be respected. */
539 /* Max time the WLAN HP will be respected. */
540 u16 wlan_hp_max_time
;
543 * The time between the last BT activity
544 * and the moment when the sense mode returns
547 u16 sense_disable_timer
;
549 /* Time before the next BT HP instance */
553 /* range: 10-20000 default: 1500 */
554 u16 rx_time_bt_hp_fast
;
555 u16 tx_time_bt_hp_fast
;
557 /* range: 2000-65535 default: 8700 */
560 /* range: 0 - 15000 (Msec) default: 1000 */
561 u16 bt_anti_starvation_period
;
563 /* range 400-10000(Usec) default: 3000 */
564 u16 next_bt_lp_packet
;
566 /* Deafult: worst case for BT DH5 traffic */
569 /* range: 0-50000(Usec) default: 1050 */
570 u16 hp_dm_max_guard_time
;
573 * This is to prevent both BT & WLAN antenna
575 * Range: 100-50000(Usec) default:2550
577 u16 next_wlan_packet
;
579 /* 0 -> shared antenna */
591 * 1 -> from dedicated GPIO
592 * 2 -> AFH on (from host)
597 * The number of cycles during which no
598 * TX will be sent after 1 cycle of RX
599 * transaction in protective mode
604 * The maximum number of CTSs that will
605 * be sent for receiving RX packet in
611 * The number of WLAN packets
612 * transferred in common mode before
618 * The number of BT packets
619 * transferred in common mode before
624 /* range: 1-255 default: 5 */
625 u8 missed_rx_avalanche
;
627 /* range: 0-1 default: 1 */
630 /* range: 0 - 15 default: 4 */
631 u8 bt_anti_starvation_cycles
;
633 u8 ack_mode_dual_ant
;
636 * Allow PA_SD assertion/de-assertion
637 * during enabled BT activity.
642 * Enable/Disable PTA in auto mode:
643 * Support Both Active & P.S modes
645 u8 pta_auto_mode_enable
;
647 /* range: 0 - 20 default: 1 */
648 u8 bt_hp_respected_num
;
651 #define CCA_THRSH_ENABLE_ENERGY_D 0x140A
652 #define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF
654 struct acx_energy_detection
{
655 struct acx_header header
;
657 /* The RX Clear Channel Assessment threshold in the PHY */
658 u16 rx_cca_threshold
;
659 u8 tx_energy_detection
;
663 #define BCN_RX_TIMEOUT_DEF_VALUE 10000
664 #define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000
665 #define RX_BROADCAST_IN_PS_DEF_VALUE 1
666 #define CONSECUTIVE_PS_POLL_FAILURE_DEF 4
668 struct acx_beacon_broadcast
{
669 struct acx_header header
;
671 u16 beacon_rx_timeout
;
672 u16 broadcast_timeout
;
674 /* Enables receiving of broadcast packets in PS mode */
675 u8 rx_broadcast_in_ps
;
677 /* Consecutive PS Poll failures before updating the host */
678 u8 ps_poll_threshold
;
682 struct acx_event_mask
{
683 struct acx_header header
;
686 u32 high_event_mask
; /* Unused */
689 #define CFG_RX_FCS BIT(2)
690 #define CFG_RX_ALL_GOOD BIT(3)
691 #define CFG_UNI_FILTER_EN BIT(4)
692 #define CFG_BSSID_FILTER_EN BIT(5)
693 #define CFG_MC_FILTER_EN BIT(6)
694 #define CFG_MC_ADDR0_EN BIT(7)
695 #define CFG_MC_ADDR1_EN BIT(8)
696 #define CFG_BC_REJECT_EN BIT(9)
697 #define CFG_SSID_FILTER_EN BIT(10)
698 #define CFG_RX_INT_FCS_ERROR BIT(11)
699 #define CFG_RX_INT_ENCRYPTED BIT(12)
700 #define CFG_RX_WR_RX_STATUS BIT(13)
701 #define CFG_RX_FILTER_NULTI BIT(14)
702 #define CFG_RX_RESERVE BIT(15)
703 #define CFG_RX_TIMESTAMP_TSF BIT(16)
705 #define CFG_RX_RSV_EN BIT(0)
706 #define CFG_RX_RCTS_ACK BIT(1)
707 #define CFG_RX_PRSP_EN BIT(2)
708 #define CFG_RX_PREQ_EN BIT(3)
709 #define CFG_RX_MGMT_EN BIT(4)
710 #define CFG_RX_FCS_ERROR BIT(5)
711 #define CFG_RX_DATA_EN BIT(6)
712 #define CFG_RX_CTL_EN BIT(7)
713 #define CFG_RX_CF_EN BIT(8)
714 #define CFG_RX_BCN_EN BIT(9)
715 #define CFG_RX_AUTH_EN BIT(10)
716 #define CFG_RX_ASSOC_EN BIT(11)
718 #define SCAN_PASSIVE BIT(0)
719 #define SCAN_5GHZ_BAND BIT(1)
720 #define SCAN_TRIGGERED BIT(2)
721 #define SCAN_PRIORITY_HIGH BIT(3)
723 struct acx_fw_gen_frame_rates
{
724 struct acx_header header
;
726 u8 tx_ctrl_frame_rate
; /* RATE_* */
727 u8 tx_ctrl_frame_mod
; /* CCK_* or PBCC_* */
728 u8 tx_mgt_frame_rate
;
733 struct acx_dot11_station_id
{
734 struct acx_header header
;
740 struct acx_feature_config
{
741 struct acx_header header
;
744 u32 data_flow_options
;
747 struct acx_current_tx_power
{
748 struct acx_header header
;
754 struct acx_dot11_default_key
{
755 struct acx_header header
;
761 struct acx_tsf_info
{
762 struct acx_header header
;
772 enum acx_wake_up_event
{
773 WAKE_UP_EVENT_BEACON_BITMAP
= 0x01, /* Wake on every Beacon*/
774 WAKE_UP_EVENT_DTIM_BITMAP
= 0x02, /* Wake on every DTIM*/
775 WAKE_UP_EVENT_N_DTIM_BITMAP
= 0x04, /* Wake on every Nth DTIM */
776 WAKE_UP_EVENT_N_BEACONS_BITMAP
= 0x08, /* Wake on every Nth Beacon */
777 WAKE_UP_EVENT_BITS_MASK
= 0x0F
780 struct acx_wake_up_condition
{
781 struct acx_header header
;
783 u8 wake_up_event
; /* Only one bit can be set */
789 struct acx_header header
;
792 * To be set when associated with an AP.
798 enum acx_preamble_type
{
799 ACX_PREAMBLE_LONG
= 0,
800 ACX_PREAMBLE_SHORT
= 1
803 struct acx_preamble
{
804 struct acx_header header
;
807 * When set, the WiLink transmits the frames with a short preamble and
808 * when cleared, the WiLink transmits the frames with a long preamble.
814 enum acx_ctsprotect_type
{
815 CTSPROTECT_DISABLE
= 0,
816 CTSPROTECT_ENABLE
= 1
819 struct acx_ctsprotect
{
820 struct acx_header header
;
825 struct acx_tx_statistics
{
826 u32 internal_desc_overflow
;
829 struct acx_rx_statistics
{
840 struct acx_dma_statistics
{
847 struct acx_isr_statistics
{
848 /* host command complete */
854 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
857 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
860 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
863 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
869 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
872 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
875 /* (INT_STS_ND & INT_TRIG_DMA0) */
878 /* (INT_STS_ND & INT_TRIG_DMA1) */
881 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
882 u32 tx_exch_complete
;
884 /* (INT_STS_ND & INT_TRIG_COMMAND) */
887 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
890 /* (INT_STS_ND & INT_TRIG_PM_802) */
891 u32 hw_pm_mode_changes
;
893 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
894 u32 host_acknowledges
;
896 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
899 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
902 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
906 struct acx_wep_statistics
{
907 /* WEP address keys configured */
910 /* default keys configured */
911 u32 default_key_count
;
915 /* number of times that WEP key not found on lookup */
918 /* number of times that WEP key decryption failed */
921 /* WEP packets decrypted */
924 /* WEP decrypt interrupts */
928 #define ACX_MISSED_BEACONS_SPREAD 10
930 struct acx_pwr_statistics
{
931 /* the amount of enters into power save mode (both PD & ELP) */
934 /* the amount of enters into ELP mode */
937 /* the amount of missing beacon interrupts to the host */
940 /* the amount of wake on host-access times */
943 /* the amount of wake on timer-expire */
944 u32 wake_on_timer_exp
;
946 /* the number of packets that were transmitted with PS bit set */
949 /* the number of packets that were transmitted with PS bit clear */
952 /* the number of received beacons */
955 /* the number of entering into PowerOn (power save off) */
958 /* the number of entries into power save mode */
962 * the number of exits from power save, not including failed PS
968 * the number of times the TSF counter was adjusted because
973 /* Gives statistics about the spread continuous missed beacons.
974 * The 16 LSB are dedicated for the PS mode.
975 * The 16 MSB are dedicated for the PS mode.
976 * cont_miss_bcns_spread[0] - single missed beacon.
977 * cont_miss_bcns_spread[1] - two continuous missed beacons.
978 * cont_miss_bcns_spread[2] - three continuous missed beacons.
980 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
982 u32 cont_miss_bcns_spread
[ACX_MISSED_BEACONS_SPREAD
];
984 /* the number of beacons in awake mode */
985 u32 rcvd_awake_beacons
;
988 struct acx_mic_statistics
{
993 struct acx_aes_statistics
{
998 u32 encrypt_interrupt
;
999 u32 decrypt_interrupt
;
1002 struct acx_event_statistics
{
1009 u32 phy_transmit_error
;
1013 struct acx_ps_statistics
{
1014 u32 pspoll_timeouts
;
1016 u32 upsd_max_sptime
;
1017 u32 upsd_max_apturn
;
1018 u32 pspoll_max_apturn
;
1019 u32 pspoll_utilization
;
1020 u32 upsd_utilization
;
1023 struct acx_rxpipe_statistics
{
1024 u32 rx_prep_beacon_drop
;
1025 u32 descr_host_int_trig_rx_data
;
1026 u32 beacon_buffer_thres_host_int_trig_rx_data
;
1027 u32 missed_beacon_host_int_trig_rx_data
;
1028 u32 tx_xfr_host_int_trig_rx_data
;
1031 struct acx_statistics
{
1032 struct acx_header header
;
1034 struct acx_tx_statistics tx
;
1035 struct acx_rx_statistics rx
;
1036 struct acx_dma_statistics dma
;
1037 struct acx_isr_statistics isr
;
1038 struct acx_wep_statistics wep
;
1039 struct acx_pwr_statistics pwr
;
1040 struct acx_aes_statistics aes
;
1041 struct acx_mic_statistics mic
;
1042 struct acx_event_statistics event
;
1043 struct acx_ps_statistics ps
;
1044 struct acx_rxpipe_statistics rxpipe
;
1047 #define ACX_MAX_RATE_CLASSES 8
1048 #define ACX_RATE_MASK_UNSPECIFIED 0
1049 #define ACX_RATE_RETRY_LIMIT 10
1051 struct acx_rate_class
{
1053 u8 short_retry_limit
;
1054 u8 long_retry_limit
;
1059 struct acx_rate_policy
{
1060 struct acx_header header
;
1063 struct acx_rate_class rate_class
[ACX_MAX_RATE_CLASSES
];
1066 struct wl1251_acx_memory
{
1067 __le16 num_stations
; /* number of STAs to be supported. */
1071 * Nmber of memory buffers for the RX mem pool.
1072 * The actual number may be less if there are
1073 * not enough blocks left for the minimum num
1076 u8 rx_mem_block_num
;
1078 u8 num_tx_queues
; /* From 1 to 16 */
1079 u8 host_if_options
; /* HOST_IF* */
1080 u8 tx_min_mem_block_num
;
1081 u8 num_ssid_profiles
;
1082 __le16 debug_buffer_size
;
1086 #define ACX_RX_DESC_MIN 1
1087 #define ACX_RX_DESC_MAX 127
1088 #define ACX_RX_DESC_DEF 32
1089 struct wl1251_acx_rx_queue_config
{
1097 #define ACX_TX_DESC_MIN 1
1098 #define ACX_TX_DESC_MAX 127
1099 #define ACX_TX_DESC_DEF 16
1100 struct wl1251_acx_tx_queue_config
{
1106 #define MAX_TX_QUEUE_CONFIGS 5
1107 #define MAX_TX_QUEUES 4
1108 struct wl1251_acx_config_memory
{
1109 struct acx_header header
;
1111 struct wl1251_acx_memory mem_config
;
1112 struct wl1251_acx_rx_queue_config rx_queue_config
;
1113 struct wl1251_acx_tx_queue_config tx_queue_config
[MAX_TX_QUEUE_CONFIGS
];
1116 struct wl1251_acx_mem_map
{
1117 struct acx_header header
;
1122 void *wep_defkey_start
;
1123 void *wep_defkey_end
;
1125 void *sta_table_start
;
1126 void *sta_table_end
;
1128 void *packet_template_start
;
1129 void *packet_template_end
;
1131 void *queue_memory_start
;
1132 void *queue_memory_end
;
1134 void *packet_memory_pool_start
;
1135 void *packet_memory_pool_end
;
1137 void *debug_buffer1_start
;
1138 void *debug_buffer1_end
;
1140 void *debug_buffer2_start
;
1141 void *debug_buffer2_end
;
1143 /* Number of blocks FW allocated for TX packets */
1144 u32 num_tx_mem_blocks
;
1146 /* Number of blocks FW allocated for RX packets */
1147 u32 num_rx_mem_blocks
;
1151 struct wl1251_acx_wr_tbtt_and_dtim
{
1153 struct acx_header header
;
1155 /* Time in TUs between two consecutive beacons */
1160 * For BSS: Number of TBTTs in a DTIM period (range: 1-10)
1161 * For IBSS: value shall be set to 1
1167 struct wl1251_acx_ac_cfg
{
1168 struct acx_header header
;
1171 * Access Category - The TX queue's access category
1172 * (refer to AccessCategory_enum)
1177 * The contention window minimum size (in slots) for
1183 * The contention window maximum size (in slots) for
1188 /* The AIF value (in slots) for the access class. */
1193 /* The TX Op Limit (in microseconds) for the access class. */
1198 enum wl1251_acx_channel_type
{
1199 CHANNEL_TYPE_DCF
= 0,
1200 CHANNEL_TYPE_EDCF
= 1,
1201 CHANNEL_TYPE_HCCA
= 2,
1204 enum wl1251_acx_ps_scheme
{
1205 /* regular ps: simple sending of packets */
1206 WL1251_ACX_PS_SCHEME_LEGACY
= 0,
1208 /* sending a packet triggers a unscheduled apsd downstream */
1209 WL1251_ACX_PS_SCHEME_UPSD_TRIGGER
= 1,
1211 /* a pspoll packet will be sent before every data packet */
1212 WL1251_ACX_PS_SCHEME_LEGACY_PSPOLL
= 2,
1214 /* scheduled apsd mode */
1215 WL1251_ACX_PS_SCHEME_SAPSD
= 3,
1218 enum wl1251_acx_ack_policy
{
1219 WL1251_ACX_ACK_POLICY_LEGACY
= 0,
1220 WL1251_ACX_ACK_POLICY_NO_ACK
= 1,
1221 WL1251_ACX_ACK_POLICY_BLOCK
= 2,
1224 struct wl1251_acx_tid_cfg
{
1225 struct acx_header header
;
1227 /* tx queue id number (0-7) */
1230 /* channel access type for the queue, enum wl1251_acx_channel_type */
1233 /* EDCA: ac index (0-3), HCCA: traffic stream id (8-15) */
1236 /* ps scheme of the specified queue, enum wl1251_acx_ps_scheme */
1239 /* the tx queue ack policy, enum wl1251_acx_ack_policy */
1248 /*************************************************************************
1250 Host Interrupt Register (WiLink -> Host)
1252 **************************************************************************/
1254 /* RX packet is ready in Xfer buffer #0 */
1255 #define WL1251_ACX_INTR_RX0_DATA BIT(0)
1257 /* TX result(s) are in the TX complete buffer */
1258 #define WL1251_ACX_INTR_TX_RESULT BIT(1)
1261 #define WL1251_ACX_INTR_TX_XFR BIT(2)
1263 /* RX packet is ready in Xfer buffer #1 */
1264 #define WL1251_ACX_INTR_RX1_DATA BIT(3)
1266 /* Event was entered to Event MBOX #A */
1267 #define WL1251_ACX_INTR_EVENT_A BIT(4)
1269 /* Event was entered to Event MBOX #B */
1270 #define WL1251_ACX_INTR_EVENT_B BIT(5)
1273 #define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6)
1275 /* Trace meassge on MBOX #A */
1276 #define WL1251_ACX_INTR_TRACE_A BIT(7)
1278 /* Trace meassge on MBOX #B */
1279 #define WL1251_ACX_INTR_TRACE_B BIT(8)
1281 /* Command processing completion */
1282 #define WL1251_ACX_INTR_CMD_COMPLETE BIT(9)
1284 /* Init sequence is done */
1285 #define WL1251_ACX_INTR_INIT_COMPLETE BIT(14)
1287 #define WL1251_ACX_INTR_ALL 0xFFFFFFFF
1290 ACX_WAKE_UP_CONDITIONS
= 0x0002,
1291 ACX_MEM_CFG
= 0x0003,
1293 ACX_QUEUE_HEAD
= 0x0005, /* for MASTER mode only */
1294 ACX_AC_CFG
= 0x0007,
1295 ACX_MEM_MAP
= 0x0008,
1297 ACX_RADIO_PARAM
= 0x000B, /* Not used */
1298 ACX_CFG
= 0x000C, /* Not used */
1299 ACX_FW_REV
= 0x000D,
1300 ACX_MEDIUM_USAGE
= 0x000F,
1301 ACX_RX_CFG
= 0x0010,
1302 ACX_TX_QUEUE_CFG
= 0x0011, /* FIXME: only used by wl1251 */
1303 ACX_BSS_IN_PS
= 0x0012, /* for AP only */
1304 ACX_STATISTICS
= 0x0013, /* Debug API */
1305 ACX_FEATURE_CFG
= 0x0015,
1306 ACX_MISC_CFG
= 0x0017, /* Not used */
1307 ACX_TID_CFG
= 0x001A,
1308 ACX_BEACON_FILTER_OPT
= 0x001F,
1309 ACX_LOW_RSSI
= 0x0020,
1310 ACX_NOISE_HIST
= 0x0021,
1311 ACX_HDK_VERSION
= 0x0022, /* ??? */
1312 ACX_PD_THRESHOLD
= 0x0023,
1313 ACX_DATA_PATH_PARAMS
= 0x0024, /* WO */
1314 ACX_DATA_PATH_RESP_PARAMS
= 0x0024, /* RO */
1315 ACX_CCA_THRESHOLD
= 0x0025,
1316 ACX_EVENT_MBOX_MASK
= 0x0026,
1317 #ifdef FW_RUNNING_AS_AP
1318 ACX_DTIM_PERIOD
= 0x0027, /* for AP only */
1320 ACX_WR_TBTT_AND_DTIM
= 0x0027, /* STA only */
1322 ACX_ACI_OPTION_CFG
= 0x0029, /* OBSOLETE (for 1251)*/
1323 ACX_GPIO_CFG
= 0x002A, /* Not used */
1324 ACX_GPIO_SET
= 0x002B, /* Not used */
1325 ACX_PM_CFG
= 0x002C, /* To Be Documented */
1326 ACX_CONN_MONIT_PARAMS
= 0x002D,
1327 ACX_AVERAGE_RSSI
= 0x002E, /* Not used */
1328 ACX_CONS_TX_FAILURE
= 0x002F,
1329 ACX_BCN_DTIM_OPTIONS
= 0x0031,
1330 ACX_SG_ENABLE
= 0x0032,
1331 ACX_SG_CFG
= 0x0033,
1332 ACX_ANTENNA_DIVERSITY_CFG
= 0x0035, /* To Be Documented */
1333 ACX_LOW_SNR
= 0x0037, /* To Be Documented */
1334 ACX_BEACON_FILTER_TABLE
= 0x0038,
1335 ACX_ARP_IP_FILTER
= 0x0039,
1336 ACX_ROAMING_STATISTICS_TBL
= 0x003B,
1337 ACX_RATE_POLICY
= 0x003D,
1338 ACX_CTS_PROTECTION
= 0x003E,
1339 ACX_SLEEP_AUTH
= 0x003F,
1340 ACX_PREAMBLE_TYPE
= 0x0040,
1341 ACX_ERROR_CNT
= 0x0041,
1342 ACX_FW_GEN_FRAME_RATES
= 0x0042,
1343 ACX_IBSS_FILTER
= 0x0044,
1344 ACX_SERVICE_PERIOD_TIMEOUT
= 0x0045,
1345 ACX_TSF_INFO
= 0x0046,
1346 ACX_CONFIG_PS_WMM
= 0x0049,
1347 ACX_ENABLE_RX_DATA_FILTER
= 0x004A,
1348 ACX_SET_RX_DATA_FILTER
= 0x004B,
1349 ACX_GET_DATA_FILTER_STATISTICS
= 0x004C,
1350 ACX_POWER_LEVEL_TABLE
= 0x004D,
1351 ACX_BET_ENABLE
= 0x0050,
1352 DOT11_STATION_ID
= 0x1001,
1353 DOT11_RX_MSDU_LIFE_TIME
= 0x1004,
1354 DOT11_CUR_TX_PWR
= 0x100D,
1355 DOT11_DEFAULT_KEY
= 0x1010,
1356 DOT11_RX_DOT11_MODE
= 0x1012,
1357 DOT11_RTS_THRESHOLD
= 0x1013,
1358 DOT11_GROUP_ADDRESS_TBL
= 0x1014,
1360 MAX_DOT11_IE
= DOT11_GROUP_ADDRESS_TBL
,
1366 int wl1251_acx_frame_rates(struct wl1251
*wl
, u8 ctrl_rate
, u8 ctrl_mod
,
1367 u8 mgt_rate
, u8 mgt_mod
);
1368 int wl1251_acx_station_id(struct wl1251
*wl
);
1369 int wl1251_acx_default_key(struct wl1251
*wl
, u8 key_id
);
1370 int wl1251_acx_wake_up_conditions(struct wl1251
*wl
, u8 wake_up_event
,
1371 u8 listen_interval
);
1372 int wl1251_acx_sleep_auth(struct wl1251
*wl
, u8 sleep_auth
);
1373 int wl1251_acx_fw_version(struct wl1251
*wl
, char *buf
, size_t len
);
1374 int wl1251_acx_tx_power(struct wl1251
*wl
, int power
);
1375 int wl1251_acx_feature_cfg(struct wl1251
*wl
);
1376 int wl1251_acx_mem_map(struct wl1251
*wl
,
1377 struct acx_header
*mem_map
, size_t len
);
1378 int wl1251_acx_data_path_params(struct wl1251
*wl
,
1379 struct acx_data_path_params_resp
*data_path
);
1380 int wl1251_acx_rx_msdu_life_time(struct wl1251
*wl
, u32 life_time
);
1381 int wl1251_acx_rx_config(struct wl1251
*wl
, u32 config
, u32 filter
);
1382 int wl1251_acx_pd_threshold(struct wl1251
*wl
);
1383 int wl1251_acx_slot(struct wl1251
*wl
, enum acx_slot_type slot_time
);
1384 int wl1251_acx_group_address_tbl(struct wl1251
*wl
);
1385 int wl1251_acx_service_period_timeout(struct wl1251
*wl
);
1386 int wl1251_acx_rts_threshold(struct wl1251
*wl
, u16 rts_threshold
);
1387 int wl1251_acx_beacon_filter_opt(struct wl1251
*wl
, bool enable_filter
);
1388 int wl1251_acx_beacon_filter_table(struct wl1251
*wl
);
1389 int wl1251_acx_conn_monit_params(struct wl1251
*wl
);
1390 int wl1251_acx_sg_enable(struct wl1251
*wl
);
1391 int wl1251_acx_sg_cfg(struct wl1251
*wl
);
1392 int wl1251_acx_cca_threshold(struct wl1251
*wl
);
1393 int wl1251_acx_bcn_dtim_options(struct wl1251
*wl
);
1394 int wl1251_acx_aid(struct wl1251
*wl
, u16 aid
);
1395 int wl1251_acx_event_mbox_mask(struct wl1251
*wl
, u32 event_mask
);
1396 int wl1251_acx_set_preamble(struct wl1251
*wl
, enum acx_preamble_type preamble
);
1397 int wl1251_acx_cts_protect(struct wl1251
*wl
,
1398 enum acx_ctsprotect_type ctsprotect
);
1399 int wl1251_acx_statistics(struct wl1251
*wl
, struct acx_statistics
*stats
);
1400 int wl1251_acx_tsf_info(struct wl1251
*wl
, u64
*mactime
);
1401 int wl1251_acx_rate_policies(struct wl1251
*wl
);
1402 int wl1251_acx_mem_cfg(struct wl1251
*wl
);
1403 int wl1251_acx_wr_tbtt_and_dtim(struct wl1251
*wl
, u16 tbtt
, u8 dtim
);
1404 int wl1251_acx_ac_cfg(struct wl1251
*wl
, u8 ac
, u8 cw_min
, u16 cw_max
,
1406 int wl1251_acx_tid_cfg(struct wl1251
*wl
, u8 queue
,
1407 enum wl1251_acx_channel_type type
,
1408 u8 tsid
, enum wl1251_acx_ps_scheme ps_scheme
,
1409 enum wl1251_acx_ack_policy ack_policy
);
1411 #endif /* __WL1251_ACX_H__ */