drivers/net/wireless/wl12xx/acx.h

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
   5  * Copyright (C) 2008-2010 Nokia Corporation
   6  *
   7  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #ifndef __ACX_H__
  26 #define __ACX_H__
  27
  28 #include "wl12xx.h"
  29 #include "cmd.h"
  30
  31 /*************************************************************************
  32
  33     Host Interrupt Register (WiLink -> Host)
  34
  35 **************************************************************************/
  36 /* HW Initiated interrupt Watchdog timer expiration */
  37 #define WL1271_ACX_INTR_WATCHDOG           BIT(0)
  38 /* Init sequence is done (masked interrupt, detection through polling only ) */
  39 #define WL1271_ACX_INTR_INIT_COMPLETE      BIT(1)
  40 /* Event was entered to Event MBOX #A*/
  41 #define WL1271_ACX_INTR_EVENT_A            BIT(2)
  42 /* Event was entered to Event MBOX #B*/
  43 #define WL1271_ACX_INTR_EVENT_B            BIT(3)
  44 /* Command processing completion*/
  45 #define WL1271_ACX_INTR_CMD_COMPLETE       BIT(4)
  46 /* Signaling the host on HW wakeup */
  47 #define WL1271_ACX_INTR_HW_AVAILABLE       BIT(5)
  48 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
  49 #define WL1271_ACX_INTR_DATA               BIT(6)
  50 /* Trace meassge on MBOX #A */
  51 #define WL1271_ACX_INTR_TRACE_A            BIT(7)
  52 /* Trace meassge on MBOX #B */
  53 #define WL1271_ACX_INTR_TRACE_B            BIT(8)
  54
  55 #define WL1271_ACX_INTR_ALL                0xFFFFFFFF
  56 #define WL1271_ACX_ALL_EVENTS_VECTOR       (WL1271_ACX_INTR_WATCHDOG      | \
  57                                             WL1271_ACX_INTR_INIT_COMPLETE | \
  58                                             WL1271_ACX_INTR_EVENT_A       | \
  59                                             WL1271_ACX_INTR_EVENT_B       | \
  60                                             WL1271_ACX_INTR_CMD_COMPLETE  | \
  61                                             WL1271_ACX_INTR_HW_AVAILABLE  | \
  62                                             WL1271_ACX_INTR_DATA)
  63
  64 #define WL1271_INTR_MASK                   (WL1271_ACX_INTR_WATCHDOG     | \
  65                                             WL1271_ACX_INTR_EVENT_A      | \
  66                                             WL1271_ACX_INTR_EVENT_B      | \
  67                                             WL1271_ACX_INTR_HW_AVAILABLE | \
  68                                             WL1271_ACX_INTR_DATA)
  69
  70 /* Target's information element */
  71 struct acx_header {
  72         struct wl1271_cmd_header cmd;
  73
  74         /* acx (or information element) header */
  75         __le16 id;
  76
  77         /* payload length (not including headers */
  78         __le16 len;
  79 } __packed;
  80
  81 struct acx_error_counter {
  82         struct acx_header header;
  83
  84         /* The number of PLCP errors since the last time this */
  85         /* information element was interrogated. This field is */
  86         /* automatically cleared when it is interrogated.*/
  87         __le32 PLCP_error;
  88
  89         /* The number of FCS errors since the last time this */
  90         /* information element was interrogated. This field is */
  91         /* automatically cleared when it is interrogated.*/
  92         __le32 FCS_error;
  93
  94         /* The number of MPDUs without PLCP header errors received*/
  95         /* since the last time this information element was interrogated. */
  96         /* This field is automatically cleared when it is interrogated.*/
  97         __le32 valid_frame;
  98
  99         /* the number of missed sequence numbers in the squentially */
 100         /* values of frames seq numbers */
 101         __le32 seq_num_miss;
 102 } __packed;
 103
 104 enum wl1271_psm_mode {
 105         /* Active mode */
 106         WL1271_PSM_CAM = 0,
 107
 108         /* Power save mode */
 109         WL1271_PSM_PS = 1,
 110
 111         /* Extreme low power */
 112         WL1271_PSM_ELP = 2,
 113 };
 114
 115 struct acx_sleep_auth {
 116         struct acx_header header;
 117
 118         /* The sleep level authorization of the device. */
 119         /* 0 - Always active*/
 120         /* 1 - Power down mode: light / fast sleep*/
 121         /* 2 - ELP mode: Deep / Max sleep*/
 122         u8  sleep_auth;
 123         u8  padding[3];
 124 } __packed;
 125
 126 enum {
 127         HOSTIF_PCI_MASTER_HOST_INDIRECT,
 128         HOSTIF_PCI_MASTER_HOST_DIRECT,
 129         HOSTIF_SLAVE,
 130         HOSTIF_PKT_RING,
 131         HOSTIF_DONTCARE = 0xFF
 132 };
 133
 134 #define DEFAULT_UCAST_PRIORITY          0
 135 #define DEFAULT_RX_Q_PRIORITY           0
 136 #define DEFAULT_NUM_STATIONS            1
 137 #define DEFAULT_RXQ_PRIORITY            0 /* low 0 .. 15 high  */
 138 #define DEFAULT_RXQ_TYPE                0x07    /* All frames, Data/Ctrl/Mgmt */
 139 #define TRACE_BUFFER_MAX_SIZE           256
 140
 141 #define  DP_RX_PACKET_RING_CHUNK_SIZE 1600
 142 #define  DP_TX_PACKET_RING_CHUNK_SIZE 1600
 143 #define  DP_RX_PACKET_RING_CHUNK_NUM 2
 144 #define  DP_TX_PACKET_RING_CHUNK_NUM 2
 145 #define  DP_TX_COMPLETE_TIME_OUT 20
 146
 147 #define TX_MSDU_LIFETIME_MIN       0
 148 #define TX_MSDU_LIFETIME_MAX       3000
 149 #define TX_MSDU_LIFETIME_DEF       512
 150 #define RX_MSDU_LIFETIME_MIN       0
 151 #define RX_MSDU_LIFETIME_MAX       0xFFFFFFFF
 152 #define RX_MSDU_LIFETIME_DEF       512000
 153
 154 struct acx_rx_msdu_lifetime {
 155         struct acx_header header;
 156
 157         /*
 158          * The maximum amount of time, in TU, before the
 159          * firmware discards the MSDU.
 160          */
 161         __le32 lifetime;
 162 } __packed;
 163
 164 /*
 165  * RX Config Options Table
 166  * Bit          Definition
 167  * ===          ==========
 168  * 31:14                Reserved
 169  * 13           Copy RX Status - when set, write three receive status words
 170  *              to top of rx'd MPDUs.
 171  *              When cleared, do not write three status words (added rev 1.5)
 172  * 12           Reserved
 173  * 11           RX Complete upon FCS error - when set, give rx complete
 174  *              interrupt for FCS errors, after the rx filtering, e.g. unicast
 175  *              frames not to us with FCS error will not generate an interrupt.
 176  * 10           SSID Filter Enable - When set, the WiLink discards all beacon,
 177  *              probe request, and probe response frames with an SSID that does
 178  *              not match the SSID specified by the host in the START/JOIN
 179  *              command.
 180  *              When clear, the WiLink receives frames with any SSID.
 181  * 9            Broadcast Filter Enable - When set, the WiLink discards all
 182  *              broadcast frames. When clear, the WiLink receives all received
 183  *              broadcast frames.
 184  * 8:6          Reserved
 185  * 5            BSSID Filter Enable - When set, the WiLink discards any frames
 186  *              with a BSSID that does not match the BSSID specified by the
 187  *              host.
 188  *              When clear, the WiLink receives frames from any BSSID.
 189  * 4            MAC Addr Filter - When set, the WiLink discards any frames
 190  *              with a destination address that does not match the MAC address
 191  *              of the adaptor.
 192  *              When clear, the WiLink receives frames destined to any MAC
 193  *              address.
 194  * 3            Promiscuous - When set, the WiLink receives all valid frames
 195  *              (i.e., all frames that pass the FCS check).
 196  *              When clear, only frames that pass the other filters specified
 197  *              are received.
 198  * 2            FCS - When set, the WiLink includes the FCS with the received
 199  *              frame.
 200  *              When cleared, the FCS is discarded.
 201  * 1            PLCP header - When set, write all data from baseband to frame
 202  *              buffer including PHY header.
 203  * 0            Reserved - Always equal to 0.
 204  *
 205  * RX Filter Options Table
 206  * Bit          Definition
 207  * ===          ==========
 208  * 31:12                Reserved - Always equal to 0.
 209  * 11           Association - When set, the WiLink receives all association
 210  *              related frames (association request/response, reassocation
 211  *              request/response, and disassociation). When clear, these frames
 212  *              are discarded.
 213  * 10           Auth/De auth - When set, the WiLink receives all authentication
 214  *              and de-authentication frames. When clear, these frames are
 215  *              discarded.
 216  * 9            Beacon - When set, the WiLink receives all beacon frames.
 217  *              When clear, these frames are discarded.
 218  * 8            Contention Free - When set, the WiLink receives all contention
 219  *              free frames.
 220  *              When clear, these frames are discarded.
 221  * 7            Control - When set, the WiLink receives all control frames.
 222  *              When clear, these frames are discarded.
 223  * 6            Data - When set, the WiLink receives all data frames.
 224  *              When clear, these frames are discarded.
 225  * 5            FCS Error - When set, the WiLink receives frames that have FCS
 226  *              errors.
 227  *              When clear, these frames are discarded.
 228  * 4            Management - When set, the WiLink receives all management
 229  *              frames.
 230  *              When clear, these frames are discarded.
 231  * 3            Probe Request - When set, the WiLink receives all probe request
 232  *              frames.
 233  *              When clear, these frames are discarded.
 234  * 2            Probe Response - When set, the WiLink receives all probe
 235  *              response frames.
 236  *              When clear, these frames are discarded.
 237  * 1            RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
 238  *              frames.
 239  *              When clear, these frames are discarded.
 240  * 0            Rsvd Type/Sub Type - When set, the WiLink receives all frames
 241  *              that have reserved frame types and sub types as defined by the
 242  *              802.11 specification.
 243  *              When clear, these frames are discarded.
 244  */
 245 struct acx_rx_config {
 246         struct acx_header header;
 247
 248         __le32 config_options;
 249         __le32 filter_options;
 250 } __packed;
 251
 252 struct acx_packet_detection {
 253         struct acx_header header;
 254
 255         __le32 threshold;
 256 } __packed;
 257
 258
 259 enum acx_slot_type {
 260         SLOT_TIME_LONG = 0,
 261         SLOT_TIME_SHORT = 1,
 262         DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
 263         MAX_SLOT_TIMES = 0xFF
 264 };
 265
 266 #define STATION_WONE_INDEX 0
 267
 268 struct acx_slot {
 269         struct acx_header header;
 270
 271         u8 wone_index; /* Reserved */
 272         u8 slot_time;
 273         u8 reserved[6];
 274 } __packed;
 275
 276
 277 #define ACX_MC_ADDRESS_GROUP_MAX        (8)
 278 #define ADDRESS_GROUP_MAX_LEN           (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
 279
 280 struct acx_dot11_grp_addr_tbl {
 281         struct acx_header header;
 282
 283         u8 enabled;
 284         u8 num_groups;
 285         u8 pad[2];
 286         u8 mac_table[ADDRESS_GROUP_MAX_LEN];
 287 } __packed;
 288
 289 struct acx_rx_timeout {
 290         struct acx_header header;
 291
 292         __le16 ps_poll_timeout;
 293         __le16 upsd_timeout;
 294 } __packed;
 295
 296 struct acx_rts_threshold {
 297         struct acx_header header;
 298
 299         __le16 threshold;
 300         u8 pad[2];
 301 } __packed;
 302
 303 struct acx_beacon_filter_option {
 304         struct acx_header header;
 305
 306         u8 enable;
 307
 308         /*
 309          * The number of beacons without the unicast TIM
 310          * bit set that the firmware buffers before
 311          * signaling the host about ready frames.
 312          * When set to 0 and the filter is enabled, beacons
 313          * without the unicast TIM bit set are dropped.
 314          */
 315         u8 max_num_beacons;
 316         u8 pad[2];
 317 } __packed;
 318
 319 /*
 320  * ACXBeaconFilterEntry (not 221)
 321  * Byte Offset     Size (Bytes)    Definition
 322  * ===========     ============    ==========
 323  * 0               1               IE identifier
 324  * 1               1               Treatment bit mask
 325  *
 326  * ACXBeaconFilterEntry (221)
 327  * Byte Offset     Size (Bytes)    Definition
 328  * ===========     ============    ==========
 329  * 0               1               IE identifier
 330  * 1               1               Treatment bit mask
 331  * 2               3               OUI
 332  * 5               1               Type
 333  * 6               2               Version
 334  *
 335  *
 336  * Treatment bit mask - The information element handling:
 337  * bit 0 - The information element is compared and transferred
 338  * in case of change.
 339  * bit 1 - The information element is transferred to the host
 340  * with each appearance or disappearance.
 341  * Note that both bits can be set at the same time.
 342  */
 343 #define BEACON_FILTER_TABLE_MAX_IE_NUM                 (32)
 344 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
 345 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE              (2)
 346 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
 347 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
 348                             BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
 349                            (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
 350                             BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
 351
 352 struct acx_beacon_filter_ie_table {
 353         struct acx_header header;
 354
 355         u8 num_ie;
 356         u8 pad[3];
 357         u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
 358 } __packed;
 359
 360 struct acx_conn_monit_params {
 361        struct acx_header header;
 362
 363        __le32 synch_fail_thold; /* number of beacons missed */
 364        __le32 bss_lose_timeout; /* number of TU's from synch fail */
 365 } __packed;
 366
 367 struct acx_bt_wlan_coex {
 368         struct acx_header header;
 369
 370         u8 enable;
 371         u8 pad[3];
 372 } __packed;
 373
 374 struct acx_bt_wlan_coex_param {
 375         struct acx_header header;
 376
 377         __le32 params[CONF_SG_PARAMS_MAX];
 378         u8 param_idx;
 379         u8 padding[3];
 380 } __packed;
 381
 382 struct acx_dco_itrim_params {
 383         struct acx_header header;
 384
 385         u8 enable;
 386         u8 padding[3];
 387         __le32 timeout;
 388 } __packed;
 389
 390 struct acx_energy_detection {
 391         struct acx_header header;
 392
 393         /* The RX Clear Channel Assessment threshold in the PHY */
 394         __le16 rx_cca_threshold;
 395         u8 tx_energy_detection;
 396         u8 pad;
 397 } __packed;
 398
 399 struct acx_beacon_broadcast {
 400         struct acx_header header;
 401
 402         __le16 beacon_rx_timeout;
 403         __le16 broadcast_timeout;
 404
 405         /* Enables receiving of broadcast packets in PS mode */
 406         u8 rx_broadcast_in_ps;
 407
 408         /* Consecutive PS Poll failures before updating the host */
 409         u8 ps_poll_threshold;
 410         u8 pad[2];
 411 } __packed;
 412
 413 struct acx_event_mask {
 414         struct acx_header header;
 415
 416         __le32 event_mask;
 417         __le32 high_event_mask; /* Unused */
 418 } __packed;
 419
 420 #define CFG_RX_FCS              BIT(2)
 421 #define CFG_RX_ALL_GOOD         BIT(3)
 422 #define CFG_UNI_FILTER_EN       BIT(4)
 423 #define CFG_BSSID_FILTER_EN     BIT(5)
 424 #define CFG_MC_FILTER_EN        BIT(6)
 425 #define CFG_MC_ADDR0_EN         BIT(7)
 426 #define CFG_MC_ADDR1_EN         BIT(8)
 427 #define CFG_BC_REJECT_EN        BIT(9)
 428 #define CFG_SSID_FILTER_EN      BIT(10)
 429 #define CFG_RX_INT_FCS_ERROR    BIT(11)
 430 #define CFG_RX_INT_ENCRYPTED    BIT(12)
 431 #define CFG_RX_WR_RX_STATUS     BIT(13)
 432 #define CFG_RX_FILTER_NULTI     BIT(14)
 433 #define CFG_RX_RESERVE          BIT(15)
 434 #define CFG_RX_TIMESTAMP_TSF    BIT(16)
 435
 436 #define CFG_RX_RSV_EN           BIT(0)
 437 #define CFG_RX_RCTS_ACK         BIT(1)
 438 #define CFG_RX_PRSP_EN          BIT(2)
 439 #define CFG_RX_PREQ_EN          BIT(3)
 440 #define CFG_RX_MGMT_EN          BIT(4)
 441 #define CFG_RX_FCS_ERROR        BIT(5)
 442 #define CFG_RX_DATA_EN          BIT(6)
 443 #define CFG_RX_CTL_EN           BIT(7)
 444 #define CFG_RX_CF_EN            BIT(8)
 445 #define CFG_RX_BCN_EN           BIT(9)
 446 #define CFG_RX_AUTH_EN          BIT(10)
 447 #define CFG_RX_ASSOC_EN         BIT(11)
 448
 449 #define SCAN_PASSIVE            BIT(0)
 450 #define SCAN_5GHZ_BAND          BIT(1)
 451 #define SCAN_TRIGGERED          BIT(2)
 452 #define SCAN_PRIORITY_HIGH      BIT(3)
 453
 454 /* When set, disable HW encryption */
 455 #define DF_ENCRYPTION_DISABLE      0x01
 456 #define DF_SNIFF_MODE_ENABLE       0x80
 457
 458 struct acx_feature_config {
 459         struct acx_header header;
 460
 461         __le32 options;
 462         __le32 data_flow_options;
 463 } __packed;
 464
 465 struct acx_current_tx_power {
 466         struct acx_header header;
 467
 468         u8  current_tx_power;
 469         u8  padding[3];
 470 } __packed;
 471
 472 struct acx_wake_up_condition {
 473         struct acx_header header;
 474
 475         u8 wake_up_event; /* Only one bit can be set */
 476         u8 listen_interval;
 477         u8 pad[2];
 478 } __packed;
 479
 480 struct acx_aid {
 481         struct acx_header header;
 482
 483         /*
 484          * To be set when associated with an AP.
 485          */
 486         __le16 aid;
 487         u8 pad[2];
 488 } __packed;
 489
 490 enum acx_preamble_type {
 491         ACX_PREAMBLE_LONG = 0,
 492         ACX_PREAMBLE_SHORT = 1
 493 };
 494
 495 struct acx_preamble {
 496         struct acx_header header;
 497
 498         /*
 499          * When set, the WiLink transmits the frames with a short preamble and
 500          * when cleared, the WiLink transmits the frames with a long preamble.
 501          */
 502         u8 preamble;
 503         u8 padding[3];
 504 } __packed;
 505
 506 enum acx_ctsprotect_type {
 507         CTSPROTECT_DISABLE = 0,
 508         CTSPROTECT_ENABLE = 1
 509 };
 510
 511 struct acx_ctsprotect {
 512         struct acx_header header;
 513         u8 ctsprotect;
 514         u8 padding[3];
 515 } __packed;
 516
 517 struct acx_tx_statistics {
 518         __le32 internal_desc_overflow;
 519 }  __packed;
 520
 521 struct acx_rx_statistics {
 522         __le32 out_of_mem;
 523         __le32 hdr_overflow;
 524         __le32 hw_stuck;
 525         __le32 dropped;
 526         __le32 fcs_err;
 527         __le32 xfr_hint_trig;
 528         __le32 path_reset;
 529         __le32 reset_counter;
 530 } __packed;
 531
 532 struct acx_dma_statistics {
 533         __le32 rx_requested;
 534         __le32 rx_errors;
 535         __le32 tx_requested;
 536         __le32 tx_errors;
 537 }  __packed;
 538
 539 struct acx_isr_statistics {
 540         /* host command complete */
 541         __le32 cmd_cmplt;
 542
 543         /* fiqisr() */
 544         __le32 fiqs;
 545
 546         /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
 547         __le32 rx_headers;
 548
 549         /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
 550         __le32 rx_completes;
 551
 552         /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
 553         __le32 rx_mem_overflow;
 554
 555         /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
 556         __le32 rx_rdys;
 557
 558         /* irqisr() */
 559         __le32 irqs;
 560
 561         /* (INT_STS_ND & INT_TRIG_TX_PROC) */
 562         __le32 tx_procs;
 563
 564         /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
 565         __le32 decrypt_done;
 566
 567         /* (INT_STS_ND & INT_TRIG_DMA0) */
 568         __le32 dma0_done;
 569
 570         /* (INT_STS_ND & INT_TRIG_DMA1) */
 571         __le32 dma1_done;
 572
 573         /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
 574         __le32 tx_exch_complete;
 575
 576         /* (INT_STS_ND & INT_TRIG_COMMAND) */
 577         __le32 commands;
 578
 579         /* (INT_STS_ND & INT_TRIG_RX_PROC) */
 580         __le32 rx_procs;
 581
 582         /* (INT_STS_ND & INT_TRIG_PM_802) */
 583         __le32 hw_pm_mode_changes;
 584
 585         /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
 586         __le32 host_acknowledges;
 587
 588         /* (INT_STS_ND & INT_TRIG_PM_PCI) */
 589         __le32 pci_pm;
 590
 591         /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
 592         __le32 wakeups;
 593
 594         /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
 595         __le32 low_rssi;
 596 } __packed;
 597
 598 struct acx_wep_statistics {
 599         /* WEP address keys configured */
 600         __le32 addr_key_count;
 601
 602         /* default keys configured */
 603         __le32 default_key_count;
 604
 605         __le32 reserved;
 606
 607         /* number of times that WEP key not found on lookup */
 608         __le32 key_not_found;
 609
 610         /* number of times that WEP key decryption failed */
 611         __le32 decrypt_fail;
 612
 613         /* WEP packets decrypted */
 614         __le32 packets;
 615
 616         /* WEP decrypt interrupts */
 617         __le32 interrupt;
 618 } __packed;
 619
 620 #define ACX_MISSED_BEACONS_SPREAD 10
 621
 622 struct acx_pwr_statistics {
 623         /* the amount of enters into power save mode (both PD & ELP) */
 624         __le32 ps_enter;
 625
 626         /* the amount of enters into ELP mode */
 627         __le32 elp_enter;
 628
 629         /* the amount of missing beacon interrupts to the host */
 630         __le32 missing_bcns;
 631
 632         /* the amount of wake on host-access times */
 633         __le32 wake_on_host;
 634
 635         /* the amount of wake on timer-expire */
 636         __le32 wake_on_timer_exp;
 637
 638         /* the number of packets that were transmitted with PS bit set */
 639         __le32 tx_with_ps;
 640
 641         /* the number of packets that were transmitted with PS bit clear */
 642         __le32 tx_without_ps;
 643
 644         /* the number of received beacons */
 645         __le32 rcvd_beacons;
 646
 647         /* the number of entering into PowerOn (power save off) */
 648         __le32 power_save_off;
 649
 650         /* the number of entries into power save mode */
 651         __le16 enable_ps;
 652
 653         /*
 654          * the number of exits from power save, not including failed PS
 655          * transitions
 656          */
 657         __le16 disable_ps;
 658
 659         /*
 660          * the number of times the TSF counter was adjusted because
 661          * of drift
 662          */
 663         __le32 fix_tsf_ps;
 664
 665         /* Gives statistics about the spread continuous missed beacons.
 666          * The 16 LSB are dedicated for the PS mode.
 667          * The 16 MSB are dedicated for the PS mode.
 668          * cont_miss_bcns_spread[0] - single missed beacon.
 669          * cont_miss_bcns_spread[1] - two continuous missed beacons.
 670          * cont_miss_bcns_spread[2] - three continuous missed beacons.
 671          * ...
 672          * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
 673         */
 674         __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
 675
 676         /* the number of beacons in awake mode */
 677         __le32 rcvd_awake_beacons;
 678 } __packed;
 679
 680 struct acx_mic_statistics {
 681         __le32 rx_pkts;
 682         __le32 calc_failure;
 683 } __packed;
 684
 685 struct acx_aes_statistics {
 686         __le32 encrypt_fail;
 687         __le32 decrypt_fail;
 688         __le32 encrypt_packets;
 689         __le32 decrypt_packets;
 690         __le32 encrypt_interrupt;
 691         __le32 decrypt_interrupt;
 692 } __packed;
 693
 694 struct acx_event_statistics {
 695         __le32 heart_beat;
 696         __le32 calibration;
 697         __le32 rx_mismatch;
 698         __le32 rx_mem_empty;
 699         __le32 rx_pool;
 700         __le32 oom_late;
 701         __le32 phy_transmit_error;
 702         __le32 tx_stuck;
 703 } __packed;
 704
 705 struct acx_ps_statistics {
 706         __le32 pspoll_timeouts;
 707         __le32 upsd_timeouts;
 708         __le32 upsd_max_sptime;
 709         __le32 upsd_max_apturn;
 710         __le32 pspoll_max_apturn;
 711         __le32 pspoll_utilization;
 712         __le32 upsd_utilization;
 713 } __packed;
 714
 715 struct acx_rxpipe_statistics {
 716         __le32 rx_prep_beacon_drop;
 717         __le32 descr_host_int_trig_rx_data;
 718         __le32 beacon_buffer_thres_host_int_trig_rx_data;
 719         __le32 missed_beacon_host_int_trig_rx_data;
 720         __le32 tx_xfr_host_int_trig_rx_data;
 721 } __packed;
 722
 723 struct acx_statistics {
 724         struct acx_header header;
 725
 726         struct acx_tx_statistics tx;
 727         struct acx_rx_statistics rx;
 728         struct acx_dma_statistics dma;
 729         struct acx_isr_statistics isr;
 730         struct acx_wep_statistics wep;
 731         struct acx_pwr_statistics pwr;
 732         struct acx_aes_statistics aes;
 733         struct acx_mic_statistics mic;
 734         struct acx_event_statistics event;
 735         struct acx_ps_statistics ps;
 736         struct acx_rxpipe_statistics rxpipe;
 737 } __packed;
 738
 739 struct acx_rate_class {
 740         __le32 enabled_rates;
 741         u8 short_retry_limit;
 742         u8 long_retry_limit;
 743         u8 aflags;
 744         u8 reserved;
 745 };
 746
 747 #define ACX_TX_BASIC_RATE      0
 748 #define ACX_TX_AP_FULL_RATE    1
 749 #define ACX_TX_RATE_POLICY_CNT 2
 750 struct acx_rate_policy {
 751         struct acx_header header;
 752
 753         __le32 rate_class_cnt;
 754         struct acx_rate_class rate_class[CONF_TX_MAX_RATE_CLASSES];
 755 } __packed;
 756
 757 struct acx_ac_cfg {
 758         struct acx_header header;
 759         u8 ac;
 760         u8 cw_min;
 761         __le16 cw_max;
 762         u8 aifsn;
 763         u8 reserved;
 764         __le16 tx_op_limit;
 765 } __packed;
 766
 767 struct acx_tid_config {
 768         struct acx_header header;
 769         u8 queue_id;
 770         u8 channel_type;
 771         u8 tsid;
 772         u8 ps_scheme;
 773         u8 ack_policy;
 774         u8 padding[3];
 775         __le32 apsd_conf[2];
 776 } __packed;
 777
 778 struct acx_frag_threshold {
 779         struct acx_header header;
 780         __le16 frag_threshold;
 781         u8 padding[2];
 782 } __packed;
 783
 784 struct acx_tx_config_options {
 785         struct acx_header header;
 786         __le16 tx_compl_timeout;     /* msec */
 787         __le16 tx_compl_threshold;   /* number of packets */
 788 } __packed;
 789
 790 #define ACX_RX_MEM_BLOCKS     70
 791 #define ACX_TX_MIN_MEM_BLOCKS 40
 792 #define ACX_TX_DESCRIPTORS    32
 793 #define ACX_NUM_SSID_PROFILES 1
 794
 795 struct wl1271_acx_config_memory {
 796         struct acx_header header;
 797
 798         u8 rx_mem_block_num;
 799         u8 tx_min_mem_block_num;
 800         u8 num_stations;
 801         u8 num_ssid_profiles;
 802         __le32 total_tx_descriptors;
 803 } __packed;
 804
 805 struct wl1271_acx_mem_map {
 806         struct acx_header header;
 807
 808         __le32 code_start;
 809         __le32 code_end;
 810
 811         __le32 wep_defkey_start;
 812         __le32 wep_defkey_end;
 813
 814         __le32 sta_table_start;
 815         __le32 sta_table_end;
 816
 817         __le32 packet_template_start;
 818         __le32 packet_template_end;
 819
 820         /* Address of the TX result interface (control block) */
 821         __le32 tx_result;
 822         __le32 tx_result_queue_start;
 823
 824         __le32 queue_memory_start;
 825         __le32 queue_memory_end;
 826
 827         __le32 packet_memory_pool_start;
 828         __le32 packet_memory_pool_end;
 829
 830         __le32 debug_buffer1_start;
 831         __le32 debug_buffer1_end;
 832
 833         __le32 debug_buffer2_start;
 834         __le32 debug_buffer2_end;
 835
 836         /* Number of blocks FW allocated for TX packets */
 837         __le32 num_tx_mem_blocks;
 838
 839         /* Number of blocks FW allocated for RX packets */
 840         __le32 num_rx_mem_blocks;
 841
 842         /* the following 4 fields are valid in SLAVE mode only */
 843         u8 *tx_cbuf;
 844         u8 *rx_cbuf;
 845         __le32 rx_ctrl;
 846         __le32 tx_ctrl;
 847 } __packed;
 848
 849 struct wl1271_acx_rx_config_opt {
 850         struct acx_header header;
 851
 852         __le16 mblk_threshold;
 853         __le16 threshold;
 854         __le16 timeout;
 855         u8 queue_type;
 856         u8 reserved;
 857 } __packed;
 858
 859
 860 struct wl1271_acx_bet_enable {
 861         struct acx_header header;
 862
 863         u8 enable;
 864         u8 max_consecutive;
 865         u8 padding[2];
 866 } __packed;
 867
 868 #define ACX_IPV4_VERSION 4
 869 #define ACX_IPV6_VERSION 6
 870 #define ACX_IPV4_ADDR_SIZE 4
 871
 872 /* bitmap of enabled arp_filter features */
 873 #define ACX_ARP_FILTER_ARP_FILTERING    BIT(0)
 874 #define ACX_ARP_FILTER_AUTO_ARP         BIT(1)
 875
 876 struct wl1271_acx_arp_filter {
 877         struct acx_header header;
 878         u8 version;         /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
 879         u8 enable;          /* bitmap of enabled ARP filtering features */
 880         u8 padding[2];
 881         u8 address[16];     /* The configured device IP address - all ARP
 882                                requests directed to this IP address will pass
 883                                through. For IPv4, the first four bytes are
 884                                used. */
 885 } __packed;
 886
 887 struct wl1271_acx_pm_config {
 888         struct acx_header header;
 889
 890         __le32 host_clk_settling_time;
 891         u8 host_fast_wakeup_support;
 892         u8 padding[3];
 893 } __packed;
 894
 895 struct wl1271_acx_keep_alive_mode {
 896         struct acx_header header;
 897
 898         u8 enabled;
 899         u8 padding[3];
 900 } __packed;
 901
 902 enum {
 903         ACX_KEEP_ALIVE_NO_TX = 0,
 904         ACX_KEEP_ALIVE_PERIOD_ONLY
 905 };
 906
 907 enum {
 908         ACX_KEEP_ALIVE_TPL_INVALID = 0,
 909         ACX_KEEP_ALIVE_TPL_VALID
 910 };
 911
 912 struct wl1271_acx_keep_alive_config {
 913         struct acx_header header;
 914
 915         __le32 period;
 916         u8 index;
 917         u8 tpl_validation;
 918         u8 trigger;
 919         u8 padding;
 920 } __packed;
 921
 922 enum {
 923         WL1271_ACX_TRIG_TYPE_LEVEL = 0,
 924         WL1271_ACX_TRIG_TYPE_EDGE,
 925 };
 926
 927 enum {
 928         WL1271_ACX_TRIG_DIR_LOW = 0,
 929         WL1271_ACX_TRIG_DIR_HIGH,
 930         WL1271_ACX_TRIG_DIR_BIDIR,
 931 };
 932
 933 enum {
 934         WL1271_ACX_TRIG_ENABLE = 1,
 935         WL1271_ACX_TRIG_DISABLE,
 936 };
 937
 938 enum {
 939         WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
 940         WL1271_ACX_TRIG_METRIC_RSSI_DATA,
 941         WL1271_ACX_TRIG_METRIC_SNR_BEACON,
 942         WL1271_ACX_TRIG_METRIC_SNR_DATA,
 943 };
 944
 945 enum {
 946         WL1271_ACX_TRIG_IDX_RSSI = 0,
 947         WL1271_ACX_TRIG_COUNT = 8,
 948 };
 949
 950 struct wl1271_acx_rssi_snr_trigger {
 951         struct acx_header header;
 952
 953         __le16 threshold;
 954         __le16 pacing; /* 0 - 60000 ms */
 955         u8 metric;
 956         u8 type;
 957         u8 dir;
 958         u8 hysteresis;
 959         u8 index;
 960         u8 enable;
 961         u8 padding[2];
 962 };
 963
 964 struct wl1271_acx_rssi_snr_avg_weights {
 965         struct acx_header header;
 966
 967         u8 rssi_beacon;
 968         u8 rssi_data;
 969         u8 snr_beacon;
 970         u8 snr_data;
 971 };
 972
 973 /*
 974  * ACX_PEER_HT_CAP
 975  * Configure HT capabilities - declare the capabilities of the peer
 976  * we are connected to.
 977  */
 978 struct wl1271_acx_ht_capabilities {
 979         struct acx_header header;
 980
 981         /*
 982          * bit 0 - Allow HT Operation
 983          * bit 1 - Allow Greenfield format in TX
 984          * bit 2 - Allow Short GI in TX
 985          * bit 3 - Allow L-SIG TXOP Protection in TX
 986          * bit 4 - Allow HT Control fields in TX.
 987          *         Note, driver will still leave space for HT control in packets
 988          *         regardless of the value of this field. FW will be responsible
 989          *         to drop the HT field from any frame when this Bit set to 0.
 990          * bit 5 - Allow RD initiation in TXOP. FW is allowed to initate RD.
 991          *         Exact policy setting for this feature is TBD.
 992          *         Note, this bit can only be set to 1 if bit 3 is set to 1.
 993          */
 994         __le32 ht_capabilites;
 995
 996         /*
 997          * Indicates to which peer these capabilities apply.
 998          * For infrastructure use ff:ff:ff:ff:ff:ff that indicates relevance
 999          * for all peers.
1000          * Only valid for IBSS/DLS operation.
1001          */
1002         u8 mac_address[ETH_ALEN];
1003
1004         /*
1005          * This the maximum A-MPDU length supported by the AP. The FW may not
1006          * exceed this length when sending A-MPDUs
1007          */
1008         u8 ampdu_max_length;
1009
1010         /* This is the minimal spacing required when sending A-MPDUs to the AP*/
1011         u8 ampdu_min_spacing;
1012 } __packed;
1013
1014 /* HT Capabilites Fw Bit Mask Mapping */
1015 #define WL1271_ACX_FW_CAP_HT_OPERATION                 BIT(0)
1016 #define WL1271_ACX_FW_CAP_GREENFIELD_FRAME_FORMAT      BIT(1)
1017 #define WL1271_ACX_FW_CAP_SHORT_GI_FOR_20MHZ_PACKETS   BIT(2)
1018 #define WL1271_ACX_FW_CAP_LSIG_TXOP_PROTECTION         BIT(3)
1019 #define WL1271_ACX_FW_CAP_HT_CONTROL_FIELDS            BIT(4)
1020 #define WL1271_ACX_FW_CAP_RD_INITIATION                BIT(5)
1021
1022
1023 /*
1024  * ACX_HT_BSS_OPERATION
1025  * Configure HT capabilities - AP rules for behavior in the BSS.
1026  */
1027 struct wl1271_acx_ht_information {
1028         struct acx_header header;
1029
1030         /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
1031         u8 rifs_mode;
1032
1033         /* Values: 0 - 3 like in spec */
1034         u8 ht_protection;
1035
1036         /* Values: 0 - GF protection not required, 1 - GF protection required */
1037         u8 gf_protection;
1038
1039         /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
1040         u8 ht_tx_burst_limit;
1041
1042         /*
1043          * Values: 0 - Dual CTS protection not required,
1044          *         1 - Dual CTS Protection required
1045          * Note: When this value is set to 1 FW will protect all TXOP with RTS
1046          * frame and will not use CTS-to-self regardless of the value of the
1047          * ACX_CTS_PROTECTION information element
1048          */
1049         u8 dual_cts_protection;
1050
1051         u8 padding[3];
1052 } __packed;
1053
1054 struct wl1271_acx_fw_tsf_information {
1055         struct acx_header header;
1056
1057         __le32 current_tsf_high;
1058         __le32 current_tsf_low;
1059         __le32 last_bttt_high;
1060         __le32 last_tbtt_low;
1061         u8 last_dtim_count;
1062         u8 padding[3];
1063 } __packed;
1064
1065 enum {
1066         ACX_WAKE_UP_CONDITIONS      = 0x0002,
1067         ACX_MEM_CFG                 = 0x0003,
1068         ACX_SLOT                    = 0x0004,
1069         ACX_AC_CFG                  = 0x0007,
1070         ACX_MEM_MAP                 = 0x0008,
1071         ACX_AID                     = 0x000A,
1072         /* ACX_FW_REV is missing in the ref driver, but seems to work */
1073         ACX_FW_REV                  = 0x000D,
1074         ACX_MEDIUM_USAGE            = 0x000F,
1075         ACX_RX_CFG                  = 0x0010,
1076         ACX_TX_QUEUE_CFG            = 0x0011, /* FIXME: only used by wl1251 */
1077         ACX_STATISTICS              = 0x0013, /* Debug API */
1078         ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
1079         ACX_FEATURE_CFG             = 0x0015,
1080         ACX_TID_CFG                 = 0x001A,
1081         ACX_PS_RX_STREAMING         = 0x001B,
1082         ACX_BEACON_FILTER_OPT       = 0x001F,
1083         ACX_NOISE_HIST              = 0x0021,
1084         ACX_HDK_VERSION             = 0x0022, /* ??? */
1085         ACX_PD_THRESHOLD            = 0x0023,
1086         ACX_TX_CONFIG_OPT           = 0x0024,
1087         ACX_CCA_THRESHOLD           = 0x0025,
1088         ACX_EVENT_MBOX_MASK         = 0x0026,
1089         ACX_CONN_MONIT_PARAMS       = 0x002D,
1090         ACX_CONS_TX_FAILURE         = 0x002F,
1091         ACX_BCN_DTIM_OPTIONS        = 0x0031,
1092         ACX_SG_ENABLE               = 0x0032,
1093         ACX_SG_CFG                  = 0x0033,
1094         ACX_BEACON_FILTER_TABLE     = 0x0038,
1095         ACX_ARP_IP_FILTER           = 0x0039,
1096         ACX_ROAMING_STATISTICS_TBL  = 0x003B,
1097         ACX_RATE_POLICY             = 0x003D,
1098         ACX_CTS_PROTECTION          = 0x003E,
1099         ACX_SLEEP_AUTH              = 0x003F,
1100         ACX_PREAMBLE_TYPE           = 0x0040,
1101         ACX_ERROR_CNT               = 0x0041,
1102         ACX_IBSS_FILTER             = 0x0044,
1103         ACX_SERVICE_PERIOD_TIMEOUT  = 0x0045,
1104         ACX_TSF_INFO                = 0x0046,
1105         ACX_CONFIG_PS_WMM           = 0x0049,
1106         ACX_ENABLE_RX_DATA_FILTER   = 0x004A,
1107         ACX_SET_RX_DATA_FILTER      = 0x004B,
1108         ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1109         ACX_RX_CONFIG_OPT           = 0x004E,
1110         ACX_FRAG_CFG                = 0x004F,
1111         ACX_BET_ENABLE              = 0x0050,
1112         ACX_RSSI_SNR_TRIGGER        = 0x0051,
1113         ACX_RSSI_SNR_WEIGHTS        = 0x0052,
1114         ACX_KEEP_ALIVE_MODE         = 0x0053,
1115         ACX_SET_KEEP_ALIVE_CONFIG   = 0x0054,
1116         ACX_BA_SESSION_RESPONDER_POLICY = 0x0055,
1117         ACX_BA_SESSION_INITIATOR_POLICY = 0x0056,
1118         ACX_PEER_HT_CAP             = 0x0057,
1119         ACX_HT_BSS_OPERATION        = 0x0058,
1120         ACX_COEX_ACTIVITY           = 0x0059,
1121         ACX_SET_DCO_ITRIM_PARAMS    = 0x0061,
1122         DOT11_RX_MSDU_LIFE_TIME     = 0x1004,
1123         DOT11_CUR_TX_PWR            = 0x100D,
1124         DOT11_RX_DOT11_MODE         = 0x1012,
1125         DOT11_RTS_THRESHOLD         = 0x1013,
1126         DOT11_GROUP_ADDRESS_TBL     = 0x1014,
1127         ACX_PM_CONFIG               = 0x1016,
1128
1129         MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1130
1131         MAX_IE = 0xFFFF
1132 };
1133
1134
1135 int wl1271_acx_wake_up_conditions(struct wl1271 *wl);
1136 int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1137 int wl1271_acx_tx_power(struct wl1271 *wl, int power);
1138 int wl1271_acx_feature_cfg(struct wl1271 *wl);
1139 int wl1271_acx_mem_map(struct wl1271 *wl,
1140                        struct acx_header *mem_map, size_t len);
1141 int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1142 int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter);
1143 int wl1271_acx_pd_threshold(struct wl1271 *wl);
1144 int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time);
1145 int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable,
1146                                  void *mc_list, u32 mc_list_len);
1147 int wl1271_acx_service_period_timeout(struct wl1271 *wl);
1148 int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold);
1149 int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1150 int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter);
1151 int wl1271_acx_beacon_filter_table(struct wl1271 *wl);
1152 int wl1271_acx_conn_monit_params(struct wl1271 *wl, bool enable);
1153 int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1154 int wl1271_acx_sg_cfg(struct wl1271 *wl);
1155 int wl1271_acx_cca_threshold(struct wl1271 *wl);
1156 int wl1271_acx_bcn_dtim_options(struct wl1271 *wl);
1157 int wl1271_acx_aid(struct wl1271 *wl, u16 aid);
1158 int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1159 int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble);
1160 int wl1271_acx_cts_protect(struct wl1271 *wl,
1161                            enum acx_ctsprotect_type ctsprotect);
1162 int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
1163 int wl1271_acx_rate_policies(struct wl1271 *wl);
1164 int wl1271_acx_ac_cfg(struct wl1271 *wl, u8 ac, u8 cw_min, u16 cw_max,
1165                       u8 aifsn, u16 txop);
1166 int wl1271_acx_tid_cfg(struct wl1271 *wl, u8 queue_id, u8 channel_type,
1167                        u8 tsid, u8 ps_scheme, u8 ack_policy,
1168                        u32 apsd_conf0, u32 apsd_conf1);
1169 int wl1271_acx_frag_threshold(struct wl1271 *wl, u16 frag_threshold);
1170 int wl1271_acx_tx_config_options(struct wl1271 *wl);
1171 int wl1271_acx_mem_cfg(struct wl1271 *wl);
1172 int wl1271_acx_init_mem_config(struct wl1271 *wl);
1173 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1174 int wl1271_acx_smart_reflex(struct wl1271 *wl);
1175 int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable);
1176 int wl1271_acx_arp_ip_filter(struct wl1271 *wl, u8 enable, __be32 address);
1177 int wl1271_acx_pm_config(struct wl1271 *wl);
1178 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, bool enable);
1179 int wl1271_acx_keep_alive_config(struct wl1271 *wl, u8 index, u8 tpl_valid);
1180 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, bool enable,
1181                                 s16 thold, u8 hyst);
1182 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl);
1183 int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
1184                                     struct ieee80211_sta_ht_cap *ht_cap,
1185                                     bool allow_ht_operation);
1186 int wl1271_acx_set_ht_information(struct wl1271 *wl,
1187                                    u16 ht_operation_mode);
1188 int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime);
1189
1190 #endif /* __WL1271_ACX_H__ */