drivers/net/wireless/wl12xx/boot.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/slab.h>
  25
  26 #include "acx.h"
  27 #include "reg.h"
  28 #include "boot.h"
  29 #include "io.h"
  30 #include "event.h"
  31
  32 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
  33         [PART_DOWN] = {
  34                 .mem = {
  35                         .start = 0x00000000,
  36                         .size  = 0x000177c0
  37                 },
  38                 .reg = {
  39                         .start = REGISTERS_BASE,
  40                         .size  = 0x00008800
  41                 },
  42                 .mem2 = {
  43                         .start = 0x00000000,
  44                         .size  = 0x00000000
  45                 },
  46                 .mem3 = {
  47                         .start = 0x00000000,
  48                         .size  = 0x00000000
  49                 },
  50         },
  51
  52         [PART_WORK] = {
  53                 .mem = {
  54                         .start = 0x00040000,
  55                         .size  = 0x00014fc0
  56                 },
  57                 .reg = {
  58                         .start = REGISTERS_BASE,
  59                         .size  = 0x0000a000
  60                 },
  61                 .mem2 = {
  62                         .start = 0x003004f8,
  63                         .size  = 0x00000004
  64                 },
  65                 .mem3 = {
  66                         .start = 0x00040404,
  67                         .size  = 0x00000000
  68                 },
  69         },
  70
  71         [PART_DRPW] = {
  72                 .mem = {
  73                         .start = 0x00040000,
  74                         .size  = 0x00014fc0
  75                 },
  76                 .reg = {
  77                         .start = DRPW_BASE,
  78                         .size  = 0x00006000
  79                 },
  80                 .mem2 = {
  81                         .start = 0x00000000,
  82                         .size  = 0x00000000
  83                 },
  84                 .mem3 = {
  85                         .start = 0x00000000,
  86                         .size  = 0x00000000
  87                 }
  88         }
  89 };
  90
  91 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  92 {
  93         u32 cpu_ctrl;
  94
  95         /* 10.5.0 run the firmware (I) */
  96         cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
  97
  98         /* 10.5.1 run the firmware (II) */
  99         cpu_ctrl |= flag;
 100         wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
 101 }
 102
 103 static void wl1271_boot_fw_version(struct wl1271 *wl)
 104 {
 105         struct wl1271_static_data static_data;
 106
 107         wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
 108                     false);
 109
 110         strncpy(wl->chip.fw_ver, static_data.fw_version,
 111                 sizeof(wl->chip.fw_ver));
 112
 113         /* make sure the string is NULL-terminated */
 114         wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
 115 }
 116
 117 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
 118                                              size_t fw_data_len, u32 dest)
 119 {
 120         struct wl1271_partition_set partition;
 121         int addr, chunk_num, partition_limit;
 122         u8 *p, *chunk;
 123
 124         /* whal_FwCtrl_LoadFwImageSm() */
 125
 126         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
 127
 128         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
 129                      fw_data_len, CHUNK_SIZE);
 130
 131         if ((fw_data_len % 4) != 0) {
 132                 wl1271_error("firmware length not multiple of four");
 133                 return -EIO;
 134         }
 135
 136         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 137         if (!chunk) {
 138                 wl1271_error("allocation for firmware upload chunk failed");
 139                 return -ENOMEM;
 140         }
 141
 142         memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
 143         partition.mem.start = dest;
 144         wl1271_set_partition(wl, &partition);
 145
 146         /* 10.1 set partition limit and chunk num */
 147         chunk_num = 0;
 148         partition_limit = part_table[PART_DOWN].mem.size;
 149
 150         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 151                 /* 10.2 update partition, if needed */
 152                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
 153                 if (addr > partition_limit) {
 154                         addr = dest + chunk_num * CHUNK_SIZE;
 155                         partition_limit = chunk_num * CHUNK_SIZE +
 156                                 part_table[PART_DOWN].mem.size;
 157                         partition.mem.start = addr;
 158                         wl1271_set_partition(wl, &partition);
 159                 }
 160
 161                 /* 10.3 upload the chunk */
 162                 addr = dest + chunk_num * CHUNK_SIZE;
 163                 p = buf + chunk_num * CHUNK_SIZE;
 164                 memcpy(chunk, p, CHUNK_SIZE);
 165                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 166                              p, addr);
 167                 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
 168
 169                 chunk_num++;
 170         }
 171
 172         /* 10.4 upload the last chunk */
 173         addr = dest + chunk_num * CHUNK_SIZE;
 174         p = buf + chunk_num * CHUNK_SIZE;
 175         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
 176         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
 177                      fw_data_len % CHUNK_SIZE, p, addr);
 178         wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
 179
 180         kfree(chunk);
 181         return 0;
 182 }
 183
 184 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
 185 {
 186         u32 chunks, addr, len;
 187         int ret = 0;
 188         u8 *fw;
 189
 190         fw = wl->fw;
 191         chunks = be32_to_cpup((__be32 *) fw);
 192         fw += sizeof(u32);
 193
 194         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
 195
 196         while (chunks--) {
 197                 addr = be32_to_cpup((__be32 *) fw);
 198                 fw += sizeof(u32);
 199                 len = be32_to_cpup((__be32 *) fw);
 200                 fw += sizeof(u32);
 201
 202                 if (len > 300000) {
 203                         wl1271_info("firmware chunk too long: %u", len);
 204                         return -EINVAL;
 205                 }
 206                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
 207                              chunks, addr, len);
 208                 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
 209                 if (ret != 0)
 210                         break;
 211                 fw += len;
 212         }
 213
 214         return ret;
 215 }
 216
 217 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
 218 {
 219         size_t nvs_len, burst_len;
 220         int i;
 221         u32 dest_addr, val;
 222         u8 *nvs_ptr, *nvs_aligned;
 223
 224         if (wl->nvs == NULL)
 225                 return -ENODEV;
 226
 227         /*
 228          * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz band
 229          * configurations) can be removed when those NVS files stop floating
 230          * around.
 231          */
 232         if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
 233             wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
 234                 if (wl->nvs->general_params.dual_mode_select)
 235                         wl->enable_11a = true;
 236         }
 237
 238         if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
 239             (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
 240              wl->enable_11a)) {
 241                 wl1271_error("nvs size is not as expected: %zu != %zu",
 242                              wl->nvs_len, sizeof(struct wl1271_nvs_file));
 243                 kfree(wl->nvs);
 244                 wl->nvs = NULL;
 245                 wl->nvs_len = 0;
 246                 return -EILSEQ;
 247         }
 248
 249         /* only the first part of the NVS needs to be uploaded */
 250         nvs_len = sizeof(wl->nvs->nvs);
 251         nvs_ptr = (u8 *)wl->nvs->nvs;
 252
 253         /* update current MAC address to NVS */
 254         nvs_ptr[11] = wl->mac_addr[0];
 255         nvs_ptr[10] = wl->mac_addr[1];
 256         nvs_ptr[6] = wl->mac_addr[2];
 257         nvs_ptr[5] = wl->mac_addr[3];
 258         nvs_ptr[4] = wl->mac_addr[4];
 259         nvs_ptr[3] = wl->mac_addr[5];
 260
 261         /*
 262          * Layout before the actual NVS tables:
 263          * 1 byte : burst length.
 264          * 2 bytes: destination address.
 265          * n bytes: data to burst copy.
 266          *
 267          * This is ended by a 0 length, then the NVS tables.
 268          */
 269
 270         /* FIXME: Do we need to check here whether the LSB is 1? */
 271         while (nvs_ptr[0]) {
 272                 burst_len = nvs_ptr[0];
 273                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 274
 275                 /*
 276                  * Due to our new wl1271_translate_reg_addr function,
 277                  * we need to add the REGISTER_BASE to the destination
 278                  */
 279                 dest_addr += REGISTERS_BASE;
 280
 281                 /* We move our pointer to the data */
 282                 nvs_ptr += 3;
 283
 284                 for (i = 0; i < burst_len; i++) {
 285                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 286                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 287
 288                         wl1271_debug(DEBUG_BOOT,
 289                                      "nvs burst write 0x%x: 0x%x",
 290                                      dest_addr, val);
 291                         wl1271_write32(wl, dest_addr, val);
 292
 293                         nvs_ptr += 4;
 294                         dest_addr += 4;
 295                 }
 296         }
 297
 298         /*
 299          * We've reached the first zero length, the first NVS table
 300          * is located at an aligned offset which is at least 7 bytes further.
 301          */
 302         nvs_ptr = (u8 *)wl->nvs->nvs +
 303                         ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
 304         nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
 305
 306         /* Now we must set the partition correctly */
 307         wl1271_set_partition(wl, &part_table[PART_WORK]);
 308
 309         /* Copy the NVS tables to a new block to ensure alignment */
 310         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
 311         if (!nvs_aligned)
 312                 return -ENOMEM;
 313
 314         /* And finally we upload the NVS tables */
 315         wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
 316
 317         kfree(nvs_aligned);
 318         return 0;
 319 }
 320
 321 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
 322 {
 323         wl1271_enable_interrupts(wl);
 324         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 325                        WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 326         wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
 327 }
 328
 329 static int wl1271_boot_soft_reset(struct wl1271 *wl)
 330 {
 331         unsigned long timeout;
 332         u32 boot_data;
 333
 334         /* perform soft reset */
 335         wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 336
 337         /* SOFT_RESET is self clearing */
 338         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 339         while (1) {
 340                 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
 341                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 342                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 343                         break;
 344
 345                 if (time_after(jiffies, timeout)) {
 346                         /* 1.2 check pWhalBus->uSelfClearTime if the
 347                          * timeout was reached */
 348                         wl1271_error("soft reset timeout");
 349                         return -1;
 350                 }
 351
 352                 udelay(SOFT_RESET_STALL_TIME);
 353         }
 354
 355         /* disable Rx/Tx */
 356         wl1271_write32(wl, ENABLE, 0x0);
 357
 358         /* disable auto calibration on start*/
 359         wl1271_write32(wl, SPARE_A2, 0xffff);
 360
 361         return 0;
 362 }
 363
 364 static int wl1271_boot_run_firmware(struct wl1271 *wl)
 365 {
 366         int loop, ret;
 367         u32 chip_id, intr;
 368
 369         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 370
 371         chip_id = wl1271_read32(wl, CHIP_ID_B);
 372
 373         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 374
 375         if (chip_id != wl->chip.id) {
 376                 wl1271_error("chip id doesn't match after firmware boot");
 377                 return -EIO;
 378         }
 379
 380         /* wait for init to complete */
 381         loop = 0;
 382         while (loop++ < INIT_LOOP) {
 383                 udelay(INIT_LOOP_DELAY);
 384                 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 385
 386                 if (intr == 0xffffffff) {
 387                         wl1271_error("error reading hardware complete "
 388                                      "init indication");
 389                         return -EIO;
 390                 }
 391                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 392                 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
 393                         wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
 394                                        WL1271_ACX_INTR_INIT_COMPLETE);
 395                         break;
 396                 }
 397         }
 398
 399         if (loop > INIT_LOOP) {
 400                 wl1271_error("timeout waiting for the hardware to "
 401                              "complete initialization");
 402                 return -EIO;
 403         }
 404
 405         /* get hardware config command mail box */
 406         wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
 407
 408         /* get hardware config event mail box */
 409         wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
 410
 411         /* set the working partition to its "running" mode offset */
 412         wl1271_set_partition(wl, &part_table[PART_WORK]);
 413
 414         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 415                      wl->cmd_box_addr, wl->event_box_addr);
 416
 417         wl1271_boot_fw_version(wl);
 418
 419         /*
 420          * in case of full asynchronous mode the firmware event must be
 421          * ready to receive event from the command mailbox
 422          */
 423
 424         /* unmask required mbox events  */
 425         wl->event_mask = BSS_LOSE_EVENT_ID |
 426                 SCAN_COMPLETE_EVENT_ID |
 427                 PS_REPORT_EVENT_ID |
 428                 JOIN_EVENT_COMPLETE_ID |
 429                 DISCONNECT_EVENT_COMPLETE_ID |
 430                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 431                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
 432                 SOFT_GEMINI_SENSE_EVENT_ID;
 433
 434         ret = wl1271_event_unmask(wl);
 435         if (ret < 0) {
 436                 wl1271_error("EVENT mask setting failed");
 437                 return ret;
 438         }
 439
 440         wl1271_event_mbox_config(wl);
 441
 442         /* firmware startup completed */
 443         return 0;
 444 }
 445
 446 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
 447 {
 448         u32 polarity;
 449
 450         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
 451
 452         /* We use HIGH polarity, so unset the LOW bit */
 453         polarity &= ~POLARITY_LOW;
 454         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
 455
 456         return 0;
 457 }
 458
 459 static void wl1271_boot_hw_version(struct wl1271 *wl)
 460 {
 461         u32 fuse;
 462
 463         fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
 464         fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
 465
 466         wl->hw_pg_ver = (s8)fuse;
 467 }
 468
 469 /* uploads NVS and firmware */
 470 int wl1271_load_firmware(struct wl1271 *wl)
 471 {
 472         int ret = 0;
 473         u32 tmp, clk, pause;
 474
 475         wl1271_boot_hw_version(wl);
 476
 477         if (wl->ref_clock == 0 || wl->ref_clock == 2 || wl->ref_clock == 4)
 478                 /* ref clk: 19.2/38.4/38.4-XTAL */
 479                 clk = 0x3;
 480         else if (wl->ref_clock == 1 || wl->ref_clock == 3)
 481                 /* ref clk: 26/52 */
 482                 clk = 0x5;
 483         else
 484                 return -EINVAL;
 485
 486         if (wl->ref_clock != 0) {
 487                 u16 val;
 488                 /* Set clock type (open drain) */
 489                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
 490                 val &= FREF_CLK_TYPE_BITS;
 491                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 492
 493                 /* Set clock pull mode (no pull) */
 494                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
 495                 val |= NO_PULL;
 496                 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 497         } else {
 498                 u16 val;
 499                 /* Set clock polarity */
 500                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
 501                 val &= FREF_CLK_POLARITY_BITS;
 502                 val |= CLK_REQ_OUTN_SEL;
 503                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
 504         }
 505
 506         wl1271_write32(wl, PLL_PARAMETERS, clk);
 507
 508         pause = wl1271_read32(wl, PLL_PARAMETERS);
 509
 510         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 511
 512         pause &= ~(WU_COUNTER_PAUSE_VAL);
 513         pause |= WU_COUNTER_PAUSE_VAL;
 514         wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
 515
 516         /* Continue the ELP wake up sequence */
 517         wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 518         udelay(500);
 519
 520         wl1271_set_partition(wl, &part_table[PART_DRPW]);
 521
 522         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 523            to be used by DRPw FW. The RTRIM value will be added by the FW
 524            before taking DRPw out of reset */
 525
 526         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
 527         clk = wl1271_read32(wl, DRPW_SCRATCH_START);
 528
 529         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 530
 531         clk |= (wl->ref_clock << 1) << 4;
 532         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
 533
 534         wl1271_set_partition(wl, &part_table[PART_WORK]);
 535
 536         /* Disable interrupts */
 537         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 538
 539         ret = wl1271_boot_soft_reset(wl);
 540         if (ret < 0)
 541                 goto out;
 542
 543         /* 2. start processing NVS file */
 544         ret = wl1271_boot_upload_nvs(wl);
 545         if (ret < 0)
 546                 goto out;
 547
 548         /* write firmware's last address (ie. it's length) to
 549          * ACX_EEPROMLESS_IND_REG */
 550         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
 551
 552         wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
 553
 554         tmp = wl1271_read32(wl, CHIP_ID_B);
 555
 556         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 557
 558         /* 6. read the EEPROM parameters */
 559         tmp = wl1271_read32(wl, SCR_PAD2);
 560
 561         ret = wl1271_boot_write_irq_polarity(wl);
 562         if (ret < 0)
 563                 goto out;
 564
 565         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 566                        WL1271_ACX_ALL_EVENTS_VECTOR);
 567
 568         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
 569          * to upload_fw) */
 570
 571         ret = wl1271_boot_upload_firmware(wl);
 572         if (ret < 0)
 573                 goto out;
 574
 575 out:
 576         return ret;
 577 }
 578 EXPORT_SYMBOL_GPL(wl1271_load_firmware);
 579
 580 int wl1271_boot(struct wl1271 *wl)
 581 {
 582         int ret;
 583
 584         /* upload NVS and firmware */
 585         ret = wl1271_load_firmware(wl);
 586         if (ret)
 587                 return ret;
 588
 589         /* 10.5 start firmware */
 590         ret = wl1271_boot_run_firmware(wl);
 591         if (ret < 0)
 592                 goto out;
 593
 594         /* Enable firmware interrupts now */
 595         wl1271_boot_enable_interrupts(wl);
 596
 597         /* set the wl1271 default filters */
 598         wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
 599         wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
 600
 601         wl1271_event_mbox_config(wl);
 602
 603 out:
 604         return ret;
 605 }