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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / usb / gadget / ci13xxx_udc.c
blob31656a2b4ab487a1ec14500664930c1c82401b70
1 /*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
25 *
26 * Compile Options
27 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
28 * - STALL_IN: non-empty bulk-in pipes cannot be halted
29 * if defined mass storage compliance succeeds but with warnings
30 * => case 4: Hi > Dn
31 * => case 5: Hi > Di
32 * => case 8: Hi <> Do
33 * if undefined usbtest 13 fails
34 * - TRACE: enable function tracing (depends on DEBUG)
35 *
36 * Main Features
37 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
38 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
39 * - Normal & LPM support
40 *
41 * USBTEST Report
42 * - OK: 0-12, 13 (STALL_IN defined) & 14
43 * - Not Supported: 15 & 16 (ISO)
44 *
45 * TODO List
46 * - OTG
47 * - Isochronous & Interrupt Traffic
48 * - Handle requests which spawns into several TDs
49 * - GET_STATUS(device) - always reports 0
50 * - Gadget API (majority of optional features)
51 * - Suspend & Remote Wakeup
52 */
53 #include <linux/delay.h>
54 #include <linux/device.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/init.h>
58 #include <linux/interrupt.h>
59 #include <linux/io.h>
60 #include <linux/irq.h>
61 #include <linux/kernel.h>
62 #include <linux/slab.h>
63 #include <linux/pm_runtime.h>
64 #include <linux/usb/ch9.h>
65 #include <linux/usb/gadget.h>
66 #include <linux/usb/otg.h>
67
68 #include "ci13xxx_udc.h"
69
70
71 /******************************************************************************
72 * DEFINE
73 *****************************************************************************/
74 /* ctrl register bank access */
75 static DEFINE_SPINLOCK(udc_lock);
76
77 /* control endpoint description */
78 static const struct usb_endpoint_descriptor
79 ctrl_endpt_desc = {
80 .bLength = USB_DT_ENDPOINT_SIZE,
81 .bDescriptorType = USB_DT_ENDPOINT,
82
83 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
84 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
85 };
86
87 /* UDC descriptor */
88 static struct ci13xxx *_udc;
89
90 /* Interrupt statistics */
91 #define ISR_MASK 0x1F
92 static struct {
93 u32 test;
94 u32 ui;
95 u32 uei;
96 u32 pci;
97 u32 uri;
98 u32 sli;
99 u32 none;
100 struct {
101 u32 cnt;
102 u32 buf[ISR_MASK+1];
103 u32 idx;
104 } hndl;
105 } isr_statistics;
106
107 /**
108 * ffs_nr: find first (least significant) bit set
109 * @x: the word to search
110 *
111 * This function returns bit number (instead of position)
112 */
113 static int ffs_nr(u32 x)
114 {
115 int n = ffs(x);
116
117 return n ? n-1 : 32;
118 }
119
120 /******************************************************************************
121 * HW block
122 *****************************************************************************/
123 /* register bank descriptor */
124 static struct {
125 unsigned lpm; /* is LPM? */
126 void __iomem *abs; /* bus map offset */
127 void __iomem *cap; /* bus map offset + CAP offset + CAP data */
128 size_t size; /* bank size */
129 } hw_bank;
130
131 /* MSM specific */
132 #define ABS_AHBBURST (0x0090UL)
133 #define ABS_AHBMODE (0x0098UL)
134 /* UDC register map */
135 #define ABS_CAPLENGTH (0x100UL)
136 #define ABS_HCCPARAMS (0x108UL)
137 #define ABS_DCCPARAMS (0x124UL)
138 #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
139 /* offset to CAPLENTGH (addr + data) */
140 #define CAP_USBCMD (0x000UL)
141 #define CAP_USBSTS (0x004UL)
142 #define CAP_USBINTR (0x008UL)
143 #define CAP_DEVICEADDR (0x014UL)
144 #define CAP_ENDPTLISTADDR (0x018UL)
145 #define CAP_PORTSC (0x044UL)
146 #define CAP_DEVLC (0x084UL)
147 #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
148 #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
149 #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
150 #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
151 #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
152 #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
153 #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
154 #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
155
156 /* maximum number of enpoints: valid only after hw_device_reset() */
157 static unsigned hw_ep_max;
158
159 /**
160 * hw_ep_bit: calculates the bit number
161 * @num: endpoint number
162 * @dir: endpoint direction
163 *
164 * This function returns bit number
165 */
166 static inline int hw_ep_bit(int num, int dir)
167 {
168 return num + (dir ? 16 : 0);
169 }
170
171 /**
172 * hw_aread: reads from register bitfield
173 * @addr: address relative to bus map
174 * @mask: bitfield mask
175 *
176 * This function returns register bitfield data
177 */
178 static u32 hw_aread(u32 addr, u32 mask)
179 {
180 return ioread32(addr + hw_bank.abs) & mask;
181 }
182
183 /**
184 * hw_awrite: writes to register bitfield
185 * @addr: address relative to bus map
186 * @mask: bitfield mask
187 * @data: new data
188 */
189 static void hw_awrite(u32 addr, u32 mask, u32 data)
190 {
191 iowrite32(hw_aread(addr, ~mask) | (data & mask),
192 addr + hw_bank.abs);
193 }
194
195 /**
196 * hw_cread: reads from register bitfield
197 * @addr: address relative to CAP offset plus content
198 * @mask: bitfield mask
199 *
200 * This function returns register bitfield data
201 */
202 static u32 hw_cread(u32 addr, u32 mask)
203 {
204 return ioread32(addr + hw_bank.cap) & mask;
205 }
206
207 /**
208 * hw_cwrite: writes to register bitfield
209 * @addr: address relative to CAP offset plus content
210 * @mask: bitfield mask
211 * @data: new data
212 */
213 static void hw_cwrite(u32 addr, u32 mask, u32 data)
214 {
215 iowrite32(hw_cread(addr, ~mask) | (data & mask),
216 addr + hw_bank.cap);
217 }
218
219 /**
220 * hw_ctest_and_clear: tests & clears register bitfield
221 * @addr: address relative to CAP offset plus content
222 * @mask: bitfield mask
223 *
224 * This function returns register bitfield data
225 */
226 static u32 hw_ctest_and_clear(u32 addr, u32 mask)
227 {
228 u32 reg = hw_cread(addr, mask);
229
230 iowrite32(reg, addr + hw_bank.cap);
231 return reg;
232 }
233
234 /**
235 * hw_ctest_and_write: tests & writes register bitfield
236 * @addr: address relative to CAP offset plus content
237 * @mask: bitfield mask
238 * @data: new data
239 *
240 * This function returns register bitfield data
241 */
242 static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
243 {
244 u32 reg = hw_cread(addr, ~0);
245
246 iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
247 return (reg & mask) >> ffs_nr(mask);
248 }
249
250 static int hw_device_init(void __iomem *base)
251 {
252 u32 reg;
253
254 /* bank is a module variable */
255 hw_bank.abs = base;
256
257 hw_bank.cap = hw_bank.abs;
258 hw_bank.cap += ABS_CAPLENGTH;
259 hw_bank.cap += ioread8(hw_bank.cap);
260
261 reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
262 hw_bank.lpm = reg;
263 hw_bank.size = hw_bank.cap - hw_bank.abs;
264 hw_bank.size += CAP_LAST;
265 hw_bank.size /= sizeof(u32);
266
267 reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
268 if (reg == 0 || reg > ENDPT_MAX)
269 return -ENODEV;
270
271 hw_ep_max = reg; /* cache hw ENDPT_MAX */
272
273 /* setup lock mode ? */
274
275 /* ENDPTSETUPSTAT is '0' by default */
276
277 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
278
279 return 0;
280 }
281 /**
282 * hw_device_reset: resets chip (execute without interruption)
283 * @base: register base address
284 *
285 * This function returns an error code
286 */
287 static int hw_device_reset(struct ci13xxx *udc)
288 {
289 /* should flush & stop before reset */
290 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
291 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
292
293 hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
294 while (hw_cread(CAP_USBCMD, USBCMD_RST))
295 udelay(10); /* not RTOS friendly */
296
297
298 if (udc->udc_driver->notify_event)
299 udc->udc_driver->notify_event(udc,
300 CI13XXX_CONTROLLER_RESET_EVENT);
301
302 if (udc->udc_driver->flags && CI13XXX_DISABLE_STREAMING)
303 hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
304
305 /* USBMODE should be configured step by step */
306 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
307 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
308 hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
309
310 if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
311 pr_err("cannot enter in device mode");
312 pr_err("lpm = %i", hw_bank.lpm);
313 return -ENODEV;
314 }
315
316 return 0;
317 }
318
319 /**
320 * hw_device_state: enables/disables interrupts & starts/stops device (execute
321 * without interruption)
322 * @dma: 0 => disable, !0 => enable and set dma engine
323 *
324 * This function returns an error code
325 */
326 static int hw_device_state(u32 dma)
327 {
328 if (dma) {
329 hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
330 /* interrupt, error, port change, reset, sleep/suspend */
331 hw_cwrite(CAP_USBINTR, ~0,
332 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
333 hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
334 } else {
335 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
336 hw_cwrite(CAP_USBINTR, ~0, 0);
337 }
338 return 0;
339 }
340
341 /**
342 * hw_ep_flush: flush endpoint fifo (execute without interruption)
343 * @num: endpoint number
344 * @dir: endpoint direction
345 *
346 * This function returns an error code
347 */
348 static int hw_ep_flush(int num, int dir)
349 {
350 int n = hw_ep_bit(num, dir);
351
352 do {
353 /* flush any pending transfer */
354 hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
355 while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
356 cpu_relax();
357 } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
358
359 return 0;
360 }
361
362 /**
363 * hw_ep_disable: disables endpoint (execute without interruption)
364 * @num: endpoint number
365 * @dir: endpoint direction
366 *
367 * This function returns an error code
368 */
369 static int hw_ep_disable(int num, int dir)
370 {
371 hw_ep_flush(num, dir);
372 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
373 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
374 return 0;
375 }
376
377 /**
378 * hw_ep_enable: enables endpoint (execute without interruption)
379 * @num: endpoint number
380 * @dir: endpoint direction
381 * @type: endpoint type
382 *
383 * This function returns an error code
384 */
385 static int hw_ep_enable(int num, int dir, int type)
386 {
387 u32 mask, data;
388
389 if (dir) {
390 mask = ENDPTCTRL_TXT; /* type */
391 data = type << ffs_nr(mask);
392
393 mask |= ENDPTCTRL_TXS; /* unstall */
394 mask |= ENDPTCTRL_TXR; /* reset data toggle */
395 data |= ENDPTCTRL_TXR;
396 mask |= ENDPTCTRL_TXE; /* enable */
397 data |= ENDPTCTRL_TXE;
398 } else {
399 mask = ENDPTCTRL_RXT; /* type */
400 data = type << ffs_nr(mask);
401
402 mask |= ENDPTCTRL_RXS; /* unstall */
403 mask |= ENDPTCTRL_RXR; /* reset data toggle */
404 data |= ENDPTCTRL_RXR;
405 mask |= ENDPTCTRL_RXE; /* enable */
406 data |= ENDPTCTRL_RXE;
407 }
408 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
409 return 0;
410 }
411
412 /**
413 * hw_ep_get_halt: return endpoint halt status
414 * @num: endpoint number
415 * @dir: endpoint direction
416 *
417 * This function returns 1 if endpoint halted
418 */
419 static int hw_ep_get_halt(int num, int dir)
420 {
421 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
422
423 return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
424 }
425
426 /**
427 * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
428 * @num: endpoint number
429 * @dir: endpoint direction
430 *
431 * This function returns true if endpoint primed
432 */
433 static int hw_ep_is_primed(int num, int dir)
434 {
435 u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
436
437 return test_bit(hw_ep_bit(num, dir), (void *)&reg);
438 }
439
440 /**
441 * hw_test_and_clear_setup_status: test & clear setup status (execute without
442 * interruption)
443 * @n: bit number (endpoint)
444 *
445 * This function returns setup status
446 */
447 static int hw_test_and_clear_setup_status(int n)
448 {
449 return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
450 }
451
452 /**
453 * hw_ep_prime: primes endpoint (execute without interruption)
454 * @num: endpoint number
455 * @dir: endpoint direction
456 * @is_ctrl: true if control endpoint
457 *
458 * This function returns an error code
459 */
460 static int hw_ep_prime(int num, int dir, int is_ctrl)
461 {
462 int n = hw_ep_bit(num, dir);
463
464 /* the caller should flush first */
465 if (hw_ep_is_primed(num, dir))
466 return -EBUSY;
467
468 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
469 return -EAGAIN;
470
471 hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
472
473 while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
474 cpu_relax();
475 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
476 return -EAGAIN;
477
478 /* status shoult be tested according with manual but it doesn't work */
479 return 0;
480 }
481
482 /**
483 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
484 * without interruption)
485 * @num: endpoint number
486 * @dir: endpoint direction
487 * @value: true => stall, false => unstall
488 *
489 * This function returns an error code
490 */
491 static int hw_ep_set_halt(int num, int dir, int value)
492 {
493 if (value != 0 && value != 1)
494 return -EINVAL;
495
496 do {
497 u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
498 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
499 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
500
501 /* data toggle - reserved for EP0 but it's in ESS */
502 hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
503
504 } while (value != hw_ep_get_halt(num, dir));
505
506 return 0;
507 }
508
509 /**
510 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
511 * interruption)
512 * @n: interrupt bit
513 *
514 * This function returns an error code
515 */
516 static int hw_intr_clear(int n)
517 {
518 if (n >= REG_BITS)
519 return -EINVAL;
520
521 hw_cwrite(CAP_USBINTR, BIT(n), 0);
522 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
523 return 0;
524 }
525
526 /**
527 * hw_intr_force: enables interrupt & forces interrupt status (execute without
528 * interruption)
529 * @n: interrupt bit
530 *
531 * This function returns an error code
532 */
533 static int hw_intr_force(int n)
534 {
535 if (n >= REG_BITS)
536 return -EINVAL;
537
538 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
539 hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
540 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
541 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
542 return 0;
543 }
544
545 /**
546 * hw_is_port_high_speed: test if port is high speed
547 *
548 * This function returns true if high speed port
549 */
550 static int hw_port_is_high_speed(void)
551 {
552 return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
553 hw_cread(CAP_PORTSC, PORTSC_HSP);
554 }
555
556 /**
557 * hw_port_test_get: reads port test mode value
558 *
559 * This function returns port test mode value
560 */
561 static u8 hw_port_test_get(void)
562 {
563 return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
564 }
565
566 /**
567 * hw_port_test_set: writes port test mode (execute without interruption)
568 * @mode: new value
569 *
570 * This function returns an error code
571 */
572 static int hw_port_test_set(u8 mode)
573 {
574 const u8 TEST_MODE_MAX = 7;
575
576 if (mode > TEST_MODE_MAX)
577 return -EINVAL;
578
579 hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
580 return 0;
581 }
582
583 /**
584 * hw_read_intr_enable: returns interrupt enable register
585 *
586 * This function returns register data
587 */
588 static u32 hw_read_intr_enable(void)
589 {
590 return hw_cread(CAP_USBINTR, ~0);
591 }
592
593 /**
594 * hw_read_intr_status: returns interrupt status register
595 *
596 * This function returns register data
597 */
598 static u32 hw_read_intr_status(void)
599 {
600 return hw_cread(CAP_USBSTS, ~0);
601 }
602
603 /**
604 * hw_register_read: reads all device registers (execute without interruption)
605 * @buf: destination buffer
606 * @size: buffer size
607 *
608 * This function returns number of registers read
609 */
610 static size_t hw_register_read(u32 *buf, size_t size)
611 {
612 unsigned i;
613
614 if (size > hw_bank.size)
615 size = hw_bank.size;
616
617 for (i = 0; i < size; i++)
618 buf[i] = hw_aread(i * sizeof(u32), ~0);
619
620 return size;
621 }
622
623 /**
624 * hw_register_write: writes to register
625 * @addr: register address
626 * @data: register value
627 *
628 * This function returns an error code
629 */
630 static int hw_register_write(u16 addr, u32 data)
631 {
632 /* align */
633 addr /= sizeof(u32);
634
635 if (addr >= hw_bank.size)
636 return -EINVAL;
637
638 /* align */
639 addr *= sizeof(u32);
640
641 hw_awrite(addr, ~0, data);
642 return 0;
643 }
644
645 /**
646 * hw_test_and_clear_complete: test & clear complete status (execute without
647 * interruption)
648 * @n: bit number (endpoint)
649 *
650 * This function returns complete status
651 */
652 static int hw_test_and_clear_complete(int n)
653 {
654 return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
655 }
656
657 /**
658 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
659 * without interruption)
660 *
661 * This function returns active interrutps
662 */
663 static u32 hw_test_and_clear_intr_active(void)
664 {
665 u32 reg = hw_read_intr_status() & hw_read_intr_enable();
666
667 hw_cwrite(CAP_USBSTS, ~0, reg);
668 return reg;
669 }
670
671 /**
672 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
673 * interruption)
674 *
675 * This function returns guard value
676 */
677 static int hw_test_and_clear_setup_guard(void)
678 {
679 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
680 }
681
682 /**
683 * hw_test_and_set_setup_guard: test & set setup guard (execute without
684 * interruption)
685 *
686 * This function returns guard value
687 */
688 static int hw_test_and_set_setup_guard(void)
689 {
690 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
691 }
692
693 /**
694 * hw_usb_set_address: configures USB address (execute without interruption)
695 * @value: new USB address
696 *
697 * This function returns an error code
698 */
699 static int hw_usb_set_address(u8 value)
700 {
701 /* advance */
702 hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
703 value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
704 return 0;
705 }
706
707 /**
708 * hw_usb_reset: restart device after a bus reset (execute without
709 * interruption)
710 *
711 * This function returns an error code
712 */
713 static int hw_usb_reset(void)
714 {
715 hw_usb_set_address(0);
716
717 /* ESS flushes only at end?!? */
718 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
719
720 /* clear setup token semaphores */
721 hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
722
723 /* clear complete status */
724 hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
725
726 /* wait until all bits cleared */
727 while (hw_cread(CAP_ENDPTPRIME, ~0))
728 udelay(10); /* not RTOS friendly */
729
730 /* reset all endpoints ? */
731
732 /* reset internal status and wait for further instructions
733 no need to verify the port reset status (ESS does it) */
734
735 return 0;
736 }
737
738 /******************************************************************************
739 * DBG block
740 *****************************************************************************/
741 /**
742 * show_device: prints information about device capabilities and status
743 *
744 * Check "device.h" for details
745 */
746 static ssize_t show_device(struct device *dev, struct device_attribute *attr,
747 char *buf)
748 {
749 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
750 struct usb_gadget *gadget = &udc->gadget;
751 int n = 0;
752
753 dbg_trace("[%s] %p\n", __func__, buf);
754 if (attr == NULL || buf == NULL) {
755 dev_err(dev, "[%s] EINVAL\n", __func__);
756 return 0;
757 }
758
759 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
760 gadget->speed);
761 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
762 gadget->is_dualspeed);
763 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
764 gadget->is_otg);
765 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
766 gadget->is_a_peripheral);
767 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
768 gadget->b_hnp_enable);
769 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
770 gadget->a_hnp_support);
771 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
772 gadget->a_alt_hnp_support);
773 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
774 (gadget->name ? gadget->name : ""));
775
776 return n;
777 }
778 static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
779
780 /**
781 * show_driver: prints information about attached gadget (if any)
782 *
783 * Check "device.h" for details
784 */
785 static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
786 char *buf)
787 {
788 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
789 struct usb_gadget_driver *driver = udc->driver;
790 int n = 0;
791
792 dbg_trace("[%s] %p\n", __func__, buf);
793 if (attr == NULL || buf == NULL) {
794 dev_err(dev, "[%s] EINVAL\n", __func__);
795 return 0;
796 }
797
798 if (driver == NULL)
799 return scnprintf(buf, PAGE_SIZE,
800 "There is no gadget attached!\n");
801
802 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
803 (driver->function ? driver->function : ""));
804 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
805 driver->speed);
806
807 return n;
808 }
809 static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
810
811 /* Maximum event message length */
812 #define DBG_DATA_MSG 64UL
813
814 /* Maximum event messages */
815 #define DBG_DATA_MAX 128UL
816
817 /* Event buffer descriptor */
818 static struct {
819 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
820 unsigned idx; /* index */
821 unsigned tty; /* print to console? */
822 rwlock_t lck; /* lock */
823 } dbg_data = {
824 .idx = 0,
825 .tty = 0,
826 .lck = __RW_LOCK_UNLOCKED(lck)
827 };
828
829 /**
830 * dbg_dec: decrements debug event index
831 * @idx: buffer index
832 */
833 static void dbg_dec(unsigned *idx)
834 {
835 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
836 }
837
838 /**
839 * dbg_inc: increments debug event index
840 * @idx: buffer index
841 */
842 static void dbg_inc(unsigned *idx)
843 {
844 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
845 }
846
847 /**
848 * dbg_print: prints the common part of the event
849 * @addr: endpoint address
850 * @name: event name
851 * @status: status
852 * @extra: extra information
853 */
854 static void dbg_print(u8 addr, const char *name, int status, const char *extra)
855 {
856 struct timeval tval;
857 unsigned int stamp;
858 unsigned long flags;
859
860 write_lock_irqsave(&dbg_data.lck, flags);
861
862 do_gettimeofday(&tval);
863 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
864 stamp = stamp * 1000000 + tval.tv_usec;
865
866 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
867 "%04X\t» %02X %-7.7s %4i «\t%s\n",
868 stamp, addr, name, status, extra);
869
870 dbg_inc(&dbg_data.idx);
871
872 write_unlock_irqrestore(&dbg_data.lck, flags);
873
874 if (dbg_data.tty != 0)
875 pr_notice("%04X\t» %02X %-7.7s %4i «\t%s\n",
876 stamp, addr, name, status, extra);
877 }
878
879 /**
880 * dbg_done: prints a DONE event
881 * @addr: endpoint address
882 * @td: transfer descriptor
883 * @status: status
884 */
885 static void dbg_done(u8 addr, const u32 token, int status)
886 {
887 char msg[DBG_DATA_MSG];
888
889 scnprintf(msg, sizeof(msg), "%d %02X",
890 (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
891 (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
892 dbg_print(addr, "DONE", status, msg);
893 }
894
895 /**
896 * dbg_event: prints a generic event
897 * @addr: endpoint address
898 * @name: event name
899 * @status: status
900 */
901 static void dbg_event(u8 addr, const char *name, int status)
902 {
903 if (name != NULL)
904 dbg_print(addr, name, status, "");
905 }
906
907 /*
908 * dbg_queue: prints a QUEUE event
909 * @addr: endpoint address
910 * @req: USB request
911 * @status: status
912 */
913 static void dbg_queue(u8 addr, const struct usb_request *req, int status)
914 {
915 char msg[DBG_DATA_MSG];
916
917 if (req != NULL) {
918 scnprintf(msg, sizeof(msg),
919 "%d %d", !req->no_interrupt, req->length);
920 dbg_print(addr, "QUEUE", status, msg);
921 }
922 }
923
924 /**
925 * dbg_setup: prints a SETUP event
926 * @addr: endpoint address
927 * @req: setup request
928 */
929 static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
930 {
931 char msg[DBG_DATA_MSG];
932
933 if (req != NULL) {
934 scnprintf(msg, sizeof(msg),
935 "%02X %02X %04X %04X %d", req->bRequestType,
936 req->bRequest, le16_to_cpu(req->wValue),
937 le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
938 dbg_print(addr, "SETUP", 0, msg);
939 }
940 }
941
942 /**
943 * show_events: displays the event buffer
944 *
945 * Check "device.h" for details
946 */
947 static ssize_t show_events(struct device *dev, struct device_attribute *attr,
948 char *buf)
949 {
950 unsigned long flags;
951 unsigned i, j, n = 0;
952
953 dbg_trace("[%s] %p\n", __func__, buf);
954 if (attr == NULL || buf == NULL) {
955 dev_err(dev, "[%s] EINVAL\n", __func__);
956 return 0;
957 }
958
959 read_lock_irqsave(&dbg_data.lck, flags);
960
961 i = dbg_data.idx;
962 for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
963 n += strlen(dbg_data.buf[i]);
964 if (n >= PAGE_SIZE) {
965 n -= strlen(dbg_data.buf[i]);
966 break;
967 }
968 }
969 for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
970 j += scnprintf(buf + j, PAGE_SIZE - j,
971 "%s", dbg_data.buf[i]);
972
973 read_unlock_irqrestore(&dbg_data.lck, flags);
974
975 return n;
976 }
977
978 /**
979 * store_events: configure if events are going to be also printed to console
980 *
981 * Check "device.h" for details
982 */
983 static ssize_t store_events(struct device *dev, struct device_attribute *attr,
984 const char *buf, size_t count)
985 {
986 unsigned tty;
987
988 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
989 if (attr == NULL || buf == NULL) {
990 dev_err(dev, "[%s] EINVAL\n", __func__);
991 goto done;
992 }
993
994 if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
995 dev_err(dev, "<1|0>: enable|disable console log\n");
996 goto done;
997 }
998
999 dbg_data.tty = tty;
1000 dev_info(dev, "tty = %u", dbg_data.tty);
1001
1002 done:
1003 return count;
1004 }
1005 static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
1006
1007 /**
1008 * show_inters: interrupt status, enable status and historic
1009 *
1010 * Check "device.h" for details
1011 */
1012 static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
1013 char *buf)
1014 {
1015 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1016 unsigned long flags;
1017 u32 intr;
1018 unsigned i, j, n = 0;
1019
1020 dbg_trace("[%s] %p\n", __func__, buf);
1021 if (attr == NULL || buf == NULL) {
1022 dev_err(dev, "[%s] EINVAL\n", __func__);
1023 return 0;
1024 }
1025
1026 spin_lock_irqsave(udc->lock, flags);
1027
1028 n += scnprintf(buf + n, PAGE_SIZE - n,
1029 "status = %08x\n", hw_read_intr_status());
1030 n += scnprintf(buf + n, PAGE_SIZE - n,
1031 "enable = %08x\n", hw_read_intr_enable());
1032
1033 n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
1034 isr_statistics.test);
1035 n += scnprintf(buf + n, PAGE_SIZE - n, "» ui = %d\n",
1036 isr_statistics.ui);
1037 n += scnprintf(buf + n, PAGE_SIZE - n, "» uei = %d\n",
1038 isr_statistics.uei);
1039 n += scnprintf(buf + n, PAGE_SIZE - n, "» pci = %d\n",
1040 isr_statistics.pci);
1041 n += scnprintf(buf + n, PAGE_SIZE - n, "» uri = %d\n",
1042 isr_statistics.uri);
1043 n += scnprintf(buf + n, PAGE_SIZE - n, "» sli = %d\n",
1044 isr_statistics.sli);
1045 n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
1046 isr_statistics.none);
1047 n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
1048 isr_statistics.hndl.cnt);
1049
1050 for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
1051 i &= ISR_MASK;
1052 intr = isr_statistics.hndl.buf[i];
1053
1054 if (USBi_UI & intr)
1055 n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
1056 intr &= ~USBi_UI;
1057 if (USBi_UEI & intr)
1058 n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
1059 intr &= ~USBi_UEI;
1060 if (USBi_PCI & intr)
1061 n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
1062 intr &= ~USBi_PCI;
1063 if (USBi_URI & intr)
1064 n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
1065 intr &= ~USBi_URI;
1066 if (USBi_SLI & intr)
1067 n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
1068 intr &= ~USBi_SLI;
1069 if (intr)
1070 n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
1071 if (isr_statistics.hndl.buf[i])
1072 n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
1073 }
1074
1075 spin_unlock_irqrestore(udc->lock, flags);
1076
1077 return n;
1078 }
1079
1080 /**
1081 * store_inters: enable & force or disable an individual interrutps
1082 * (to be used for test purposes only)
1083 *
1084 * Check "device.h" for details
1085 */
1086 static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
1087 const char *buf, size_t count)
1088 {
1089 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1090 unsigned long flags;
1091 unsigned en, bit;
1092
1093 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1094 if (attr == NULL || buf == NULL) {
1095 dev_err(dev, "[%s] EINVAL\n", __func__);
1096 goto done;
1097 }
1098
1099 if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
1100 dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
1101 goto done;
1102 }
1103
1104 spin_lock_irqsave(udc->lock, flags);
1105 if (en) {
1106 if (hw_intr_force(bit))
1107 dev_err(dev, "invalid bit number\n");
1108 else
1109 isr_statistics.test++;
1110 } else {
1111 if (hw_intr_clear(bit))
1112 dev_err(dev, "invalid bit number\n");
1113 }
1114 spin_unlock_irqrestore(udc->lock, flags);
1115
1116 done:
1117 return count;
1118 }
1119 static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
1120
1121 /**
1122 * show_port_test: reads port test mode
1123 *
1124 * Check "device.h" for details
1125 */
1126 static ssize_t show_port_test(struct device *dev,
1127 struct device_attribute *attr, char *buf)
1128 {
1129 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1130 unsigned long flags;
1131 unsigned mode;
1132
1133 dbg_trace("[%s] %p\n", __func__, buf);
1134 if (attr == NULL || buf == NULL) {
1135 dev_err(dev, "[%s] EINVAL\n", __func__);
1136 return 0;
1137 }
1138
1139 spin_lock_irqsave(udc->lock, flags);
1140 mode = hw_port_test_get();
1141 spin_unlock_irqrestore(udc->lock, flags);
1142
1143 return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
1144 }
1145
1146 /**
1147 * store_port_test: writes port test mode
1148 *
1149 * Check "device.h" for details
1150 */
1151 static ssize_t store_port_test(struct device *dev,
1152 struct device_attribute *attr,
1153 const char *buf, size_t count)
1154 {
1155 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1156 unsigned long flags;
1157 unsigned mode;
1158
1159 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1160 if (attr == NULL || buf == NULL) {
1161 dev_err(dev, "[%s] EINVAL\n", __func__);
1162 goto done;
1163 }
1164
1165 if (sscanf(buf, "%u", &mode) != 1) {
1166 dev_err(dev, "<mode>: set port test mode");
1167 goto done;
1168 }
1169
1170 spin_lock_irqsave(udc->lock, flags);
1171 if (hw_port_test_set(mode))
1172 dev_err(dev, "invalid mode\n");
1173 spin_unlock_irqrestore(udc->lock, flags);
1174
1175 done:
1176 return count;
1177 }
1178 static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
1179 show_port_test, store_port_test);
1180
1181 /**
1182 * show_qheads: DMA contents of all queue heads
1183 *
1184 * Check "device.h" for details
1185 */
1186 static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
1187 char *buf)
1188 {
1189 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1190 unsigned long flags;
1191 unsigned i, j, n = 0;
1192
1193 dbg_trace("[%s] %p\n", __func__, buf);
1194 if (attr == NULL || buf == NULL) {
1195 dev_err(dev, "[%s] EINVAL\n", __func__);
1196 return 0;
1197 }
1198
1199 spin_lock_irqsave(udc->lock, flags);
1200 for (i = 0; i < hw_ep_max; i++) {
1201 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1202 n += scnprintf(buf + n, PAGE_SIZE - n,
1203 "EP=%02i: RX=%08X TX=%08X\n",
1204 i, (u32)mEp->qh[RX].dma, (u32)mEp->qh[TX].dma);
1205 for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
1206 n += scnprintf(buf + n, PAGE_SIZE - n,
1207 " %04X: %08X %08X\n", j,
1208 *((u32 *)mEp->qh[RX].ptr + j),
1209 *((u32 *)mEp->qh[TX].ptr + j));
1210 }
1211 }
1212 spin_unlock_irqrestore(udc->lock, flags);
1213
1214 return n;
1215 }
1216 static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
1217
1218 /**
1219 * show_registers: dumps all registers
1220 *
1221 * Check "device.h" for details
1222 */
1223 static ssize_t show_registers(struct device *dev,
1224 struct device_attribute *attr, char *buf)
1225 {
1226 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1227 unsigned long flags;
1228 u32 dump[512];
1229 unsigned i, k, n = 0;
1230
1231 dbg_trace("[%s] %p\n", __func__, buf);
1232 if (attr == NULL || buf == NULL) {
1233 dev_err(dev, "[%s] EINVAL\n", __func__);
1234 return 0;
1235 }
1236
1237 spin_lock_irqsave(udc->lock, flags);
1238 k = hw_register_read(dump, sizeof(dump)/sizeof(u32));
1239 spin_unlock_irqrestore(udc->lock, flags);
1240
1241 for (i = 0; i < k; i++) {
1242 n += scnprintf(buf + n, PAGE_SIZE - n,
1243 "reg[0x%04X] = 0x%08X\n",
1244 i * (unsigned)sizeof(u32), dump[i]);
1245 }
1246
1247 return n;
1248 }
1249
1250 /**
1251 * store_registers: writes value to register address
1252 *
1253 * Check "device.h" for details
1254 */
1255 static ssize_t store_registers(struct device *dev,
1256 struct device_attribute *attr,
1257 const char *buf, size_t count)
1258 {
1259 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1260 unsigned long addr, data, flags;
1261
1262 dbg_trace("[%s] %p, %d\n", __func__, buf, count);
1263 if (attr == NULL || buf == NULL) {
1264 dev_err(dev, "[%s] EINVAL\n", __func__);
1265 goto done;
1266 }
1267
1268 if (sscanf(buf, "%li %li", &addr, &data) != 2) {
1269 dev_err(dev, "<addr> <data>: write data to register address");
1270 goto done;
1271 }
1272
1273 spin_lock_irqsave(udc->lock, flags);
1274 if (hw_register_write(addr, data))
1275 dev_err(dev, "invalid address range\n");
1276 spin_unlock_irqrestore(udc->lock, flags);
1277
1278 done:
1279 return count;
1280 }
1281 static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
1282 show_registers, store_registers);
1283
1284 /**
1285 * show_requests: DMA contents of all requests currently queued (all endpts)
1286 *
1287 * Check "device.h" for details
1288 */
1289 static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
1290 char *buf)
1291 {
1292 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1293 unsigned long flags;
1294 struct list_head *ptr = NULL;
1295 struct ci13xxx_req *req = NULL;
1296 unsigned i, j, k, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
1297
1298 dbg_trace("[%s] %p\n", __func__, buf);
1299 if (attr == NULL || buf == NULL) {
1300 dev_err(dev, "[%s] EINVAL\n", __func__);
1301 return 0;
1302 }
1303
1304 spin_lock_irqsave(udc->lock, flags);
1305 for (i = 0; i < hw_ep_max; i++)
1306 for (k = RX; k <= TX; k++)
1307 list_for_each(ptr, &udc->ci13xxx_ep[i].qh[k].queue)
1308 {
1309 req = list_entry(ptr,
1310 struct ci13xxx_req, queue);
1311
1312 n += scnprintf(buf + n, PAGE_SIZE - n,
1313 "EP=%02i: TD=%08X %s\n",
1314 i, (u32)req->dma,
1315 ((k == RX) ? "RX" : "TX"));
1316
1317 for (j = 0; j < qSize; j++)
1318 n += scnprintf(buf + n, PAGE_SIZE - n,
1319 " %04X: %08X\n", j,
1320 *((u32 *)req->ptr + j));
1321 }
1322 spin_unlock_irqrestore(udc->lock, flags);
1323
1324 return n;
1325 }
1326 static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
1327
1328 /**
1329 * dbg_create_files: initializes the attribute interface
1330 * @dev: device
1331 *
1332 * This function returns an error code
1333 */
1334 __maybe_unused static int dbg_create_files(struct device *dev)
1335 {
1336 int retval = 0;
1337
1338 if (dev == NULL)
1339 return -EINVAL;
1340 retval = device_create_file(dev, &dev_attr_device);
1341 if (retval)
1342 goto done;
1343 retval = device_create_file(dev, &dev_attr_driver);
1344 if (retval)
1345 goto rm_device;
1346 retval = device_create_file(dev, &dev_attr_events);
1347 if (retval)
1348 goto rm_driver;
1349 retval = device_create_file(dev, &dev_attr_inters);
1350 if (retval)
1351 goto rm_events;
1352 retval = device_create_file(dev, &dev_attr_port_test);
1353 if (retval)
1354 goto rm_inters;
1355 retval = device_create_file(dev, &dev_attr_qheads);
1356 if (retval)
1357 goto rm_port_test;
1358 retval = device_create_file(dev, &dev_attr_registers);
1359 if (retval)
1360 goto rm_qheads;
1361 retval = device_create_file(dev, &dev_attr_requests);
1362 if (retval)
1363 goto rm_registers;
1364 return 0;
1365
1366 rm_registers:
1367 device_remove_file(dev, &dev_attr_registers);
1368 rm_qheads:
1369 device_remove_file(dev, &dev_attr_qheads);
1370 rm_port_test:
1371 device_remove_file(dev, &dev_attr_port_test);
1372 rm_inters:
1373 device_remove_file(dev, &dev_attr_inters);
1374 rm_events:
1375 device_remove_file(dev, &dev_attr_events);
1376 rm_driver:
1377 device_remove_file(dev, &dev_attr_driver);
1378 rm_device:
1379 device_remove_file(dev, &dev_attr_device);
1380 done:
1381 return retval;
1382 }
1383
1384 /**
1385 * dbg_remove_files: destroys the attribute interface
1386 * @dev: device
1387 *
1388 * This function returns an error code
1389 */
1390 __maybe_unused static int dbg_remove_files(struct device *dev)
1391 {
1392 if (dev == NULL)
1393 return -EINVAL;
1394 device_remove_file(dev, &dev_attr_requests);
1395 device_remove_file(dev, &dev_attr_registers);
1396 device_remove_file(dev, &dev_attr_qheads);
1397 device_remove_file(dev, &dev_attr_port_test);
1398 device_remove_file(dev, &dev_attr_inters);
1399 device_remove_file(dev, &dev_attr_events);
1400 device_remove_file(dev, &dev_attr_driver);
1401 device_remove_file(dev, &dev_attr_device);
1402 return 0;
1403 }
1404
1405 /******************************************************************************
1406 * UTIL block
1407 *****************************************************************************/
1408 /**
1409 * _usb_addr: calculates endpoint address from direction & number
1410 * @ep: endpoint
1411 */
1412 static inline u8 _usb_addr(struct ci13xxx_ep *ep)
1413 {
1414 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
1415 }
1416
1417 /**
1418 * _hardware_queue: configures a request at hardware level
1419 * @gadget: gadget
1420 * @mEp: endpoint
1421 *
1422 * This function returns an error code
1423 */
1424 static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1425 {
1426 unsigned i;
1427
1428 trace("%p, %p", mEp, mReq);
1429
1430 /* don't queue twice */
1431 if (mReq->req.status == -EALREADY)
1432 return -EALREADY;
1433
1434 if (hw_ep_is_primed(mEp->num, mEp->dir))
1435 return -EBUSY;
1436
1437 mReq->req.status = -EALREADY;
1438
1439 if (mReq->req.length && !mReq->req.dma) {
1440 mReq->req.dma = \
1441 dma_map_single(mEp->device, mReq->req.buf,
1442 mReq->req.length, mEp->dir ?
1443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
1444 if (mReq->req.dma == 0)
1445 return -ENOMEM;
1446
1447 mReq->map = 1;
1448 }
1449
1450 /*
1451 * TD configuration
1452 * TODO - handle requests which spawns into several TDs
1453 */
1454 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
1455 mReq->ptr->next |= TD_TERMINATE;
1456 mReq->ptr->token = mReq->req.length << ffs_nr(TD_TOTAL_BYTES);
1457 mReq->ptr->token &= TD_TOTAL_BYTES;
1458 mReq->ptr->token |= TD_IOC;
1459 mReq->ptr->token |= TD_STATUS_ACTIVE;
1460 mReq->ptr->page[0] = mReq->req.dma;
1461 for (i = 1; i < 5; i++)
1462 mReq->ptr->page[i] =
1463 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
1464
1465 /*
1466 * QH configuration
1467 * At this point it's guaranteed exclusive access to qhead
1468 * (endpt is not primed) so it's no need to use tripwire
1469 */
1470 mEp->qh[mEp->dir].ptr->td.next = mReq->dma; /* TERMINATE = 0 */
1471 mEp->qh[mEp->dir].ptr->td.token &= ~TD_STATUS; /* clear status */
1472 if (mReq->req.zero == 0)
1473 mEp->qh[mEp->dir].ptr->cap |= QH_ZLT;
1474 else
1475 mEp->qh[mEp->dir].ptr->cap &= ~QH_ZLT;
1476
1477 wmb(); /* synchronize before ep prime */
1478
1479 return hw_ep_prime(mEp->num, mEp->dir,
1480 mEp->type == USB_ENDPOINT_XFER_CONTROL);
1481 }
1482
1483 /**
1484 * _hardware_dequeue: handles a request at hardware level
1485 * @gadget: gadget
1486 * @mEp: endpoint
1487 *
1488 * This function returns an error code
1489 */
1490 static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1491 {
1492 trace("%p, %p", mEp, mReq);
1493
1494 if (mReq->req.status != -EALREADY)
1495 return -EINVAL;
1496
1497 if (hw_ep_is_primed(mEp->num, mEp->dir))
1498 hw_ep_flush(mEp->num, mEp->dir);
1499
1500 mReq->req.status = 0;
1501
1502 if (mReq->map) {
1503 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
1504 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1505 mReq->req.dma = 0;
1506 mReq->map = 0;
1507 }
1508
1509 mReq->req.status = mReq->ptr->token & TD_STATUS;
1510 if ((TD_STATUS_ACTIVE & mReq->req.status) != 0)
1511 mReq->req.status = -ECONNRESET;
1512 else if ((TD_STATUS_HALTED & mReq->req.status) != 0)
1513 mReq->req.status = -1;
1514 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
1515 mReq->req.status = -1;
1516 else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
1517 mReq->req.status = -1;
1518
1519 mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
1520 mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
1521 mReq->req.actual = mReq->req.length - mReq->req.actual;
1522 mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
1523
1524 return mReq->req.actual;
1525 }
1526
1527 /**
1528 * _ep_nuke: dequeues all endpoint requests
1529 * @mEp: endpoint
1530 *
1531 * This function returns an error code
1532 * Caller must hold lock
1533 */
1534 static int _ep_nuke(struct ci13xxx_ep *mEp)
1535 __releases(mEp->lock)
1536 __acquires(mEp->lock)
1537 {
1538 trace("%p", mEp);
1539
1540 if (mEp == NULL)
1541 return -EINVAL;
1542
1543 hw_ep_flush(mEp->num, mEp->dir);
1544
1545 while (!list_empty(&mEp->qh[mEp->dir].queue)) {
1546
1547 /* pop oldest request */
1548 struct ci13xxx_req *mReq = \
1549 list_entry(mEp->qh[mEp->dir].queue.next,
1550 struct ci13xxx_req, queue);
1551 list_del_init(&mReq->queue);
1552 mReq->req.status = -ESHUTDOWN;
1553
1554 if (mReq->req.complete != NULL) {
1555 spin_unlock(mEp->lock);
1556 mReq->req.complete(&mEp->ep, &mReq->req);
1557 spin_lock(mEp->lock);
1558 }
1559 }
1560 return 0;
1561 }
1562
1563 /**
1564 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
1565 * @gadget: gadget
1566 *
1567 * This function returns an error code
1568 * Caller must hold lock
1569 */
1570 static int _gadget_stop_activity(struct usb_gadget *gadget)
1571 {
1572 struct usb_ep *ep;
1573 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
1574 struct ci13xxx_ep *mEp = container_of(gadget->ep0,
1575 struct ci13xxx_ep, ep);
1576
1577 trace("%p", gadget);
1578
1579 if (gadget == NULL)
1580 return -EINVAL;
1581
1582 /* flush all endpoints */
1583 gadget_for_each_ep(ep, gadget) {
1584 usb_ep_fifo_flush(ep);
1585 }
1586 usb_ep_fifo_flush(gadget->ep0);
1587
1588 udc->driver->disconnect(gadget);
1589
1590 /* make sure to disable all endpoints */
1591 gadget_for_each_ep(ep, gadget) {
1592 usb_ep_disable(ep);
1593 }
1594 usb_ep_disable(gadget->ep0);
1595
1596 if (mEp->status != NULL) {
1597 usb_ep_free_request(gadget->ep0, mEp->status);
1598 mEp->status = NULL;
1599 }
1600
1601 return 0;
1602 }
1603
1604 /******************************************************************************
1605 * ISR block
1606 *****************************************************************************/
1607 /**
1608 * isr_reset_handler: USB reset interrupt handler
1609 * @udc: UDC device
1610 *
1611 * This function resets USB engine after a bus reset occurred
1612 */
1613 static void isr_reset_handler(struct ci13xxx *udc)
1614 __releases(udc->lock)
1615 __acquires(udc->lock)
1616 {
1617 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[0];
1618 int retval;
1619
1620 trace("%p", udc);
1621
1622 if (udc == NULL) {
1623 err("EINVAL");
1624 return;
1625 }
1626
1627 dbg_event(0xFF, "BUS RST", 0);
1628
1629 spin_unlock(udc->lock);
1630 retval = _gadget_stop_activity(&udc->gadget);
1631 if (retval)
1632 goto done;
1633
1634 retval = hw_usb_reset();
1635 if (retval)
1636 goto done;
1637
1638 retval = usb_ep_enable(&mEp->ep, &ctrl_endpt_desc);
1639 if (!retval) {
1640 mEp->status = usb_ep_alloc_request(&mEp->ep, GFP_ATOMIC);
1641 if (mEp->status == NULL) {
1642 usb_ep_disable(&mEp->ep);
1643 retval = -ENOMEM;
1644 }
1645 }
1646 spin_lock(udc->lock);
1647
1648 done:
1649 if (retval)
1650 err("error: %i", retval);
1651 }
1652
1653 /**
1654 * isr_get_status_complete: get_status request complete function
1655 * @ep: endpoint
1656 * @req: request handled
1657 *
1658 * Caller must release lock
1659 */
1660 static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
1661 {
1662 trace("%p, %p", ep, req);
1663
1664 if (ep == NULL || req == NULL) {
1665 err("EINVAL");
1666 return;
1667 }
1668
1669 kfree(req->buf);
1670 usb_ep_free_request(ep, req);
1671 }
1672
1673 /**
1674 * isr_get_status_response: get_status request response
1675 * @ep: endpoint
1676 * @setup: setup request packet
1677 *
1678 * This function returns an error code
1679 */
1680 static int isr_get_status_response(struct ci13xxx_ep *mEp,
1681 struct usb_ctrlrequest *setup)
1682 __releases(mEp->lock)
1683 __acquires(mEp->lock)
1684 {
1685 struct usb_request *req = NULL;
1686 gfp_t gfp_flags = GFP_ATOMIC;
1687 int dir, num, retval;
1688
1689 trace("%p, %p", mEp, setup);
1690
1691 if (mEp == NULL || setup == NULL)
1692 return -EINVAL;
1693
1694 spin_unlock(mEp->lock);
1695 req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
1696 spin_lock(mEp->lock);
1697 if (req == NULL)
1698 return -ENOMEM;
1699
1700 req->complete = isr_get_status_complete;
1701 req->length = 2;
1702 req->buf = kzalloc(req->length, gfp_flags);
1703 if (req->buf == NULL) {
1704 retval = -ENOMEM;
1705 goto err_free_req;
1706 }
1707
1708 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1709 /* TODO: D1 - Remote Wakeup; D0 - Self Powered */
1710 retval = 0;
1711 } else if ((setup->bRequestType & USB_RECIP_MASK) \
1712 == USB_RECIP_ENDPOINT) {
1713 dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
1714 TX : RX;
1715 num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
1716 *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
1717 }
1718 /* else do nothing; reserved for future use */
1719
1720 spin_unlock(mEp->lock);
1721 retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
1722 spin_lock(mEp->lock);
1723 if (retval)
1724 goto err_free_buf;
1725
1726 return 0;
1727
1728 err_free_buf:
1729 kfree(req->buf);
1730 err_free_req:
1731 spin_unlock(mEp->lock);
1732 usb_ep_free_request(&mEp->ep, req);
1733 spin_lock(mEp->lock);
1734 return retval;
1735 }
1736
1737 /**
1738 * isr_setup_status_phase: queues the status phase of a setup transation
1739 * @mEp: endpoint
1740 *
1741 * This function returns an error code
1742 */
1743 static int isr_setup_status_phase(struct ci13xxx_ep *mEp)
1744 __releases(mEp->lock)
1745 __acquires(mEp->lock)
1746 {
1747 int retval;
1748
1749 trace("%p", mEp);
1750
1751 /* mEp is always valid & configured */
1752
1753 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1754 mEp->dir = (mEp->dir == TX) ? RX : TX;
1755
1756 mEp->status->no_interrupt = 1;
1757
1758 spin_unlock(mEp->lock);
1759 retval = usb_ep_queue(&mEp->ep, mEp->status, GFP_ATOMIC);
1760 spin_lock(mEp->lock);
1761
1762 return retval;
1763 }
1764
1765 /**
1766 * isr_tr_complete_low: transaction complete low level handler
1767 * @mEp: endpoint
1768 *
1769 * This function returns an error code
1770 * Caller must hold lock
1771 */
1772 static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
1773 __releases(mEp->lock)
1774 __acquires(mEp->lock)
1775 {
1776 struct ci13xxx_req *mReq;
1777 int retval;
1778
1779 trace("%p", mEp);
1780
1781 if (list_empty(&mEp->qh[mEp->dir].queue))
1782 return -EINVAL;
1783
1784 /* pop oldest request */
1785 mReq = list_entry(mEp->qh[mEp->dir].queue.next,
1786 struct ci13xxx_req, queue);
1787 list_del_init(&mReq->queue);
1788
1789 retval = _hardware_dequeue(mEp, mReq);
1790 if (retval < 0) {
1791 dbg_event(_usb_addr(mEp), "DONE", retval);
1792 goto done;
1793 }
1794
1795 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
1796
1797 if (!list_empty(&mEp->qh[mEp->dir].queue)) {
1798 struct ci13xxx_req* mReqEnq;
1799
1800 mReqEnq = list_entry(mEp->qh[mEp->dir].queue.next,
1801 struct ci13xxx_req, queue);
1802 _hardware_enqueue(mEp, mReqEnq);
1803 }
1804
1805 if (mReq->req.complete != NULL) {
1806 spin_unlock(mEp->lock);
1807 mReq->req.complete(&mEp->ep, &mReq->req);
1808 spin_lock(mEp->lock);
1809 }
1810
1811 done:
1812 return retval;
1813 }
1814
1815 /**
1816 * isr_tr_complete_handler: transaction complete interrupt handler
1817 * @udc: UDC descriptor
1818 *
1819 * This function handles traffic events
1820 */
1821 static void isr_tr_complete_handler(struct ci13xxx *udc)
1822 __releases(udc->lock)
1823 __acquires(udc->lock)
1824 {
1825 unsigned i;
1826
1827 trace("%p", udc);
1828
1829 if (udc == NULL) {
1830 err("EINVAL");
1831 return;
1832 }
1833
1834 for (i = 0; i < hw_ep_max; i++) {
1835 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1836 int type, num, err = -EINVAL;
1837 struct usb_ctrlrequest req;
1838
1839
1840 if (mEp->desc == NULL)
1841 continue; /* not configured */
1842
1843 if ((mEp->dir == RX && hw_test_and_clear_complete(i)) ||
1844 (mEp->dir == TX && hw_test_and_clear_complete(i + 16))) {
1845 err = isr_tr_complete_low(mEp);
1846 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
1847 if (err > 0) /* needs status phase */
1848 err = isr_setup_status_phase(mEp);
1849 if (err < 0) {
1850 dbg_event(_usb_addr(mEp),
1851 "ERROR", err);
1852 spin_unlock(udc->lock);
1853 if (usb_ep_set_halt(&mEp->ep))
1854 err("error: ep_set_halt");
1855 spin_lock(udc->lock);
1856 }
1857 }
1858 }
1859
1860 if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
1861 !hw_test_and_clear_setup_status(i))
1862 continue;
1863
1864 if (i != 0) {
1865 warn("ctrl traffic received at endpoint");
1866 continue;
1867 }
1868
1869 /* read_setup_packet */
1870 do {
1871 hw_test_and_set_setup_guard();
1872 memcpy(&req, &mEp->qh[RX].ptr->setup, sizeof(req));
1873 } while (!hw_test_and_clear_setup_guard());
1874
1875 type = req.bRequestType;
1876
1877 mEp->dir = (type & USB_DIR_IN) ? TX : RX;
1878
1879 dbg_setup(_usb_addr(mEp), &req);
1880
1881 switch (req.bRequest) {
1882 case USB_REQ_CLEAR_FEATURE:
1883 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1884 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
1885 goto delegate;
1886 if (req.wLength != 0)
1887 break;
1888 num = le16_to_cpu(req.wIndex);
1889 num &= USB_ENDPOINT_NUMBER_MASK;
1890 if (!udc->ci13xxx_ep[num].wedge) {
1891 spin_unlock(udc->lock);
1892 err = usb_ep_clear_halt(
1893 &udc->ci13xxx_ep[num].ep);
1894 spin_lock(udc->lock);
1895 if (err)
1896 break;
1897 }
1898 err = isr_setup_status_phase(mEp);
1899 break;
1900 case USB_REQ_GET_STATUS:
1901 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
1902 type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
1903 type != (USB_DIR_IN|USB_RECIP_INTERFACE))
1904 goto delegate;
1905 if (le16_to_cpu(req.wLength) != 2 ||
1906 le16_to_cpu(req.wValue) != 0)
1907 break;
1908 err = isr_get_status_response(mEp, &req);
1909 break;
1910 case USB_REQ_SET_ADDRESS:
1911 if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
1912 goto delegate;
1913 if (le16_to_cpu(req.wLength) != 0 ||
1914 le16_to_cpu(req.wIndex) != 0)
1915 break;
1916 err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
1917 if (err)
1918 break;
1919 err = isr_setup_status_phase(mEp);
1920 break;
1921 case USB_REQ_SET_FEATURE:
1922 if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1923 le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
1924 goto delegate;
1925 if (req.wLength != 0)
1926 break;
1927 num = le16_to_cpu(req.wIndex);
1928 num &= USB_ENDPOINT_NUMBER_MASK;
1929
1930 spin_unlock(udc->lock);
1931 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
1932 spin_lock(udc->lock);
1933 if (err)
1934 break;
1935 err = isr_setup_status_phase(mEp);
1936 break;
1937 default:
1938 delegate:
1939 if (req.wLength == 0) /* no data phase */
1940 mEp->dir = TX;
1941
1942 spin_unlock(udc->lock);
1943 err = udc->driver->setup(&udc->gadget, &req);
1944 spin_lock(udc->lock);
1945 break;
1946 }
1947
1948 if (err < 0) {
1949 dbg_event(_usb_addr(mEp), "ERROR", err);
1950
1951 spin_unlock(udc->lock);
1952 if (usb_ep_set_halt(&mEp->ep))
1953 err("error: ep_set_halt");
1954 spin_lock(udc->lock);
1955 }
1956 }
1957 }
1958
1959 /******************************************************************************
1960 * ENDPT block
1961 *****************************************************************************/
1962 /**
1963 * ep_enable: configure endpoint, making it usable
1964 *
1965 * Check usb_ep_enable() at "usb_gadget.h" for details
1966 */
1967 static int ep_enable(struct usb_ep *ep,
1968 const struct usb_endpoint_descriptor *desc)
1969 {
1970 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1971 int direction, retval = 0;
1972 unsigned long flags;
1973
1974 trace("%p, %p", ep, desc);
1975
1976 if (ep == NULL || desc == NULL)
1977 return -EINVAL;
1978
1979 spin_lock_irqsave(mEp->lock, flags);
1980
1981 /* only internal SW should enable ctrl endpts */
1982
1983 mEp->desc = desc;
1984
1985 if (!list_empty(&mEp->qh[mEp->dir].queue))
1986 warn("enabling a non-empty endpoint!");
1987
1988 mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
1989 mEp->num = usb_endpoint_num(desc);
1990 mEp->type = usb_endpoint_type(desc);
1991
1992 mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
1993
1994 direction = mEp->dir;
1995 do {
1996 dbg_event(_usb_addr(mEp), "ENABLE", 0);
1997
1998 mEp->qh[mEp->dir].ptr->cap = 0;
1999
2000 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2001 mEp->qh[mEp->dir].ptr->cap |= QH_IOS;
2002 else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
2003 mEp->qh[mEp->dir].ptr->cap &= ~QH_MULT;
2004 else
2005 mEp->qh[mEp->dir].ptr->cap &= ~QH_ZLT;
2006
2007 mEp->qh[mEp->dir].ptr->cap |=
2008 (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
2009 mEp->qh[mEp->dir].ptr->td.next |= TD_TERMINATE; /* needed? */
2010
2011 retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
2012
2013 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2014 mEp->dir = (mEp->dir == TX) ? RX : TX;
2015
2016 } while (mEp->dir != direction);
2017
2018 spin_unlock_irqrestore(mEp->lock, flags);
2019 return retval;
2020 }
2021
2022 /**
2023 * ep_disable: endpoint is no longer usable
2024 *
2025 * Check usb_ep_disable() at "usb_gadget.h" for details
2026 */
2027 static int ep_disable(struct usb_ep *ep)
2028 {
2029 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2030 int direction, retval = 0;
2031 unsigned long flags;
2032
2033 trace("%p", ep);
2034
2035 if (ep == NULL)
2036 return -EINVAL;
2037 else if (mEp->desc == NULL)
2038 return -EBUSY;
2039
2040 spin_lock_irqsave(mEp->lock, flags);
2041
2042 /* only internal SW should disable ctrl endpts */
2043
2044 direction = mEp->dir;
2045 do {
2046 dbg_event(_usb_addr(mEp), "DISABLE", 0);
2047
2048 retval |= _ep_nuke(mEp);
2049 retval |= hw_ep_disable(mEp->num, mEp->dir);
2050
2051 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2052 mEp->dir = (mEp->dir == TX) ? RX : TX;
2053
2054 } while (mEp->dir != direction);
2055
2056 mEp->desc = NULL;
2057
2058 spin_unlock_irqrestore(mEp->lock, flags);
2059 return retval;
2060 }
2061
2062 /**
2063 * ep_alloc_request: allocate a request object to use with this endpoint
2064 *
2065 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
2066 */
2067 static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
2068 {
2069 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2070 struct ci13xxx_req *mReq = NULL;
2071
2072 trace("%p, %i", ep, gfp_flags);
2073
2074 if (ep == NULL) {
2075 err("EINVAL");
2076 return NULL;
2077 }
2078
2079 mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
2080 if (mReq != NULL) {
2081 INIT_LIST_HEAD(&mReq->queue);
2082
2083 mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
2084 &mReq->dma);
2085 if (mReq->ptr == NULL) {
2086 kfree(mReq);
2087 mReq = NULL;
2088 }
2089 }
2090
2091 dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
2092
2093 return (mReq == NULL) ? NULL : &mReq->req;
2094 }
2095
2096 /**
2097 * ep_free_request: frees a request object
2098 *
2099 * Check usb_ep_free_request() at "usb_gadget.h" for details
2100 */
2101 static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
2102 {
2103 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2104 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2105 unsigned long flags;
2106
2107 trace("%p, %p", ep, req);
2108
2109 if (ep == NULL || req == NULL) {
2110 err("EINVAL");
2111 return;
2112 } else if (!list_empty(&mReq->queue)) {
2113 err("EBUSY");
2114 return;
2115 }
2116
2117 spin_lock_irqsave(mEp->lock, flags);
2118
2119 if (mReq->ptr)
2120 dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
2121 kfree(mReq);
2122
2123 dbg_event(_usb_addr(mEp), "FREE", 0);
2124
2125 spin_unlock_irqrestore(mEp->lock, flags);
2126 }
2127
2128 /**
2129 * ep_queue: queues (submits) an I/O request to an endpoint
2130 *
2131 * Check usb_ep_queue()* at usb_gadget.h" for details
2132 */
2133 static int ep_queue(struct usb_ep *ep, struct usb_request *req,
2134 gfp_t __maybe_unused gfp_flags)
2135 {
2136 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2137 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2138 int retval = 0;
2139 unsigned long flags;
2140
2141 trace("%p, %p, %X", ep, req, gfp_flags);
2142
2143 if (ep == NULL || req == NULL || mEp->desc == NULL)
2144 return -EINVAL;
2145
2146 spin_lock_irqsave(mEp->lock, flags);
2147
2148 if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
2149 !list_empty(&mEp->qh[mEp->dir].queue)) {
2150 _ep_nuke(mEp);
2151 retval = -EOVERFLOW;
2152 warn("endpoint ctrl %X nuked", _usb_addr(mEp));
2153 }
2154
2155 /* first nuke then test link, e.g. previous status has not sent */
2156 if (!list_empty(&mReq->queue)) {
2157 retval = -EBUSY;
2158 err("request already in queue");
2159 goto done;
2160 }
2161
2162 if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
2163 req->length = (4 * CI13XXX_PAGE_SIZE);
2164 retval = -EMSGSIZE;
2165 warn("request length truncated");
2166 }
2167
2168 dbg_queue(_usb_addr(mEp), req, retval);
2169
2170 /* push request */
2171 mReq->req.status = -EINPROGRESS;
2172 mReq->req.actual = 0;
2173 list_add_tail(&mReq->queue, &mEp->qh[mEp->dir].queue);
2174
2175 if (list_is_singular(&mEp->qh[mEp->dir].queue))
2176 retval = _hardware_enqueue(mEp, mReq);
2177
2178 if (retval == -EALREADY) {
2179 dbg_event(_usb_addr(mEp), "QUEUE", retval);
2180 retval = 0;
2181 }
2182
2183 done:
2184 spin_unlock_irqrestore(mEp->lock, flags);
2185 return retval;
2186 }
2187
2188 /**
2189 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
2190 *
2191 * Check usb_ep_dequeue() at "usb_gadget.h" for details
2192 */
2193 static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2194 {
2195 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2196 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2197 unsigned long flags;
2198
2199 trace("%p, %p", ep, req);
2200
2201 if (ep == NULL || req == NULL || mEp->desc == NULL ||
2202 list_empty(&mReq->queue) || list_empty(&mEp->qh[mEp->dir].queue))
2203 return -EINVAL;
2204
2205 spin_lock_irqsave(mEp->lock, flags);
2206
2207 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
2208
2209 if (mReq->req.status == -EALREADY)
2210 _hardware_dequeue(mEp, mReq);
2211
2212 /* pop request */
2213 list_del_init(&mReq->queue);
2214 req->status = -ECONNRESET;
2215
2216 if (mReq->req.complete != NULL) {
2217 spin_unlock(mEp->lock);
2218 mReq->req.complete(&mEp->ep, &mReq->req);
2219 spin_lock(mEp->lock);
2220 }
2221
2222 spin_unlock_irqrestore(mEp->lock, flags);
2223 return 0;
2224 }
2225
2226 /**
2227 * ep_set_halt: sets the endpoint halt feature
2228 *
2229 * Check usb_ep_set_halt() at "usb_gadget.h" for details
2230 */
2231 static int ep_set_halt(struct usb_ep *ep, int value)
2232 {
2233 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2234 int direction, retval = 0;
2235 unsigned long flags;
2236
2237 trace("%p, %i", ep, value);
2238
2239 if (ep == NULL || mEp->desc == NULL)
2240 return -EINVAL;
2241
2242 spin_lock_irqsave(mEp->lock, flags);
2243
2244 #ifndef STALL_IN
2245 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
2246 if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
2247 !list_empty(&mEp->qh[mEp->dir].queue)) {
2248 spin_unlock_irqrestore(mEp->lock, flags);
2249 return -EAGAIN;
2250 }
2251 #endif
2252
2253 direction = mEp->dir;
2254 do {
2255 dbg_event(_usb_addr(mEp), "HALT", value);
2256 retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
2257
2258 if (!value)
2259 mEp->wedge = 0;
2260
2261 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2262 mEp->dir = (mEp->dir == TX) ? RX : TX;
2263
2264 } while (mEp->dir != direction);
2265
2266 spin_unlock_irqrestore(mEp->lock, flags);
2267 return retval;
2268 }
2269
2270 /**
2271 * ep_set_wedge: sets the halt feature and ignores clear requests
2272 *
2273 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
2274 */
2275 static int ep_set_wedge(struct usb_ep *ep)
2276 {
2277 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2278 unsigned long flags;
2279
2280 trace("%p", ep);
2281
2282 if (ep == NULL || mEp->desc == NULL)
2283 return -EINVAL;
2284
2285 spin_lock_irqsave(mEp->lock, flags);
2286
2287 dbg_event(_usb_addr(mEp), "WEDGE", 0);
2288 mEp->wedge = 1;
2289
2290 spin_unlock_irqrestore(mEp->lock, flags);
2291
2292 return usb_ep_set_halt(ep);
2293 }
2294
2295 /**
2296 * ep_fifo_flush: flushes contents of a fifo
2297 *
2298 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
2299 */
2300 static void ep_fifo_flush(struct usb_ep *ep)
2301 {
2302 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2303 unsigned long flags;
2304
2305 trace("%p", ep);
2306
2307 if (ep == NULL) {
2308 err("%02X: -EINVAL", _usb_addr(mEp));
2309 return;
2310 }
2311
2312 spin_lock_irqsave(mEp->lock, flags);
2313
2314 dbg_event(_usb_addr(mEp), "FFLUSH", 0);
2315 hw_ep_flush(mEp->num, mEp->dir);
2316
2317 spin_unlock_irqrestore(mEp->lock, flags);
2318 }
2319
2320 /**
2321 * Endpoint-specific part of the API to the USB controller hardware
2322 * Check "usb_gadget.h" for details
2323 */
2324 static const struct usb_ep_ops usb_ep_ops = {
2325 .enable = ep_enable,
2326 .disable = ep_disable,
2327 .alloc_request = ep_alloc_request,
2328 .free_request = ep_free_request,
2329 .queue = ep_queue,
2330 .dequeue = ep_dequeue,
2331 .set_halt = ep_set_halt,
2332 .set_wedge = ep_set_wedge,
2333 .fifo_flush = ep_fifo_flush,
2334 };
2335
2336 /******************************************************************************
2337 * GADGET block
2338 *****************************************************************************/
2339 static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
2340 {
2341 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2342 unsigned long flags;
2343 int gadget_ready = 0;
2344
2345 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
2346 return -EOPNOTSUPP;
2347
2348 spin_lock_irqsave(udc->lock, flags);
2349 udc->vbus_active = is_active;
2350 if (udc->driver)
2351 gadget_ready = 1;
2352 spin_unlock_irqrestore(udc->lock, flags);
2353
2354 if (gadget_ready) {
2355 if (is_active) {
2356 pm_runtime_get_sync(&_gadget->dev);
2357 hw_device_reset(udc);
2358 hw_device_state(udc->ci13xxx_ep[0].qh[RX].dma);
2359 } else {
2360 hw_device_state(0);
2361 if (udc->udc_driver->notify_event)
2362 udc->udc_driver->notify_event(udc,
2363 CI13XXX_CONTROLLER_STOPPED_EVENT);
2364 _gadget_stop_activity(&udc->gadget);
2365 pm_runtime_put_sync(&_gadget->dev);
2366 }
2367 }
2368
2369 return 0;
2370 }
2371
2372 /**
2373 * Device operations part of the API to the USB controller hardware,
2374 * which don't involve endpoints (or i/o)
2375 * Check "usb_gadget.h" for details
2376 */
2377 static const struct usb_gadget_ops usb_gadget_ops = {
2378 .vbus_session = ci13xxx_vbus_session,
2379 };
2380
2381 /**
2382 * usb_gadget_probe_driver: register a gadget driver
2383 * @driver: the driver being registered
2384 * @bind: the driver's bind callback
2385 *
2386 * Check usb_gadget_probe_driver() at <linux/usb/gadget.h> for details.
2387 * Interrupts are enabled here.
2388 */
2389 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
2390 int (*bind)(struct usb_gadget *))
2391 {
2392 struct ci13xxx *udc = _udc;
2393 unsigned long i, k, flags;
2394 int retval = -ENOMEM;
2395
2396 trace("%p", driver);
2397
2398 if (driver == NULL ||
2399 bind == NULL ||
2400 driver->setup == NULL ||
2401 driver->disconnect == NULL ||
2402 driver->suspend == NULL ||
2403 driver->resume == NULL)
2404 return -EINVAL;
2405 else if (udc == NULL)
2406 return -ENODEV;
2407 else if (udc->driver != NULL)
2408 return -EBUSY;
2409
2410 /* alloc resources */
2411 udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
2412 sizeof(struct ci13xxx_qh),
2413 64, CI13XXX_PAGE_SIZE);
2414 if (udc->qh_pool == NULL)
2415 return -ENOMEM;
2416
2417 udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
2418 sizeof(struct ci13xxx_td),
2419 64, CI13XXX_PAGE_SIZE);
2420 if (udc->td_pool == NULL) {
2421 dma_pool_destroy(udc->qh_pool);
2422 udc->qh_pool = NULL;
2423 return -ENOMEM;
2424 }
2425
2426 spin_lock_irqsave(udc->lock, flags);
2427
2428 info("hw_ep_max = %d", hw_ep_max);
2429
2430 udc->driver = driver;
2431 udc->gadget.dev.driver = NULL;
2432
2433 retval = 0;
2434 for (i = 0; i < hw_ep_max; i++) {
2435 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
2436
2437 scnprintf(mEp->name, sizeof(mEp->name), "ep%i", (int)i);
2438
2439 mEp->lock = udc->lock;
2440 mEp->device = &udc->gadget.dev;
2441 mEp->td_pool = udc->td_pool;
2442
2443 mEp->ep.name = mEp->name;
2444 mEp->ep.ops = &usb_ep_ops;
2445 mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
2446
2447 /* this allocation cannot be random */
2448 for (k = RX; k <= TX; k++) {
2449 INIT_LIST_HEAD(&mEp->qh[k].queue);
2450 spin_unlock_irqrestore(udc->lock, flags);
2451 mEp->qh[k].ptr = dma_pool_alloc(udc->qh_pool,
2452 GFP_KERNEL,
2453 &mEp->qh[k].dma);
2454 spin_lock_irqsave(udc->lock, flags);
2455 if (mEp->qh[k].ptr == NULL)
2456 retval = -ENOMEM;
2457 else
2458 memset(mEp->qh[k].ptr, 0,
2459 sizeof(*mEp->qh[k].ptr));
2460 }
2461 if (i == 0)
2462 udc->gadget.ep0 = &mEp->ep;
2463 else
2464 list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
2465 }
2466 if (retval)
2467 goto done;
2468
2469 /* bind gadget */
2470 driver->driver.bus = NULL;
2471 udc->gadget.dev.driver = &driver->driver;
2472
2473 spin_unlock_irqrestore(udc->lock, flags);
2474 retval = bind(&udc->gadget); /* MAY SLEEP */
2475 spin_lock_irqsave(udc->lock, flags);
2476
2477 if (retval) {
2478 udc->gadget.dev.driver = NULL;
2479 goto done;
2480 }
2481
2482 pm_runtime_get_sync(&udc->gadget.dev);
2483 if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
2484 if (udc->vbus_active) {
2485 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
2486 hw_device_reset(udc);
2487 } else {
2488 pm_runtime_put_sync(&udc->gadget.dev);
2489 goto done;
2490 }
2491 }
2492
2493 retval = hw_device_state(udc->ci13xxx_ep[0].qh[RX].dma);
2494 if (retval)
2495 pm_runtime_put_sync(&udc->gadget.dev);
2496
2497 done:
2498 spin_unlock_irqrestore(udc->lock, flags);
2499 if (retval)
2500 usb_gadget_unregister_driver(driver);
2501 return retval;
2502 }
2503 EXPORT_SYMBOL(usb_gadget_probe_driver);
2504
2505 /**
2506 * usb_gadget_unregister_driver: unregister a gadget driver
2507 *
2508 * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
2509 */
2510 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2511 {
2512 struct ci13xxx *udc = _udc;
2513 unsigned long i, k, flags;
2514
2515 trace("%p", driver);
2516
2517 if (driver == NULL ||
2518 driver->unbind == NULL ||
2519 driver->setup == NULL ||
2520 driver->disconnect == NULL ||
2521 driver->suspend == NULL ||
2522 driver->resume == NULL ||
2523 driver != udc->driver)
2524 return -EINVAL;
2525
2526 spin_lock_irqsave(udc->lock, flags);
2527
2528 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
2529 udc->vbus_active) {
2530 hw_device_state(0);
2531 if (udc->udc_driver->notify_event)
2532 udc->udc_driver->notify_event(udc,
2533 CI13XXX_CONTROLLER_STOPPED_EVENT);
2534 _gadget_stop_activity(&udc->gadget);
2535 pm_runtime_put(&udc->gadget.dev);
2536 }
2537
2538 /* unbind gadget */
2539 spin_unlock_irqrestore(udc->lock, flags);
2540 driver->unbind(&udc->gadget); /* MAY SLEEP */
2541 spin_lock_irqsave(udc->lock, flags);
2542
2543 udc->gadget.dev.driver = NULL;
2544
2545 /* free resources */
2546 for (i = 0; i < hw_ep_max; i++) {
2547 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
2548
2549 if (i == 0)
2550 udc->gadget.ep0 = NULL;
2551 else if (!list_empty(&mEp->ep.ep_list))
2552 list_del_init(&mEp->ep.ep_list);
2553
2554 for (k = RX; k <= TX; k++)
2555 if (mEp->qh[k].ptr != NULL)
2556 dma_pool_free(udc->qh_pool,
2557 mEp->qh[k].ptr, mEp->qh[k].dma);
2558 }
2559
2560 udc->driver = NULL;
2561
2562 spin_unlock_irqrestore(udc->lock, flags);
2563
2564 if (udc->td_pool != NULL) {
2565 dma_pool_destroy(udc->td_pool);
2566 udc->td_pool = NULL;
2567 }
2568 if (udc->qh_pool != NULL) {
2569 dma_pool_destroy(udc->qh_pool);
2570 udc->qh_pool = NULL;
2571 }
2572
2573 return 0;
2574 }
2575 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2576
2577 /******************************************************************************
2578 * BUS block
2579 *****************************************************************************/
2580 /**
2581 * udc_irq: global interrupt handler
2582 *
2583 * This function returns IRQ_HANDLED if the IRQ has been handled
2584 * It locks access to registers
2585 */
2586 static irqreturn_t udc_irq(void)
2587 {
2588 struct ci13xxx *udc = _udc;
2589 irqreturn_t retval;
2590 u32 intr;
2591
2592 trace();
2593
2594 if (udc == NULL) {
2595 err("ENODEV");
2596 return IRQ_HANDLED;
2597 }
2598
2599 spin_lock(udc->lock);
2600
2601 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
2602 if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
2603 USBMODE_CM_DEVICE) {
2604 spin_unlock(udc->lock);
2605 return IRQ_NONE;
2606 }
2607 }
2608 intr = hw_test_and_clear_intr_active();
2609 if (intr) {
2610 isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
2611 isr_statistics.hndl.idx &= ISR_MASK;
2612 isr_statistics.hndl.cnt++;
2613
2614 /* order defines priority - do NOT change it */
2615 if (USBi_URI & intr) {
2616 isr_statistics.uri++;
2617 isr_reset_handler(udc);
2618 }
2619 if (USBi_PCI & intr) {
2620 isr_statistics.pci++;
2621 udc->gadget.speed = hw_port_is_high_speed() ?
2622 USB_SPEED_HIGH : USB_SPEED_FULL;
2623 }
2624 if (USBi_UEI & intr)
2625 isr_statistics.uei++;
2626 if (USBi_UI & intr) {
2627 isr_statistics.ui++;
2628 isr_tr_complete_handler(udc);
2629 }
2630 if (USBi_SLI & intr)
2631 isr_statistics.sli++;
2632 retval = IRQ_HANDLED;
2633 } else {
2634 isr_statistics.none++;
2635 retval = IRQ_NONE;
2636 }
2637 spin_unlock(udc->lock);
2638
2639 return retval;
2640 }
2641
2642 /**
2643 * udc_release: driver release function
2644 * @dev: device
2645 *
2646 * Currently does nothing
2647 */
2648 static void udc_release(struct device *dev)
2649 {
2650 trace("%p", dev);
2651
2652 if (dev == NULL)
2653 err("EINVAL");
2654 }
2655
2656 /**
2657 * udc_probe: parent probe must call this to initialize UDC
2658 * @dev: parent device
2659 * @regs: registers base address
2660 * @name: driver name
2661 *
2662 * This function returns an error code
2663 * No interrupts active, the IRQ has not been requested yet
2664 * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
2665 */
2666 static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
2667 void __iomem *regs)
2668 {
2669 struct ci13xxx *udc;
2670 int retval = 0;
2671
2672 trace("%p, %p, %p", dev, regs, name);
2673
2674 if (dev == NULL || regs == NULL || driver == NULL ||
2675 driver->name == NULL)
2676 return -EINVAL;
2677
2678 udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
2679 if (udc == NULL)
2680 return -ENOMEM;
2681
2682 udc->lock = &udc_lock;
2683 udc->regs = regs;
2684 udc->udc_driver = driver;
2685
2686 udc->gadget.ops = &usb_gadget_ops;
2687 udc->gadget.speed = USB_SPEED_UNKNOWN;
2688 udc->gadget.is_dualspeed = 1;
2689 udc->gadget.is_otg = 0;
2690 udc->gadget.name = driver->name;
2691
2692 INIT_LIST_HEAD(&udc->gadget.ep_list);
2693 udc->gadget.ep0 = NULL;
2694
2695 dev_set_name(&udc->gadget.dev, "gadget");
2696 udc->gadget.dev.dma_mask = dev->dma_mask;
2697 udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
2698 udc->gadget.dev.parent = dev;
2699 udc->gadget.dev.release = udc_release;
2700
2701 retval = hw_device_init(regs);
2702 if (retval < 0)
2703 goto free_udc;
2704
2705 udc->transceiver = otg_get_transceiver();
2706
2707 if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
2708 if (udc->transceiver == NULL) {
2709 retval = -ENODEV;
2710 goto free_udc;
2711 }
2712 }
2713
2714 if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
2715 retval = hw_device_reset(udc);
2716 if (retval)
2717 goto put_transceiver;
2718 }
2719
2720 retval = device_register(&udc->gadget.dev);
2721 if (retval) {
2722 put_device(&udc->gadget.dev);
2723 goto put_transceiver;
2724 }
2725
2726 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2727 retval = dbg_create_files(&udc->gadget.dev);
2728 #endif
2729 if (retval)
2730 goto unreg_device;
2731
2732 if (udc->transceiver) {
2733 retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
2734 if (retval)
2735 goto remove_dbg;
2736 }
2737 pm_runtime_no_callbacks(&udc->gadget.dev);
2738 pm_runtime_enable(&udc->gadget.dev);
2739
2740 _udc = udc;
2741 return retval;
2742
2743 err("error = %i", retval);
2744 remove_dbg:
2745 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2746 dbg_remove_files(&udc->gadget.dev);
2747 #endif
2748 unreg_device:
2749 device_unregister(&udc->gadget.dev);
2750 put_transceiver:
2751 if (udc->transceiver)
2752 otg_put_transceiver(udc->transceiver);
2753 free_udc:
2754 kfree(udc);
2755 _udc = NULL;
2756 return retval;
2757 }
2758
2759 /**
2760 * udc_remove: parent remove must call this to remove UDC
2761 *
2762 * No interrupts active, the IRQ has been released
2763 */
2764 static void udc_remove(void)
2765 {
2766 struct ci13xxx *udc = _udc;
2767
2768 if (udc == NULL) {
2769 err("EINVAL");
2770 return;
2771 }
2772
2773 if (udc->transceiver) {
2774 otg_set_peripheral(udc->transceiver, &udc->gadget);
2775 otg_put_transceiver(udc->transceiver);
2776 }
2777 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2778 dbg_remove_files(&udc->gadget.dev);
2779 #endif
2780 device_unregister(&udc->gadget.dev);
2781
2782 kfree(udc);
2783 _udc = NULL;
2784 }
linux-next