2 * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Description: MIPS USB IP core family device controller
13 * Structures, registers and logging macros
19 /******************************************************************************
21 *****************************************************************************/
22 #define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
23 #define ENDPT_MAX (16)
24 #define CTRL_PAYLOAD_MAX (64)
25 #define RX (0) /* similar to USB_DIR_OUT but can be used as an index */
26 #define TX (1) /* similar to USB_DIR_IN but can be used as an index */
28 /******************************************************************************
30 *****************************************************************************/
31 /* DMA layout of transfer descriptors */
35 #define TD_TERMINATE BIT(0)
38 #define TD_STATUS (0x00FFUL << 0)
39 #define TD_STATUS_TR_ERR BIT(3)
40 #define TD_STATUS_DT_ERR BIT(5)
41 #define TD_STATUS_HALTED BIT(6)
42 #define TD_STATUS_ACTIVE BIT(7)
43 #define TD_MULTO (0x0003UL << 10)
44 #define TD_IOC BIT(15)
45 #define TD_TOTAL_BYTES (0x7FFFUL << 16)
48 #define TD_CURR_OFFSET (0x0FFFUL << 0)
49 #define TD_FRAME_NUM (0x07FFUL << 0)
50 #define TD_RESERVED_MASK (0x0FFFUL << 0)
51 } __attribute__ ((packed
));
53 /* DMA layout of queue heads */
57 #define QH_IOS BIT(15)
58 #define QH_MAX_PKT (0x07FFUL << 16)
59 #define QH_ZLT BIT(29)
60 #define QH_MULT (0x0003UL << 30)
67 struct usb_ctrlrequest setup
;
68 } __attribute__ ((packed
));
70 /* Extension of usb_request */
72 struct usb_request req
;
74 struct list_head queue
;
75 struct ci13xxx_td
*ptr
;
79 /* Extension of usb_ep */
82 const struct usb_endpoint_descriptor
*desc
;
88 struct list_head queue
;
89 struct ci13xxx_qh
*ptr
;
92 struct usb_request
*status
;
95 /* global resources */
97 struct device
*device
;
98 struct dma_pool
*td_pool
;
102 struct ci13xxx_udc_driver
{
105 #define CI13XXX_REGS_SHARED BIT(0)
106 #define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
107 #define CI13XXX_PULLUP_ON_VBUS BIT(2)
108 #define CI13XXX_DISABLE_STREAMING BIT(3)
110 #define CI13XXX_CONTROLLER_RESET_EVENT 0
111 #define CI13XXX_CONTROLLER_STOPPED_EVENT 1
112 void (*notify_event
) (struct ci13xxx
*udc
, unsigned event
);
115 /* CI13XXX UDC descriptor & global resources */
117 spinlock_t
*lock
; /* ctrl register bank access */
118 void __iomem
*regs
; /* registers address space */
120 struct dma_pool
*qh_pool
; /* DMA pool for queue heads */
121 struct dma_pool
*td_pool
; /* DMA pool for transfer descs */
123 struct usb_gadget gadget
; /* USB slave device */
124 struct ci13xxx_ep ci13xxx_ep
[ENDPT_MAX
]; /* extended endpts */
126 struct usb_gadget_driver
*driver
; /* 3rd party gadget driver */
127 struct ci13xxx_udc_driver
*udc_driver
; /* device controller driver */
128 int vbus_active
; /* is VBUS active */
129 struct otg_transceiver
*transceiver
; /* Transceiver struct */
132 /******************************************************************************
134 *****************************************************************************/
136 #define REG_BITS (32)
139 #define HCCPARAMS_LEN BIT(17)
142 #define DCCPARAMS_DEN (0x1F << 0)
143 #define DCCPARAMS_DC BIT(7)
146 #define TESTMODE_FORCE BIT(0)
149 #define USBCMD_RS BIT(0)
150 #define USBCMD_RST BIT(1)
151 #define USBCMD_SUTW BIT(13)
153 /* USBSTS & USBINTR */
154 #define USBi_UI BIT(0)
155 #define USBi_UEI BIT(1)
156 #define USBi_PCI BIT(2)
157 #define USBi_URI BIT(6)
158 #define USBi_SLI BIT(8)
161 #define DEVICEADDR_USBADRA BIT(24)
162 #define DEVICEADDR_USBADR (0x7FUL << 25)
165 #define PORTSC_SUSP BIT(7)
166 #define PORTSC_HSP BIT(9)
167 #define PORTSC_PTC (0x0FUL << 16)
170 #define DEVLC_PSPD (0x03UL << 25)
171 #define DEVLC_PSPD_HS (0x02UL << 25)
174 #define USBMODE_CM (0x03UL << 0)
175 #define USBMODE_CM_IDLE (0x00UL << 0)
176 #define USBMODE_CM_DEVICE (0x02UL << 0)
177 #define USBMODE_CM_HOST (0x03UL << 0)
178 #define USBMODE_SLOM BIT(3)
179 #define USBMODE_SDIS BIT(4)
182 #define ENDPTCTRL_RXS BIT(0)
183 #define ENDPTCTRL_RXT (0x03UL << 2)
184 #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
185 #define ENDPTCTRL_RXE BIT(7)
186 #define ENDPTCTRL_TXS BIT(16)
187 #define ENDPTCTRL_TXT (0x03UL << 18)
188 #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
189 #define ENDPTCTRL_TXE BIT(23)
191 /******************************************************************************
193 *****************************************************************************/
194 #define ci13xxx_printk(level, format, args...) \
197 printk(level "[%s] " format "\n", __func__, ## args); \
199 dev_printk(level, _udc->gadget.dev.parent, \
200 "[%s] " format "\n", __func__, ## args); \
203 #define err(format, args...) ci13xxx_printk(KERN_ERR, format, ## args)
204 #define warn(format, args...) ci13xxx_printk(KERN_WARNING, format, ## args)
205 #define info(format, args...) ci13xxx_printk(KERN_INFO, format, ## args)
208 #define trace(format, args...) ci13xxx_printk(KERN_DEBUG, format, ## args)
209 #define dbg_trace(format, args...) dev_dbg(dev, format, ##args)
211 #define trace(format, args...) do {} while (0)
212 #define dbg_trace(format, args...) do {} while (0)
215 #endif /* _CI13XXX_h_ */