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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / usb / host / ehci-sched.c
blobaa46f57f9ec8f31cbe6153dade5162cccf734806
1 /*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 /* this file is part of ehci-hcd.c */
21
22 /*-------------------------------------------------------------------------*/
23
24 /*
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
27 *
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
31 *
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
35 */
36
37 static int ehci_get_frame (struct usb_hcd *hcd);
38
39 /*-------------------------------------------------------------------------*/
40
41 /*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
49 {
50 switch (hc32_to_cpu(ehci, tag)) {
51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
60 }
61 }
62
63 static __hc32 *
64 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
65 __hc32 tag)
66 {
67 switch (hc32_to_cpu(ehci, tag)) {
68 /* our ehci_shadow.qh is actually software part */
69 case Q_TYPE_QH:
70 return &periodic->qh->hw->hw_next;
71 /* others are hw parts */
72 default:
73 return periodic->hw_next;
74 }
75 }
76
77 /* caller must hold ehci->lock */
78 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
79 {
80 union ehci_shadow *prev_p = &ehci->pshadow[frame];
81 __hc32 *hw_p = &ehci->periodic[frame];
82 union ehci_shadow here = *prev_p;
83
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here.ptr && here.ptr != ptr) {
86 prev_p = periodic_next_shadow(ehci, prev_p,
87 Q_NEXT_TYPE(ehci, *hw_p));
88 hw_p = shadow_next_periodic(ehci, &here,
89 Q_NEXT_TYPE(ehci, *hw_p));
90 here = *prev_p;
91 }
92 /* an interrupt entry (at list end) could have been shared */
93 if (!here.ptr)
94 return;
95
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
98 */
99 *prev_p = *periodic_next_shadow(ehci, &here,
100 Q_NEXT_TYPE(ehci, *hw_p));
101
102 if (!ehci->use_dummy_qh ||
103 *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
104 != EHCI_LIST_END(ehci))
105 *hw_p = *shadow_next_periodic(ehci, &here,
106 Q_NEXT_TYPE(ehci, *hw_p));
107 else
108 *hw_p = ehci->dummy->qh_dma;
109 }
110
111 /* how many of the uframe's 125 usecs are allocated? */
112 static unsigned short
113 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
114 {
115 __hc32 *hw_p = &ehci->periodic [frame];
116 union ehci_shadow *q = &ehci->pshadow [frame];
117 unsigned usecs = 0;
118 struct ehci_qh_hw *hw;
119
120 while (q->ptr) {
121 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
122 case Q_TYPE_QH:
123 hw = q->qh->hw;
124 /* is it in the S-mask? */
125 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
126 usecs += q->qh->usecs;
127 /* ... or C-mask? */
128 if (hw->hw_info2 & cpu_to_hc32(ehci,
129 1 << (8 + uframe)))
130 usecs += q->qh->c_usecs;
131 hw_p = &hw->hw_next;
132 q = &q->qh->qh_next;
133 break;
134 // case Q_TYPE_FSTN:
135 default:
136 /* for "save place" FSTNs, count the relevant INTR
137 * bandwidth from the previous frame
138 */
139 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
140 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
141 }
142 hw_p = &q->fstn->hw_next;
143 q = &q->fstn->fstn_next;
144 break;
145 case Q_TYPE_ITD:
146 if (q->itd->hw_transaction[uframe])
147 usecs += q->itd->stream->usecs;
148 hw_p = &q->itd->hw_next;
149 q = &q->itd->itd_next;
150 break;
151 case Q_TYPE_SITD:
152 /* is it in the S-mask? (count SPLIT, DATA) */
153 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
154 1 << uframe)) {
155 if (q->sitd->hw_fullspeed_ep &
156 cpu_to_hc32(ehci, 1<<31))
157 usecs += q->sitd->stream->usecs;
158 else /* worst case for OUT start-split */
159 usecs += HS_USECS_ISO (188);
160 }
161
162 /* ... C-mask? (count CSPLIT, DATA) */
163 if (q->sitd->hw_uframe &
164 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
165 /* worst case for IN complete-split */
166 usecs += q->sitd->stream->c_usecs;
167 }
168
169 hw_p = &q->sitd->hw_next;
170 q = &q->sitd->sitd_next;
171 break;
172 }
173 }
174 #ifdef DEBUG
175 if (usecs > 100)
176 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
177 frame * 8 + uframe, usecs);
178 #endif
179 return usecs;
180 }
181
182 /*-------------------------------------------------------------------------*/
183
184 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
185 {
186 if (!dev1->tt || !dev2->tt)
187 return 0;
188 if (dev1->tt != dev2->tt)
189 return 0;
190 if (dev1->tt->multi)
191 return dev1->ttport == dev2->ttport;
192 else
193 return 1;
194 }
195
196 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
197
198 /* Which uframe does the low/fullspeed transfer start in?
199 *
200 * The parameter is the mask of ssplits in "H-frame" terms
201 * and this returns the transfer start uframe in "B-frame" terms,
202 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
203 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
204 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
205 */
206 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
207 {
208 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
209 if (!smask) {
210 ehci_err(ehci, "invalid empty smask!\n");
211 /* uframe 7 can't have bw so this will indicate failure */
212 return 7;
213 }
214 return ffs(smask) - 1;
215 }
216
217 static const unsigned char
218 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
219
220 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
221 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
222 {
223 int i;
224 for (i=0; i<7; i++) {
225 if (max_tt_usecs[i] < tt_usecs[i]) {
226 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
227 tt_usecs[i] = max_tt_usecs[i];
228 }
229 }
230 }
231
232 /* How many of the tt's periodic downstream 1000 usecs are allocated?
233 *
234 * While this measures the bandwidth in terms of usecs/uframe,
235 * the low/fullspeed bus has no notion of uframes, so any particular
236 * low/fullspeed transfer can "carry over" from one uframe to the next,
237 * since the TT just performs downstream transfers in sequence.
238 *
239 * For example two separate 100 usec transfers can start in the same uframe,
240 * and the second one would "carry over" 75 usecs into the next uframe.
241 */
242 static void
243 periodic_tt_usecs (
244 struct ehci_hcd *ehci,
245 struct usb_device *dev,
246 unsigned frame,
247 unsigned short tt_usecs[8]
248 )
249 {
250 __hc32 *hw_p = &ehci->periodic [frame];
251 union ehci_shadow *q = &ehci->pshadow [frame];
252 unsigned char uf;
253
254 memset(tt_usecs, 0, 16);
255
256 while (q->ptr) {
257 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
258 case Q_TYPE_ITD:
259 hw_p = &q->itd->hw_next;
260 q = &q->itd->itd_next;
261 continue;
262 case Q_TYPE_QH:
263 if (same_tt(dev, q->qh->dev)) {
264 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
265 tt_usecs[uf] += q->qh->tt_usecs;
266 }
267 hw_p = &q->qh->hw->hw_next;
268 q = &q->qh->qh_next;
269 continue;
270 case Q_TYPE_SITD:
271 if (same_tt(dev, q->sitd->urb->dev)) {
272 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
273 tt_usecs[uf] += q->sitd->stream->tt_usecs;
274 }
275 hw_p = &q->sitd->hw_next;
276 q = &q->sitd->sitd_next;
277 continue;
278 // case Q_TYPE_FSTN:
279 default:
280 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
281 frame);
282 hw_p = &q->fstn->hw_next;
283 q = &q->fstn->fstn_next;
284 }
285 }
286
287 carryover_tt_bandwidth(tt_usecs);
288
289 if (max_tt_usecs[7] < tt_usecs[7])
290 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
291 frame, tt_usecs[7] - max_tt_usecs[7]);
292 }
293
294 /*
295 * Return true if the device's tt's downstream bus is available for a
296 * periodic transfer of the specified length (usecs), starting at the
297 * specified frame/uframe. Note that (as summarized in section 11.19
298 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
299 * uframe.
300 *
301 * The uframe parameter is when the fullspeed/lowspeed transfer
302 * should be executed in "B-frame" terms, which is the same as the
303 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
304 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
305 * See the EHCI spec sec 4.5 and fig 4.7.
306 *
307 * This checks if the full/lowspeed bus, at the specified starting uframe,
308 * has the specified bandwidth available, according to rules listed
309 * in USB 2.0 spec section 11.18.1 fig 11-60.
310 *
311 * This does not check if the transfer would exceed the max ssplit
312 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
313 * since proper scheduling limits ssplits to less than 16 per uframe.
314 */
315 static int tt_available (
316 struct ehci_hcd *ehci,
317 unsigned period,
318 struct usb_device *dev,
319 unsigned frame,
320 unsigned uframe,
321 u16 usecs
322 )
323 {
324 if ((period == 0) || (uframe >= 7)) /* error */
325 return 0;
326
327 for (; frame < ehci->periodic_size; frame += period) {
328 unsigned short tt_usecs[8];
329
330 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
331
332 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
333 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
334 frame, usecs, uframe,
335 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
336 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
337
338 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
339 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
340 frame, uframe);
341 return 0;
342 }
343
344 /* special case for isoc transfers larger than 125us:
345 * the first and each subsequent fully used uframe
346 * must be empty, so as to not illegally delay
347 * already scheduled transactions
348 */
349 if (125 < usecs) {
350 int ufs = (usecs / 125);
351 int i;
352 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
353 if (0 < tt_usecs[i]) {
354 ehci_vdbg(ehci,
355 "multi-uframe xfer can't fit "
356 "in frame %d uframe %d\n",
357 frame, i);
358 return 0;
359 }
360 }
361
362 tt_usecs[uframe] += usecs;
363
364 carryover_tt_bandwidth(tt_usecs);
365
366 /* fail if the carryover pushed bw past the last uframe's limit */
367 if (max_tt_usecs[7] < tt_usecs[7]) {
368 ehci_vdbg(ehci,
369 "tt unavailable usecs %d frame %d uframe %d\n",
370 usecs, frame, uframe);
371 return 0;
372 }
373 }
374
375 return 1;
376 }
377
378 #else
379
380 /* return true iff the device's transaction translator is available
381 * for a periodic transfer starting at the specified frame, using
382 * all the uframes in the mask.
383 */
384 static int tt_no_collision (
385 struct ehci_hcd *ehci,
386 unsigned period,
387 struct usb_device *dev,
388 unsigned frame,
389 u32 uf_mask
390 )
391 {
392 if (period == 0) /* error */
393 return 0;
394
395 /* note bandwidth wastage: split never follows csplit
396 * (different dev or endpoint) until the next uframe.
397 * calling convention doesn't make that distinction.
398 */
399 for (; frame < ehci->periodic_size; frame += period) {
400 union ehci_shadow here;
401 __hc32 type;
402 struct ehci_qh_hw *hw;
403
404 here = ehci->pshadow [frame];
405 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
406 while (here.ptr) {
407 switch (hc32_to_cpu(ehci, type)) {
408 case Q_TYPE_ITD:
409 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
410 here = here.itd->itd_next;
411 continue;
412 case Q_TYPE_QH:
413 hw = here.qh->hw;
414 if (same_tt (dev, here.qh->dev)) {
415 u32 mask;
416
417 mask = hc32_to_cpu(ehci,
418 hw->hw_info2);
419 /* "knows" no gap is needed */
420 mask |= mask >> 8;
421 if (mask & uf_mask)
422 break;
423 }
424 type = Q_NEXT_TYPE(ehci, hw->hw_next);
425 here = here.qh->qh_next;
426 continue;
427 case Q_TYPE_SITD:
428 if (same_tt (dev, here.sitd->urb->dev)) {
429 u16 mask;
430
431 mask = hc32_to_cpu(ehci, here.sitd
432 ->hw_uframe);
433 /* FIXME assumes no gap for IN! */
434 mask |= mask >> 8;
435 if (mask & uf_mask)
436 break;
437 }
438 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
439 here = here.sitd->sitd_next;
440 continue;
441 // case Q_TYPE_FSTN:
442 default:
443 ehci_dbg (ehci,
444 "periodic frame %d bogus type %d\n",
445 frame, type);
446 }
447
448 /* collision or error */
449 return 0;
450 }
451 }
452
453 /* no collision */
454 return 1;
455 }
456
457 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
458
459 /*-------------------------------------------------------------------------*/
460
461 static int enable_periodic (struct ehci_hcd *ehci)
462 {
463 u32 cmd;
464 int status;
465
466 if (ehci->periodic_sched++)
467 return 0;
468
469 /* did clearing PSE did take effect yet?
470 * takes effect only at frame boundaries...
471 */
472 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
473 STS_PSS, 0, 9 * 125);
474 if (status)
475 return status;
476
477 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
478 ehci_writel(ehci, cmd, &ehci->regs->command);
479 /* posted write ... PSS happens later */
480 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
481
482 /* make sure ehci_work scans these */
483 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
484 % (ehci->periodic_size << 3);
485 if (unlikely(ehci->broken_periodic))
486 ehci->last_periodic_enable = ktime_get_real();
487 return 0;
488 }
489
490 static int disable_periodic (struct ehci_hcd *ehci)
491 {
492 u32 cmd;
493 int status;
494
495 if (--ehci->periodic_sched)
496 return 0;
497
498 if (unlikely(ehci->broken_periodic)) {
499 /* delay experimentally determined */
500 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
501 ktime_t now = ktime_get_real();
502 s64 delay = ktime_us_delta(safe, now);
503
504 if (unlikely(delay > 0))
505 udelay(delay);
506 }
507
508 /* did setting PSE not take effect yet?
509 * takes effect only at frame boundaries...
510 */
511 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
512 STS_PSS, STS_PSS, 9 * 125);
513 if (status)
514 return status;
515
516 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
517 ehci_writel(ehci, cmd, &ehci->regs->command);
518 /* posted write ... */
519
520 free_cached_lists(ehci);
521
522 ehci->next_uframe = -1;
523 return 0;
524 }
525
526 /*-------------------------------------------------------------------------*/
527
528 /* periodic schedule slots have iso tds (normal or split) first, then a
529 * sparse tree for active interrupt transfers.
530 *
531 * this just links in a qh; caller guarantees uframe masks are set right.
532 * no FSTN support (yet; ehci 0.96+)
533 */
534 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
535 {
536 unsigned i;
537 unsigned period = qh->period;
538
539 dev_dbg (&qh->dev->dev,
540 "link qh%d-%04x/%p start %d [%d/%d us]\n",
541 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
542 & (QH_CMASK | QH_SMASK),
543 qh, qh->start, qh->usecs, qh->c_usecs);
544
545 /* high bandwidth, or otherwise every microframe */
546 if (period == 0)
547 period = 1;
548
549 for (i = qh->start; i < ehci->periodic_size; i += period) {
550 union ehci_shadow *prev = &ehci->pshadow[i];
551 __hc32 *hw_p = &ehci->periodic[i];
552 union ehci_shadow here = *prev;
553 __hc32 type = 0;
554
555 /* skip the iso nodes at list head */
556 while (here.ptr) {
557 type = Q_NEXT_TYPE(ehci, *hw_p);
558 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
559 break;
560 prev = periodic_next_shadow(ehci, prev, type);
561 hw_p = shadow_next_periodic(ehci, &here, type);
562 here = *prev;
563 }
564
565 /* sorting each branch by period (slow-->fast)
566 * enables sharing interior tree nodes
567 */
568 while (here.ptr && qh != here.qh) {
569 if (qh->period > here.qh->period)
570 break;
571 prev = &here.qh->qh_next;
572 hw_p = &here.qh->hw->hw_next;
573 here = *prev;
574 }
575 /* link in this qh, unless some earlier pass did that */
576 if (qh != here.qh) {
577 qh->qh_next = here;
578 if (here.qh)
579 qh->hw->hw_next = *hw_p;
580 wmb ();
581 prev->qh = qh;
582 *hw_p = QH_NEXT (ehci, qh->qh_dma);
583 }
584 }
585 qh->qh_state = QH_STATE_LINKED;
586 qh->xacterrs = 0;
587 qh_get (qh);
588
589 /* update per-qh bandwidth for usbfs */
590 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
591 ? ((qh->usecs + qh->c_usecs) / qh->period)
592 : (qh->usecs * 8);
593
594 /* maybe enable periodic schedule processing */
595 return enable_periodic(ehci);
596 }
597
598 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
599 {
600 unsigned i;
601 unsigned period;
602
603 // FIXME:
604 // IF this isn't high speed
605 // and this qh is active in the current uframe
606 // (and overlay token SplitXstate is false?)
607 // THEN
608 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
609
610 /* high bandwidth, or otherwise part of every microframe */
611 if ((period = qh->period) == 0)
612 period = 1;
613
614 for (i = qh->start; i < ehci->periodic_size; i += period)
615 periodic_unlink (ehci, i, qh);
616
617 /* update per-qh bandwidth for usbfs */
618 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
619 ? ((qh->usecs + qh->c_usecs) / qh->period)
620 : (qh->usecs * 8);
621
622 dev_dbg (&qh->dev->dev,
623 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
624 qh->period,
625 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
626 qh, qh->start, qh->usecs, qh->c_usecs);
627
628 /* qh->qh_next still "live" to HC */
629 qh->qh_state = QH_STATE_UNLINK;
630 qh->qh_next.ptr = NULL;
631 qh_put (qh);
632
633 /* maybe turn off periodic schedule */
634 return disable_periodic(ehci);
635 }
636
637 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
638 {
639 unsigned wait;
640 struct ehci_qh_hw *hw = qh->hw;
641 int rc;
642
643 /* If the QH isn't linked then there's nothing we can do
644 * unless we were called during a giveback, in which case
645 * qh_completions() has to deal with it.
646 */
647 if (qh->qh_state != QH_STATE_LINKED) {
648 if (qh->qh_state == QH_STATE_COMPLETING)
649 qh->needs_rescan = 1;
650 return;
651 }
652
653 qh_unlink_periodic (ehci, qh);
654
655 /* simple/paranoid: always delay, expecting the HC needs to read
656 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
657 * expect khubd to clean up after any CSPLITs we won't issue.
658 * active high speed queues may need bigger delays...
659 */
660 if (list_empty (&qh->qtd_list)
661 || (cpu_to_hc32(ehci, QH_CMASK)
662 & hw->hw_info2) != 0)
663 wait = 2;
664 else
665 wait = 55; /* worst case: 3 * 1024 */
666
667 udelay (wait);
668 qh->qh_state = QH_STATE_IDLE;
669 hw->hw_next = EHCI_LIST_END(ehci);
670 wmb ();
671
672 qh_completions(ehci, qh);
673
674 /* reschedule QH iff another request is queued */
675 if (!list_empty(&qh->qtd_list) &&
676 HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
677 rc = qh_schedule(ehci, qh);
678
679 /* An error here likely indicates handshake failure
680 * or no space left in the schedule. Neither fault
681 * should happen often ...
682 *
683 * FIXME kill the now-dysfunctional queued urbs
684 */
685 if (rc != 0)
686 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
687 qh, rc);
688 }
689 }
690
691 /*-------------------------------------------------------------------------*/
692
693 static int check_period (
694 struct ehci_hcd *ehci,
695 unsigned frame,
696 unsigned uframe,
697 unsigned period,
698 unsigned usecs
699 ) {
700 int claimed;
701
702 /* complete split running into next frame?
703 * given FSTN support, we could sometimes check...
704 */
705 if (uframe >= 8)
706 return 0;
707
708 /*
709 * 80% periodic == 100 usec/uframe available
710 * convert "usecs we need" to "max already claimed"
711 */
712 usecs = 100 - usecs;
713
714 /* we "know" 2 and 4 uframe intervals were rejected; so
715 * for period 0, check _every_ microframe in the schedule.
716 */
717 if (unlikely (period == 0)) {
718 do {
719 for (uframe = 0; uframe < 7; uframe++) {
720 claimed = periodic_usecs (ehci, frame, uframe);
721 if (claimed > usecs)
722 return 0;
723 }
724 } while ((frame += 1) < ehci->periodic_size);
725
726 /* just check the specified uframe, at that period */
727 } else {
728 do {
729 claimed = periodic_usecs (ehci, frame, uframe);
730 if (claimed > usecs)
731 return 0;
732 } while ((frame += period) < ehci->periodic_size);
733 }
734
735 // success!
736 return 1;
737 }
738
739 static int check_intr_schedule (
740 struct ehci_hcd *ehci,
741 unsigned frame,
742 unsigned uframe,
743 const struct ehci_qh *qh,
744 __hc32 *c_maskp
745 )
746 {
747 int retval = -ENOSPC;
748 u8 mask = 0;
749
750 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
751 goto done;
752
753 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
754 goto done;
755 if (!qh->c_usecs) {
756 retval = 0;
757 *c_maskp = 0;
758 goto done;
759 }
760
761 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
762 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
763 qh->tt_usecs)) {
764 unsigned i;
765
766 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
767 for (i=uframe+1; i<8 && i<uframe+4; i++)
768 if (!check_period (ehci, frame, i,
769 qh->period, qh->c_usecs))
770 goto done;
771 else
772 mask |= 1 << i;
773
774 retval = 0;
775
776 *c_maskp = cpu_to_hc32(ehci, mask << 8);
777 }
778 #else
779 /* Make sure this tt's buffer is also available for CSPLITs.
780 * We pessimize a bit; probably the typical full speed case
781 * doesn't need the second CSPLIT.
782 *
783 * NOTE: both SPLIT and CSPLIT could be checked in just
784 * one smart pass...
785 */
786 mask = 0x03 << (uframe + qh->gap_uf);
787 *c_maskp = cpu_to_hc32(ehci, mask << 8);
788
789 mask |= 1 << uframe;
790 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
791 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
792 qh->period, qh->c_usecs))
793 goto done;
794 if (!check_period (ehci, frame, uframe + qh->gap_uf,
795 qh->period, qh->c_usecs))
796 goto done;
797 retval = 0;
798 }
799 #endif
800 done:
801 return retval;
802 }
803
804 /* "first fit" scheduling policy used the first time through,
805 * or when the previous schedule slot can't be re-used.
806 */
807 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
808 {
809 int status;
810 unsigned uframe;
811 __hc32 c_mask;
812 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
813 struct ehci_qh_hw *hw = qh->hw;
814
815 qh_refresh(ehci, qh);
816 hw->hw_next = EHCI_LIST_END(ehci);
817 frame = qh->start;
818
819 /* reuse the previous schedule slots, if we can */
820 if (frame < qh->period) {
821 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
822 status = check_intr_schedule (ehci, frame, --uframe,
823 qh, &c_mask);
824 } else {
825 uframe = 0;
826 c_mask = 0;
827 status = -ENOSPC;
828 }
829
830 /* else scan the schedule to find a group of slots such that all
831 * uframes have enough periodic bandwidth available.
832 */
833 if (status) {
834 /* "normal" case, uframing flexible except with splits */
835 if (qh->period) {
836 int i;
837
838 for (i = qh->period; status && i > 0; --i) {
839 frame = ++ehci->random_frame % qh->period;
840 for (uframe = 0; uframe < 8; uframe++) {
841 status = check_intr_schedule (ehci,
842 frame, uframe, qh,
843 &c_mask);
844 if (status == 0)
845 break;
846 }
847 }
848
849 /* qh->period == 0 means every uframe */
850 } else {
851 frame = 0;
852 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
853 }
854 if (status)
855 goto done;
856 qh->start = frame;
857
858 /* reset S-frame and (maybe) C-frame masks */
859 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
860 hw->hw_info2 |= qh->period
861 ? cpu_to_hc32(ehci, 1 << uframe)
862 : cpu_to_hc32(ehci, QH_SMASK);
863 hw->hw_info2 |= c_mask;
864 } else
865 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
866
867 /* stuff into the periodic schedule */
868 status = qh_link_periodic (ehci, qh);
869 done:
870 return status;
871 }
872
873 static int intr_submit (
874 struct ehci_hcd *ehci,
875 struct urb *urb,
876 struct list_head *qtd_list,
877 gfp_t mem_flags
878 ) {
879 unsigned epnum;
880 unsigned long flags;
881 struct ehci_qh *qh;
882 int status;
883 struct list_head empty;
884
885 /* get endpoint and transfer/schedule data */
886 epnum = urb->ep->desc.bEndpointAddress;
887
888 spin_lock_irqsave (&ehci->lock, flags);
889
890 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
891 status = -ESHUTDOWN;
892 goto done_not_linked;
893 }
894 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
895 if (unlikely(status))
896 goto done_not_linked;
897
898 /* get qh and force any scheduling errors */
899 INIT_LIST_HEAD (&empty);
900 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
901 if (qh == NULL) {
902 status = -ENOMEM;
903 goto done;
904 }
905 if (qh->qh_state == QH_STATE_IDLE) {
906 if ((status = qh_schedule (ehci, qh)) != 0)
907 goto done;
908 }
909
910 /* then queue the urb's tds to the qh */
911 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
912 BUG_ON (qh == NULL);
913
914 /* ... update usbfs periodic stats */
915 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
916
917 done:
918 if (unlikely(status))
919 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
920 done_not_linked:
921 spin_unlock_irqrestore (&ehci->lock, flags);
922 if (status)
923 qtd_list_free (ehci, urb, qtd_list);
924
925 return status;
926 }
927
928 /*-------------------------------------------------------------------------*/
929
930 /* ehci_iso_stream ops work with both ITD and SITD */
931
932 static struct ehci_iso_stream *
933 iso_stream_alloc (gfp_t mem_flags)
934 {
935 struct ehci_iso_stream *stream;
936
937 stream = kzalloc(sizeof *stream, mem_flags);
938 if (likely (stream != NULL)) {
939 INIT_LIST_HEAD(&stream->td_list);
940 INIT_LIST_HEAD(&stream->free_list);
941 stream->next_uframe = -1;
942 stream->refcount = 1;
943 }
944 return stream;
945 }
946
947 static void
948 iso_stream_init (
949 struct ehci_hcd *ehci,
950 struct ehci_iso_stream *stream,
951 struct usb_device *dev,
952 int pipe,
953 unsigned interval
954 )
955 {
956 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
957
958 u32 buf1;
959 unsigned epnum, maxp;
960 int is_input;
961 long bandwidth;
962
963 /*
964 * this might be a "high bandwidth" highspeed endpoint,
965 * as encoded in the ep descriptor's wMaxPacket field
966 */
967 epnum = usb_pipeendpoint (pipe);
968 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
969 maxp = usb_maxpacket(dev, pipe, !is_input);
970 if (is_input) {
971 buf1 = (1 << 11);
972 } else {
973 buf1 = 0;
974 }
975
976 /* knows about ITD vs SITD */
977 if (dev->speed == USB_SPEED_HIGH) {
978 unsigned multi = hb_mult(maxp);
979
980 stream->highspeed = 1;
981
982 maxp = max_packet(maxp);
983 buf1 |= maxp;
984 maxp *= multi;
985
986 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
987 stream->buf1 = cpu_to_hc32(ehci, buf1);
988 stream->buf2 = cpu_to_hc32(ehci, multi);
989
990 /* usbfs wants to report the average usecs per frame tied up
991 * when transfers on this endpoint are scheduled ...
992 */
993 stream->usecs = HS_USECS_ISO (maxp);
994 bandwidth = stream->usecs * 8;
995 bandwidth /= interval;
996
997 } else {
998 u32 addr;
999 int think_time;
1000 int hs_transfers;
1001
1002 addr = dev->ttport << 24;
1003 if (!ehci_is_TDI(ehci)
1004 || (dev->tt->hub !=
1005 ehci_to_hcd(ehci)->self.root_hub))
1006 addr |= dev->tt->hub->devnum << 16;
1007 addr |= epnum << 8;
1008 addr |= dev->devnum;
1009 stream->usecs = HS_USECS_ISO (maxp);
1010 think_time = dev->tt ? dev->tt->think_time : 0;
1011 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1012 dev->speed, is_input, 1, maxp));
1013 hs_transfers = max (1u, (maxp + 187) / 188);
1014 if (is_input) {
1015 u32 tmp;
1016
1017 addr |= 1 << 31;
1018 stream->c_usecs = stream->usecs;
1019 stream->usecs = HS_USECS_ISO (1);
1020 stream->raw_mask = 1;
1021
1022 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1023 tmp = (1 << (hs_transfers + 2)) - 1;
1024 stream->raw_mask |= tmp << (8 + 2);
1025 } else
1026 stream->raw_mask = smask_out [hs_transfers - 1];
1027 bandwidth = stream->usecs + stream->c_usecs;
1028 bandwidth /= interval << 3;
1029
1030 /* stream->splits gets created from raw_mask later */
1031 stream->address = cpu_to_hc32(ehci, addr);
1032 }
1033 stream->bandwidth = bandwidth;
1034
1035 stream->udev = dev;
1036
1037 stream->bEndpointAddress = is_input | epnum;
1038 stream->interval = interval;
1039 stream->maxp = maxp;
1040 }
1041
1042 static void
1043 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1044 {
1045 stream->refcount--;
1046
1047 /* free whenever just a dev->ep reference remains.
1048 * not like a QH -- no persistent state (toggle, halt)
1049 */
1050 if (stream->refcount == 1) {
1051 int is_in;
1052
1053 // BUG_ON (!list_empty(&stream->td_list));
1054
1055 while (!list_empty (&stream->free_list)) {
1056 struct list_head *entry;
1057
1058 entry = stream->free_list.next;
1059 list_del (entry);
1060
1061 /* knows about ITD vs SITD */
1062 if (stream->highspeed) {
1063 struct ehci_itd *itd;
1064
1065 itd = list_entry (entry, struct ehci_itd,
1066 itd_list);
1067 dma_pool_free (ehci->itd_pool, itd,
1068 itd->itd_dma);
1069 } else {
1070 struct ehci_sitd *sitd;
1071
1072 sitd = list_entry (entry, struct ehci_sitd,
1073 sitd_list);
1074 dma_pool_free (ehci->sitd_pool, sitd,
1075 sitd->sitd_dma);
1076 }
1077 }
1078
1079 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1080 stream->bEndpointAddress &= 0x0f;
1081 if (stream->ep)
1082 stream->ep->hcpriv = NULL;
1083
1084 kfree(stream);
1085 }
1086 }
1087
1088 static inline struct ehci_iso_stream *
1089 iso_stream_get (struct ehci_iso_stream *stream)
1090 {
1091 if (likely (stream != NULL))
1092 stream->refcount++;
1093 return stream;
1094 }
1095
1096 static struct ehci_iso_stream *
1097 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1098 {
1099 unsigned epnum;
1100 struct ehci_iso_stream *stream;
1101 struct usb_host_endpoint *ep;
1102 unsigned long flags;
1103
1104 epnum = usb_pipeendpoint (urb->pipe);
1105 if (usb_pipein(urb->pipe))
1106 ep = urb->dev->ep_in[epnum];
1107 else
1108 ep = urb->dev->ep_out[epnum];
1109
1110 spin_lock_irqsave (&ehci->lock, flags);
1111 stream = ep->hcpriv;
1112
1113 if (unlikely (stream == NULL)) {
1114 stream = iso_stream_alloc(GFP_ATOMIC);
1115 if (likely (stream != NULL)) {
1116 /* dev->ep owns the initial refcount */
1117 ep->hcpriv = stream;
1118 stream->ep = ep;
1119 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1120 urb->interval);
1121 }
1122
1123 /* if dev->ep [epnum] is a QH, hw is set */
1124 } else if (unlikely (stream->hw != NULL)) {
1125 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1126 urb->dev->devpath, epnum,
1127 usb_pipein(urb->pipe) ? "in" : "out");
1128 stream = NULL;
1129 }
1130
1131 /* caller guarantees an eventual matching iso_stream_put */
1132 stream = iso_stream_get (stream);
1133
1134 spin_unlock_irqrestore (&ehci->lock, flags);
1135 return stream;
1136 }
1137
1138 /*-------------------------------------------------------------------------*/
1139
1140 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1141
1142 static struct ehci_iso_sched *
1143 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1144 {
1145 struct ehci_iso_sched *iso_sched;
1146 int size = sizeof *iso_sched;
1147
1148 size += packets * sizeof (struct ehci_iso_packet);
1149 iso_sched = kzalloc(size, mem_flags);
1150 if (likely (iso_sched != NULL)) {
1151 INIT_LIST_HEAD (&iso_sched->td_list);
1152 }
1153 return iso_sched;
1154 }
1155
1156 static inline void
1157 itd_sched_init(
1158 struct ehci_hcd *ehci,
1159 struct ehci_iso_sched *iso_sched,
1160 struct ehci_iso_stream *stream,
1161 struct urb *urb
1162 )
1163 {
1164 unsigned i;
1165 dma_addr_t dma = urb->transfer_dma;
1166
1167 /* how many uframes are needed for these transfers */
1168 iso_sched->span = urb->number_of_packets * stream->interval;
1169
1170 /* figure out per-uframe itd fields that we'll need later
1171 * when we fit new itds into the schedule.
1172 */
1173 for (i = 0; i < urb->number_of_packets; i++) {
1174 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1175 unsigned length;
1176 dma_addr_t buf;
1177 u32 trans;
1178
1179 length = urb->iso_frame_desc [i].length;
1180 buf = dma + urb->iso_frame_desc [i].offset;
1181
1182 trans = EHCI_ISOC_ACTIVE;
1183 trans |= buf & 0x0fff;
1184 if (unlikely (((i + 1) == urb->number_of_packets))
1185 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1186 trans |= EHCI_ITD_IOC;
1187 trans |= length << 16;
1188 uframe->transaction = cpu_to_hc32(ehci, trans);
1189
1190 /* might need to cross a buffer page within a uframe */
1191 uframe->bufp = (buf & ~(u64)0x0fff);
1192 buf += length;
1193 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1194 uframe->cross = 1;
1195 }
1196 }
1197
1198 static void
1199 iso_sched_free (
1200 struct ehci_iso_stream *stream,
1201 struct ehci_iso_sched *iso_sched
1202 )
1203 {
1204 if (!iso_sched)
1205 return;
1206 // caller must hold ehci->lock!
1207 list_splice (&iso_sched->td_list, &stream->free_list);
1208 kfree (iso_sched);
1209 }
1210
1211 static int
1212 itd_urb_transaction (
1213 struct ehci_iso_stream *stream,
1214 struct ehci_hcd *ehci,
1215 struct urb *urb,
1216 gfp_t mem_flags
1217 )
1218 {
1219 struct ehci_itd *itd;
1220 dma_addr_t itd_dma;
1221 int i;
1222 unsigned num_itds;
1223 struct ehci_iso_sched *sched;
1224 unsigned long flags;
1225
1226 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1227 if (unlikely (sched == NULL))
1228 return -ENOMEM;
1229
1230 itd_sched_init(ehci, sched, stream, urb);
1231
1232 if (urb->interval < 8)
1233 num_itds = 1 + (sched->span + 7) / 8;
1234 else
1235 num_itds = urb->number_of_packets;
1236
1237 /* allocate/init ITDs */
1238 spin_lock_irqsave (&ehci->lock, flags);
1239 for (i = 0; i < num_itds; i++) {
1240
1241 /* free_list.next might be cache-hot ... but maybe
1242 * the HC caches it too. avoid that issue for now.
1243 */
1244
1245 /* prefer previously-allocated itds */
1246 if (likely (!list_empty(&stream->free_list))) {
1247 itd = list_entry (stream->free_list.prev,
1248 struct ehci_itd, itd_list);
1249 list_del (&itd->itd_list);
1250 itd_dma = itd->itd_dma;
1251 } else {
1252 spin_unlock_irqrestore (&ehci->lock, flags);
1253 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1254 &itd_dma);
1255 spin_lock_irqsave (&ehci->lock, flags);
1256 if (!itd) {
1257 iso_sched_free(stream, sched);
1258 spin_unlock_irqrestore(&ehci->lock, flags);
1259 return -ENOMEM;
1260 }
1261 }
1262
1263 memset (itd, 0, sizeof *itd);
1264 itd->itd_dma = itd_dma;
1265 list_add (&itd->itd_list, &sched->td_list);
1266 }
1267 spin_unlock_irqrestore (&ehci->lock, flags);
1268
1269 /* temporarily store schedule info in hcpriv */
1270 urb->hcpriv = sched;
1271 urb->error_count = 0;
1272 return 0;
1273 }
1274
1275 /*-------------------------------------------------------------------------*/
1276
1277 static inline int
1278 itd_slot_ok (
1279 struct ehci_hcd *ehci,
1280 u32 mod,
1281 u32 uframe,
1282 u8 usecs,
1283 u32 period
1284 )
1285 {
1286 uframe %= period;
1287 do {
1288 /* can't commit more than 80% periodic == 100 usec */
1289 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1290 > (100 - usecs))
1291 return 0;
1292
1293 /* we know urb->interval is 2^N uframes */
1294 uframe += period;
1295 } while (uframe < mod);
1296 return 1;
1297 }
1298
1299 static inline int
1300 sitd_slot_ok (
1301 struct ehci_hcd *ehci,
1302 u32 mod,
1303 struct ehci_iso_stream *stream,
1304 u32 uframe,
1305 struct ehci_iso_sched *sched,
1306 u32 period_uframes
1307 )
1308 {
1309 u32 mask, tmp;
1310 u32 frame, uf;
1311
1312 mask = stream->raw_mask << (uframe & 7);
1313
1314 /* for IN, don't wrap CSPLIT into the next frame */
1315 if (mask & ~0xffff)
1316 return 0;
1317
1318 /* this multi-pass logic is simple, but performance may
1319 * suffer when the schedule data isn't cached.
1320 */
1321
1322 /* check bandwidth */
1323 uframe %= period_uframes;
1324 do {
1325 u32 max_used;
1326
1327 frame = uframe >> 3;
1328 uf = uframe & 7;
1329
1330 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1331 /* The tt's fullspeed bus bandwidth must be available.
1332 * tt_available scheduling guarantees 10+% for control/bulk.
1333 */
1334 if (!tt_available (ehci, period_uframes << 3,
1335 stream->udev, frame, uf, stream->tt_usecs))
1336 return 0;
1337 #else
1338 /* tt must be idle for start(s), any gap, and csplit.
1339 * assume scheduling slop leaves 10+% for control/bulk.
1340 */
1341 if (!tt_no_collision (ehci, period_uframes << 3,
1342 stream->udev, frame, mask))
1343 return 0;
1344 #endif
1345
1346 /* check starts (OUT uses more than one) */
1347 max_used = 100 - stream->usecs;
1348 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1349 if (periodic_usecs (ehci, frame, uf) > max_used)
1350 return 0;
1351 }
1352
1353 /* for IN, check CSPLIT */
1354 if (stream->c_usecs) {
1355 uf = uframe & 7;
1356 max_used = 100 - stream->c_usecs;
1357 do {
1358 tmp = 1 << uf;
1359 tmp <<= 8;
1360 if ((stream->raw_mask & tmp) == 0)
1361 continue;
1362 if (periodic_usecs (ehci, frame, uf)
1363 > max_used)
1364 return 0;
1365 } while (++uf < 8);
1366 }
1367
1368 /* we know urb->interval is 2^N uframes */
1369 uframe += period_uframes;
1370 } while (uframe < mod);
1371
1372 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1373 return 1;
1374 }
1375
1376 /*
1377 * This scheduler plans almost as far into the future as it has actual
1378 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1379 * "as small as possible" to be cache-friendlier.) That limits the size
1380 * transfers you can stream reliably; avoid more than 64 msec per urb.
1381 * Also avoid queue depths of less than ehci's worst irq latency (affected
1382 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1383 * and other factors); or more than about 230 msec total (for portability,
1384 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1385 */
1386
1387 #define SCHEDULE_SLOP 80 /* microframes */
1388
1389 static int
1390 iso_stream_schedule (
1391 struct ehci_hcd *ehci,
1392 struct urb *urb,
1393 struct ehci_iso_stream *stream
1394 )
1395 {
1396 u32 now, next, start, period, span;
1397 int status;
1398 unsigned mod = ehci->periodic_size << 3;
1399 struct ehci_iso_sched *sched = urb->hcpriv;
1400
1401 period = urb->interval;
1402 span = sched->span;
1403 if (!stream->highspeed) {
1404 period <<= 3;
1405 span <<= 3;
1406 }
1407
1408 if (span > mod - SCHEDULE_SLOP) {
1409 ehci_dbg (ehci, "iso request %p too long\n", urb);
1410 status = -EFBIG;
1411 goto fail;
1412 }
1413
1414 now = ehci_readl(ehci, &ehci->regs->frame_index) & (mod - 1);
1415
1416 /* Typical case: reuse current schedule, stream is still active.
1417 * Hopefully there are no gaps from the host falling behind
1418 * (irq delays etc), but if there are we'll take the next
1419 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1420 */
1421 if (likely (!list_empty (&stream->td_list))) {
1422 u32 excess;
1423
1424 /* For high speed devices, allow scheduling within the
1425 * isochronous scheduling threshold. For full speed devices
1426 * and Intel PCI-based controllers, don't (work around for
1427 * Intel ICH9 bug).
1428 */
1429 if (!stream->highspeed && ehci->fs_i_thresh)
1430 next = now + ehci->i_thresh;
1431 else
1432 next = now;
1433
1434 /* Fell behind (by up to twice the slop amount)?
1435 * We decide based on the time of the last currently-scheduled
1436 * slot, not the time of the next available slot.
1437 */
1438 excess = (stream->next_uframe - period - next) & (mod - 1);
1439 if (excess >= mod - 2 * SCHEDULE_SLOP)
1440 start = next + excess - mod + period *
1441 DIV_ROUND_UP(mod - excess, period);
1442 else
1443 start = next + excess + period;
1444 if (start - now >= mod) {
1445 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1446 urb, start - now - period, period,
1447 mod);
1448 status = -EFBIG;
1449 goto fail;
1450 }
1451 }
1452
1453 /* need to schedule; when's the next (u)frame we could start?
1454 * this is bigger than ehci->i_thresh allows; scheduling itself
1455 * isn't free, the slop should handle reasonably slow cpus. it
1456 * can also help high bandwidth if the dma and irq loads don't
1457 * jump until after the queue is primed.
1458 */
1459 else {
1460 start = SCHEDULE_SLOP + (now & ~0x07);
1461
1462 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1463
1464 /* find a uframe slot with enough bandwidth */
1465 next = start + period;
1466 for (; start < next; start++) {
1467
1468 /* check schedule: enough space? */
1469 if (stream->highspeed) {
1470 if (itd_slot_ok(ehci, mod, start,
1471 stream->usecs, period))
1472 break;
1473 } else {
1474 if ((start % 8) >= 6)
1475 continue;
1476 if (sitd_slot_ok(ehci, mod, stream,
1477 start, sched, period))
1478 break;
1479 }
1480 }
1481
1482 /* no room in the schedule */
1483 if (start == next) {
1484 ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1485 urb, now, now + mod);
1486 status = -ENOSPC;
1487 goto fail;
1488 }
1489 }
1490
1491 /* Tried to schedule too far into the future? */
1492 if (unlikely(start - now + span - period
1493 >= mod - 2 * SCHEDULE_SLOP)) {
1494 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1495 urb, start - now, span - period,
1496 mod - 2 * SCHEDULE_SLOP);
1497 status = -EFBIG;
1498 goto fail;
1499 }
1500
1501 stream->next_uframe = start & (mod - 1);
1502
1503 /* report high speed start in uframes; full speed, in frames */
1504 urb->start_frame = stream->next_uframe;
1505 if (!stream->highspeed)
1506 urb->start_frame >>= 3;
1507 return 0;
1508
1509 fail:
1510 iso_sched_free(stream, sched);
1511 urb->hcpriv = NULL;
1512 return status;
1513 }
1514
1515 /*-------------------------------------------------------------------------*/
1516
1517 static inline void
1518 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1519 struct ehci_itd *itd)
1520 {
1521 int i;
1522
1523 /* it's been recently zeroed */
1524 itd->hw_next = EHCI_LIST_END(ehci);
1525 itd->hw_bufp [0] = stream->buf0;
1526 itd->hw_bufp [1] = stream->buf1;
1527 itd->hw_bufp [2] = stream->buf2;
1528
1529 for (i = 0; i < 8; i++)
1530 itd->index[i] = -1;
1531
1532 /* All other fields are filled when scheduling */
1533 }
1534
1535 static inline void
1536 itd_patch(
1537 struct ehci_hcd *ehci,
1538 struct ehci_itd *itd,
1539 struct ehci_iso_sched *iso_sched,
1540 unsigned index,
1541 u16 uframe
1542 )
1543 {
1544 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1545 unsigned pg = itd->pg;
1546
1547 // BUG_ON (pg == 6 && uf->cross);
1548
1549 uframe &= 0x07;
1550 itd->index [uframe] = index;
1551
1552 itd->hw_transaction[uframe] = uf->transaction;
1553 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1554 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1555 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1556
1557 /* iso_frame_desc[].offset must be strictly increasing */
1558 if (unlikely (uf->cross)) {
1559 u64 bufp = uf->bufp + 4096;
1560
1561 itd->pg = ++pg;
1562 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1563 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1564 }
1565 }
1566
1567 static inline void
1568 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1569 {
1570 union ehci_shadow *prev = &ehci->pshadow[frame];
1571 __hc32 *hw_p = &ehci->periodic[frame];
1572 union ehci_shadow here = *prev;
1573 __hc32 type = 0;
1574
1575 /* skip any iso nodes which might belong to previous microframes */
1576 while (here.ptr) {
1577 type = Q_NEXT_TYPE(ehci, *hw_p);
1578 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1579 break;
1580 prev = periodic_next_shadow(ehci, prev, type);
1581 hw_p = shadow_next_periodic(ehci, &here, type);
1582 here = *prev;
1583 }
1584
1585 itd->itd_next = here;
1586 itd->hw_next = *hw_p;
1587 prev->itd = itd;
1588 itd->frame = frame;
1589 wmb ();
1590 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1591 }
1592
1593 #define AB_REG_BAR_LOW 0xe0
1594 #define AB_REG_BAR_HIGH 0xe1
1595 #define AB_INDX(addr) ((addr) + 0x00)
1596 #define AB_DATA(addr) ((addr) + 0x04)
1597 #define NB_PCIE_INDX_ADDR 0xe0
1598 #define NB_PCIE_INDX_DATA 0xe4
1599 #define NB_PIF0_PWRDOWN_0 0x01100012
1600 #define NB_PIF0_PWRDOWN_1 0x01100013
1601
1602 static void ehci_quirk_amd_L1(struct ehci_hcd *ehci, int disable)
1603 {
1604 u32 addr, addr_low, addr_high, val;
1605
1606 outb_p(AB_REG_BAR_LOW, 0xcd6);
1607 addr_low = inb_p(0xcd7);
1608 outb_p(AB_REG_BAR_HIGH, 0xcd6);
1609 addr_high = inb_p(0xcd7);
1610 addr = addr_high << 8 | addr_low;
1611 outl_p(0x30, AB_INDX(addr));
1612 outl_p(0x40, AB_DATA(addr));
1613 outl_p(0x34, AB_INDX(addr));
1614 val = inl_p(AB_DATA(addr));
1615
1616 if (disable) {
1617 val &= ~0x8;
1618 val |= (1 << 4) | (1 << 9);
1619 } else {
1620 val |= 0x8;
1621 val &= ~((1 << 4) | (1 << 9));
1622 }
1623 outl_p(val, AB_DATA(addr));
1624
1625 if (amd_nb_dev) {
1626 addr = NB_PIF0_PWRDOWN_0;
1627 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_ADDR, addr);
1628 pci_read_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, &val);
1629 if (disable)
1630 val &= ~(0x3f << 7);
1631 else
1632 val |= 0x3f << 7;
1633
1634 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, val);
1635
1636 addr = NB_PIF0_PWRDOWN_1;
1637 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_ADDR, addr);
1638 pci_read_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, &val);
1639 if (disable)
1640 val &= ~(0x3f << 7);
1641 else
1642 val |= 0x3f << 7;
1643
1644 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, val);
1645 }
1646
1647 return;
1648 }
1649
1650 /* fit urb's itds into the selected schedule slot; activate as needed */
1651 static int
1652 itd_link_urb (
1653 struct ehci_hcd *ehci,
1654 struct urb *urb,
1655 unsigned mod,
1656 struct ehci_iso_stream *stream
1657 )
1658 {
1659 int packet;
1660 unsigned next_uframe, uframe, frame;
1661 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1662 struct ehci_itd *itd;
1663
1664 next_uframe = stream->next_uframe & (mod - 1);
1665
1666 if (unlikely (list_empty(&stream->td_list))) {
1667 ehci_to_hcd(ehci)->self.bandwidth_allocated
1668 += stream->bandwidth;
1669 ehci_vdbg (ehci,
1670 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1671 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1672 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1673 urb->interval,
1674 next_uframe >> 3, next_uframe & 0x7);
1675 }
1676
1677 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1678 if (ehci->amd_l1_fix == 1)
1679 ehci_quirk_amd_L1(ehci, 1);
1680 }
1681
1682 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1683
1684 /* fill iTDs uframe by uframe */
1685 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1686 if (itd == NULL) {
1687 /* ASSERT: we have all necessary itds */
1688 // BUG_ON (list_empty (&iso_sched->td_list));
1689
1690 /* ASSERT: no itds for this endpoint in this uframe */
1691
1692 itd = list_entry (iso_sched->td_list.next,
1693 struct ehci_itd, itd_list);
1694 list_move_tail (&itd->itd_list, &stream->td_list);
1695 itd->stream = iso_stream_get (stream);
1696 itd->urb = urb;
1697 itd_init (ehci, stream, itd);
1698 }
1699
1700 uframe = next_uframe & 0x07;
1701 frame = next_uframe >> 3;
1702
1703 itd_patch(ehci, itd, iso_sched, packet, uframe);
1704
1705 next_uframe += stream->interval;
1706 next_uframe &= mod - 1;
1707 packet++;
1708
1709 /* link completed itds into the schedule */
1710 if (((next_uframe >> 3) != frame)
1711 || packet == urb->number_of_packets) {
1712 itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1713 itd = NULL;
1714 }
1715 }
1716 stream->next_uframe = next_uframe;
1717
1718 /* don't need that schedule data any more */
1719 iso_sched_free (stream, iso_sched);
1720 urb->hcpriv = NULL;
1721
1722 timer_action (ehci, TIMER_IO_WATCHDOG);
1723 return enable_periodic(ehci);
1724 }
1725
1726 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1727
1728 /* Process and recycle a completed ITD. Return true iff its urb completed,
1729 * and hence its completion callback probably added things to the hardware
1730 * schedule.
1731 *
1732 * Note that we carefully avoid recycling this descriptor until after any
1733 * completion callback runs, so that it won't be reused quickly. That is,
1734 * assuming (a) no more than two urbs per frame on this endpoint, and also
1735 * (b) only this endpoint's completions submit URBs. It seems some silicon
1736 * corrupts things if you reuse completed descriptors very quickly...
1737 */
1738 static unsigned
1739 itd_complete (
1740 struct ehci_hcd *ehci,
1741 struct ehci_itd *itd
1742 ) {
1743 struct urb *urb = itd->urb;
1744 struct usb_iso_packet_descriptor *desc;
1745 u32 t;
1746 unsigned uframe;
1747 int urb_index = -1;
1748 struct ehci_iso_stream *stream = itd->stream;
1749 struct usb_device *dev;
1750 unsigned retval = false;
1751
1752 /* for each uframe with a packet */
1753 for (uframe = 0; uframe < 8; uframe++) {
1754 if (likely (itd->index[uframe] == -1))
1755 continue;
1756 urb_index = itd->index[uframe];
1757 desc = &urb->iso_frame_desc [urb_index];
1758
1759 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1760 itd->hw_transaction [uframe] = 0;
1761
1762 /* report transfer status */
1763 if (unlikely (t & ISO_ERRS)) {
1764 urb->error_count++;
1765 if (t & EHCI_ISOC_BUF_ERR)
1766 desc->status = usb_pipein (urb->pipe)
1767 ? -ENOSR /* hc couldn't read */
1768 : -ECOMM; /* hc couldn't write */
1769 else if (t & EHCI_ISOC_BABBLE)
1770 desc->status = -EOVERFLOW;
1771 else /* (t & EHCI_ISOC_XACTERR) */
1772 desc->status = -EPROTO;
1773
1774 /* HC need not update length with this error */
1775 if (!(t & EHCI_ISOC_BABBLE)) {
1776 desc->actual_length = EHCI_ITD_LENGTH(t);
1777 urb->actual_length += desc->actual_length;
1778 }
1779 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1780 desc->status = 0;
1781 desc->actual_length = EHCI_ITD_LENGTH(t);
1782 urb->actual_length += desc->actual_length;
1783 } else {
1784 /* URB was too late */
1785 desc->status = -EXDEV;
1786 }
1787 }
1788
1789 /* handle completion now? */
1790 if (likely ((urb_index + 1) != urb->number_of_packets))
1791 goto done;
1792
1793 /* ASSERT: it's really the last itd for this urb
1794 list_for_each_entry (itd, &stream->td_list, itd_list)
1795 BUG_ON (itd->urb == urb);
1796 */
1797
1798 /* give urb back to the driver; completion often (re)submits */
1799 dev = urb->dev;
1800 ehci_urb_done(ehci, urb, 0);
1801 retval = true;
1802 urb = NULL;
1803 (void) disable_periodic(ehci);
1804 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1805
1806 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1807 if (ehci->amd_l1_fix == 1)
1808 ehci_quirk_amd_L1(ehci, 0);
1809 }
1810
1811 if (unlikely(list_is_singular(&stream->td_list))) {
1812 ehci_to_hcd(ehci)->self.bandwidth_allocated
1813 -= stream->bandwidth;
1814 ehci_vdbg (ehci,
1815 "deschedule devp %s ep%d%s-iso\n",
1816 dev->devpath, stream->bEndpointAddress & 0x0f,
1817 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1818 }
1819 iso_stream_put (ehci, stream);
1820
1821 done:
1822 itd->urb = NULL;
1823 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1824 /* OK to recycle this ITD now. */
1825 itd->stream = NULL;
1826 list_move(&itd->itd_list, &stream->free_list);
1827 iso_stream_put(ehci, stream);
1828 } else {
1829 /* HW might remember this ITD, so we can't recycle it yet.
1830 * Move it to a safe place until a new frame starts.
1831 */
1832 list_move(&itd->itd_list, &ehci->cached_itd_list);
1833 if (stream->refcount == 2) {
1834 /* If iso_stream_put() were called here, stream
1835 * would be freed. Instead, just prevent reuse.
1836 */
1837 stream->ep->hcpriv = NULL;
1838 stream->ep = NULL;
1839 }
1840 }
1841 return retval;
1842 }
1843
1844 /*-------------------------------------------------------------------------*/
1845
1846 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1847 gfp_t mem_flags)
1848 {
1849 int status = -EINVAL;
1850 unsigned long flags;
1851 struct ehci_iso_stream *stream;
1852
1853 /* Get iso_stream head */
1854 stream = iso_stream_find (ehci, urb);
1855 if (unlikely (stream == NULL)) {
1856 ehci_dbg (ehci, "can't get iso stream\n");
1857 return -ENOMEM;
1858 }
1859 if (unlikely (urb->interval != stream->interval)) {
1860 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1861 stream->interval, urb->interval);
1862 goto done;
1863 }
1864
1865 #ifdef EHCI_URB_TRACE
1866 ehci_dbg (ehci,
1867 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1868 __func__, urb->dev->devpath, urb,
1869 usb_pipeendpoint (urb->pipe),
1870 usb_pipein (urb->pipe) ? "in" : "out",
1871 urb->transfer_buffer_length,
1872 urb->number_of_packets, urb->interval,
1873 stream);
1874 #endif
1875
1876 /* allocate ITDs w/o locking anything */
1877 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1878 if (unlikely (status < 0)) {
1879 ehci_dbg (ehci, "can't init itds\n");
1880 goto done;
1881 }
1882
1883 /* schedule ... need to lock */
1884 spin_lock_irqsave (&ehci->lock, flags);
1885 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1886 status = -ESHUTDOWN;
1887 goto done_not_linked;
1888 }
1889 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1890 if (unlikely(status))
1891 goto done_not_linked;
1892 status = iso_stream_schedule(ehci, urb, stream);
1893 if (likely (status == 0))
1894 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1895 else
1896 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1897 done_not_linked:
1898 spin_unlock_irqrestore (&ehci->lock, flags);
1899
1900 done:
1901 if (unlikely (status < 0))
1902 iso_stream_put (ehci, stream);
1903 return status;
1904 }
1905
1906 /*-------------------------------------------------------------------------*/
1907
1908 /*
1909 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1910 * TTs in USB 2.0 hubs. These need microframe scheduling.
1911 */
1912
1913 static inline void
1914 sitd_sched_init(
1915 struct ehci_hcd *ehci,
1916 struct ehci_iso_sched *iso_sched,
1917 struct ehci_iso_stream *stream,
1918 struct urb *urb
1919 )
1920 {
1921 unsigned i;
1922 dma_addr_t dma = urb->transfer_dma;
1923
1924 /* how many frames are needed for these transfers */
1925 iso_sched->span = urb->number_of_packets * stream->interval;
1926
1927 /* figure out per-frame sitd fields that we'll need later
1928 * when we fit new sitds into the schedule.
1929 */
1930 for (i = 0; i < urb->number_of_packets; i++) {
1931 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1932 unsigned length;
1933 dma_addr_t buf;
1934 u32 trans;
1935
1936 length = urb->iso_frame_desc [i].length & 0x03ff;
1937 buf = dma + urb->iso_frame_desc [i].offset;
1938
1939 trans = SITD_STS_ACTIVE;
1940 if (((i + 1) == urb->number_of_packets)
1941 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1942 trans |= SITD_IOC;
1943 trans |= length << 16;
1944 packet->transaction = cpu_to_hc32(ehci, trans);
1945
1946 /* might need to cross a buffer page within a td */
1947 packet->bufp = buf;
1948 packet->buf1 = (buf + length) & ~0x0fff;
1949 if (packet->buf1 != (buf & ~(u64)0x0fff))
1950 packet->cross = 1;
1951
1952 /* OUT uses multiple start-splits */
1953 if (stream->bEndpointAddress & USB_DIR_IN)
1954 continue;
1955 length = (length + 187) / 188;
1956 if (length > 1) /* BEGIN vs ALL */
1957 length |= 1 << 3;
1958 packet->buf1 |= length;
1959 }
1960 }
1961
1962 static int
1963 sitd_urb_transaction (
1964 struct ehci_iso_stream *stream,
1965 struct ehci_hcd *ehci,
1966 struct urb *urb,
1967 gfp_t mem_flags
1968 )
1969 {
1970 struct ehci_sitd *sitd;
1971 dma_addr_t sitd_dma;
1972 int i;
1973 struct ehci_iso_sched *iso_sched;
1974 unsigned long flags;
1975
1976 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1977 if (iso_sched == NULL)
1978 return -ENOMEM;
1979
1980 sitd_sched_init(ehci, iso_sched, stream, urb);
1981
1982 /* allocate/init sITDs */
1983 spin_lock_irqsave (&ehci->lock, flags);
1984 for (i = 0; i < urb->number_of_packets; i++) {
1985
1986 /* NOTE: for now, we don't try to handle wraparound cases
1987 * for IN (using sitd->hw_backpointer, like a FSTN), which
1988 * means we never need two sitds for full speed packets.
1989 */
1990
1991 /* free_list.next might be cache-hot ... but maybe
1992 * the HC caches it too. avoid that issue for now.
1993 */
1994
1995 /* prefer previously-allocated sitds */
1996 if (!list_empty(&stream->free_list)) {
1997 sitd = list_entry (stream->free_list.prev,
1998 struct ehci_sitd, sitd_list);
1999 list_del (&sitd->sitd_list);
2000 sitd_dma = sitd->sitd_dma;
2001 } else {
2002 spin_unlock_irqrestore (&ehci->lock, flags);
2003 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
2004 &sitd_dma);
2005 spin_lock_irqsave (&ehci->lock, flags);
2006 if (!sitd) {
2007 iso_sched_free(stream, iso_sched);
2008 spin_unlock_irqrestore(&ehci->lock, flags);
2009 return -ENOMEM;
2010 }
2011 }
2012
2013 memset (sitd, 0, sizeof *sitd);
2014 sitd->sitd_dma = sitd_dma;
2015 list_add (&sitd->sitd_list, &iso_sched->td_list);
2016 }
2017
2018 /* temporarily store schedule info in hcpriv */
2019 urb->hcpriv = iso_sched;
2020 urb->error_count = 0;
2021
2022 spin_unlock_irqrestore (&ehci->lock, flags);
2023 return 0;
2024 }
2025
2026 /*-------------------------------------------------------------------------*/
2027
2028 static inline void
2029 sitd_patch(
2030 struct ehci_hcd *ehci,
2031 struct ehci_iso_stream *stream,
2032 struct ehci_sitd *sitd,
2033 struct ehci_iso_sched *iso_sched,
2034 unsigned index
2035 )
2036 {
2037 struct ehci_iso_packet *uf = &iso_sched->packet [index];
2038 u64 bufp = uf->bufp;
2039
2040 sitd->hw_next = EHCI_LIST_END(ehci);
2041 sitd->hw_fullspeed_ep = stream->address;
2042 sitd->hw_uframe = stream->splits;
2043 sitd->hw_results = uf->transaction;
2044 sitd->hw_backpointer = EHCI_LIST_END(ehci);
2045
2046 bufp = uf->bufp;
2047 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
2048 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
2049
2050 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
2051 if (uf->cross)
2052 bufp += 4096;
2053 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
2054 sitd->index = index;
2055 }
2056
2057 static inline void
2058 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
2059 {
2060 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
2061 sitd->sitd_next = ehci->pshadow [frame];
2062 sitd->hw_next = ehci->periodic [frame];
2063 ehci->pshadow [frame].sitd = sitd;
2064 sitd->frame = frame;
2065 wmb ();
2066 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
2067 }
2068
2069 /* fit urb's sitds into the selected schedule slot; activate as needed */
2070 static int
2071 sitd_link_urb (
2072 struct ehci_hcd *ehci,
2073 struct urb *urb,
2074 unsigned mod,
2075 struct ehci_iso_stream *stream
2076 )
2077 {
2078 int packet;
2079 unsigned next_uframe;
2080 struct ehci_iso_sched *sched = urb->hcpriv;
2081 struct ehci_sitd *sitd;
2082
2083 next_uframe = stream->next_uframe;
2084
2085 if (list_empty(&stream->td_list)) {
2086 /* usbfs ignores TT bandwidth */
2087 ehci_to_hcd(ehci)->self.bandwidth_allocated
2088 += stream->bandwidth;
2089 ehci_vdbg (ehci,
2090 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2091 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2092 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2093 (next_uframe >> 3) & (ehci->periodic_size - 1),
2094 stream->interval, hc32_to_cpu(ehci, stream->splits));
2095 }
2096
2097 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2098 if (ehci->amd_l1_fix == 1)
2099 ehci_quirk_amd_L1(ehci, 1);
2100 }
2101
2102 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2103
2104 /* fill sITDs frame by frame */
2105 for (packet = 0, sitd = NULL;
2106 packet < urb->number_of_packets;
2107 packet++) {
2108
2109 /* ASSERT: we have all necessary sitds */
2110 BUG_ON (list_empty (&sched->td_list));
2111
2112 /* ASSERT: no itds for this endpoint in this frame */
2113
2114 sitd = list_entry (sched->td_list.next,
2115 struct ehci_sitd, sitd_list);
2116 list_move_tail (&sitd->sitd_list, &stream->td_list);
2117 sitd->stream = iso_stream_get (stream);
2118 sitd->urb = urb;
2119
2120 sitd_patch(ehci, stream, sitd, sched, packet);
2121 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2122 sitd);
2123
2124 next_uframe += stream->interval << 3;
2125 }
2126 stream->next_uframe = next_uframe & (mod - 1);
2127
2128 /* don't need that schedule data any more */
2129 iso_sched_free (stream, sched);
2130 urb->hcpriv = NULL;
2131
2132 timer_action (ehci, TIMER_IO_WATCHDOG);
2133 return enable_periodic(ehci);
2134 }
2135
2136 /*-------------------------------------------------------------------------*/
2137
2138 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2139 | SITD_STS_XACT | SITD_STS_MMF)
2140
2141 /* Process and recycle a completed SITD. Return true iff its urb completed,
2142 * and hence its completion callback probably added things to the hardware
2143 * schedule.
2144 *
2145 * Note that we carefully avoid recycling this descriptor until after any
2146 * completion callback runs, so that it won't be reused quickly. That is,
2147 * assuming (a) no more than two urbs per frame on this endpoint, and also
2148 * (b) only this endpoint's completions submit URBs. It seems some silicon
2149 * corrupts things if you reuse completed descriptors very quickly...
2150 */
2151 static unsigned
2152 sitd_complete (
2153 struct ehci_hcd *ehci,
2154 struct ehci_sitd *sitd
2155 ) {
2156 struct urb *urb = sitd->urb;
2157 struct usb_iso_packet_descriptor *desc;
2158 u32 t;
2159 int urb_index = -1;
2160 struct ehci_iso_stream *stream = sitd->stream;
2161 struct usb_device *dev;
2162 unsigned retval = false;
2163
2164 urb_index = sitd->index;
2165 desc = &urb->iso_frame_desc [urb_index];
2166 t = hc32_to_cpup(ehci, &sitd->hw_results);
2167
2168 /* report transfer status */
2169 if (t & SITD_ERRS) {
2170 urb->error_count++;
2171 if (t & SITD_STS_DBE)
2172 desc->status = usb_pipein (urb->pipe)
2173 ? -ENOSR /* hc couldn't read */
2174 : -ECOMM; /* hc couldn't write */
2175 else if (t & SITD_STS_BABBLE)
2176 desc->status = -EOVERFLOW;
2177 else /* XACT, MMF, etc */
2178 desc->status = -EPROTO;
2179 } else {
2180 desc->status = 0;
2181 desc->actual_length = desc->length - SITD_LENGTH(t);
2182 urb->actual_length += desc->actual_length;
2183 }
2184
2185 /* handle completion now? */
2186 if ((urb_index + 1) != urb->number_of_packets)
2187 goto done;
2188
2189 /* ASSERT: it's really the last sitd for this urb
2190 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2191 BUG_ON (sitd->urb == urb);
2192 */
2193
2194 /* give urb back to the driver; completion often (re)submits */
2195 dev = urb->dev;
2196 ehci_urb_done(ehci, urb, 0);
2197 retval = true;
2198 urb = NULL;
2199 (void) disable_periodic(ehci);
2200 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2201
2202 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2203 if (ehci->amd_l1_fix == 1)
2204 ehci_quirk_amd_L1(ehci, 0);
2205 }
2206
2207 if (list_is_singular(&stream->td_list)) {
2208 ehci_to_hcd(ehci)->self.bandwidth_allocated
2209 -= stream->bandwidth;
2210 ehci_vdbg (ehci,
2211 "deschedule devp %s ep%d%s-iso\n",
2212 dev->devpath, stream->bEndpointAddress & 0x0f,
2213 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2214 }
2215 iso_stream_put (ehci, stream);
2216
2217 done:
2218 sitd->urb = NULL;
2219 if (ehci->clock_frame != sitd->frame) {
2220 /* OK to recycle this SITD now. */
2221 sitd->stream = NULL;
2222 list_move(&sitd->sitd_list, &stream->free_list);
2223 iso_stream_put(ehci, stream);
2224 } else {
2225 /* HW might remember this SITD, so we can't recycle it yet.
2226 * Move it to a safe place until a new frame starts.
2227 */
2228 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2229 if (stream->refcount == 2) {
2230 /* If iso_stream_put() were called here, stream
2231 * would be freed. Instead, just prevent reuse.
2232 */
2233 stream->ep->hcpriv = NULL;
2234 stream->ep = NULL;
2235 }
2236 }
2237 return retval;
2238 }
2239
2240
2241 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2242 gfp_t mem_flags)
2243 {
2244 int status = -EINVAL;
2245 unsigned long flags;
2246 struct ehci_iso_stream *stream;
2247
2248 /* Get iso_stream head */
2249 stream = iso_stream_find (ehci, urb);
2250 if (stream == NULL) {
2251 ehci_dbg (ehci, "can't get iso stream\n");
2252 return -ENOMEM;
2253 }
2254 if (urb->interval != stream->interval) {
2255 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2256 stream->interval, urb->interval);
2257 goto done;
2258 }
2259
2260 #ifdef EHCI_URB_TRACE
2261 ehci_dbg (ehci,
2262 "submit %p dev%s ep%d%s-iso len %d\n",
2263 urb, urb->dev->devpath,
2264 usb_pipeendpoint (urb->pipe),
2265 usb_pipein (urb->pipe) ? "in" : "out",
2266 urb->transfer_buffer_length);
2267 #endif
2268
2269 /* allocate SITDs */
2270 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2271 if (status < 0) {
2272 ehci_dbg (ehci, "can't init sitds\n");
2273 goto done;
2274 }
2275
2276 /* schedule ... need to lock */
2277 spin_lock_irqsave (&ehci->lock, flags);
2278 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
2279 status = -ESHUTDOWN;
2280 goto done_not_linked;
2281 }
2282 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2283 if (unlikely(status))
2284 goto done_not_linked;
2285 status = iso_stream_schedule(ehci, urb, stream);
2286 if (status == 0)
2287 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2288 else
2289 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2290 done_not_linked:
2291 spin_unlock_irqrestore (&ehci->lock, flags);
2292
2293 done:
2294 if (status < 0)
2295 iso_stream_put (ehci, stream);
2296 return status;
2297 }
2298
2299 /*-------------------------------------------------------------------------*/
2300
2301 static void free_cached_lists(struct ehci_hcd *ehci)
2302 {
2303 struct ehci_itd *itd, *n;
2304 struct ehci_sitd *sitd, *sn;
2305
2306 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2307 struct ehci_iso_stream *stream = itd->stream;
2308 itd->stream = NULL;
2309 list_move(&itd->itd_list, &stream->free_list);
2310 iso_stream_put(ehci, stream);
2311 }
2312
2313 list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2314 struct ehci_iso_stream *stream = sitd->stream;
2315 sitd->stream = NULL;
2316 list_move(&sitd->sitd_list, &stream->free_list);
2317 iso_stream_put(ehci, stream);
2318 }
2319 }
2320
2321 /*-------------------------------------------------------------------------*/
2322
2323 static void
2324 scan_periodic (struct ehci_hcd *ehci)
2325 {
2326 unsigned now_uframe, frame, clock, clock_frame, mod;
2327 unsigned modified;
2328
2329 mod = ehci->periodic_size << 3;
2330
2331 /*
2332 * When running, scan from last scan point up to "now"
2333 * else clean up by scanning everything that's left.
2334 * Touches as few pages as possible: cache-friendly.
2335 */
2336 now_uframe = ehci->next_uframe;
2337 if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2338 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2339 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
2340 } else {
2341 clock = now_uframe + mod - 1;
2342 clock_frame = -1;
2343 }
2344 if (ehci->clock_frame != clock_frame) {
2345 free_cached_lists(ehci);
2346 ehci->clock_frame = clock_frame;
2347 }
2348 clock &= mod - 1;
2349 clock_frame = clock >> 3;
2350
2351 for (;;) {
2352 union ehci_shadow q, *q_p;
2353 __hc32 type, *hw_p;
2354 unsigned incomplete = false;
2355
2356 frame = now_uframe >> 3;
2357
2358 restart:
2359 /* scan each element in frame's queue for completions */
2360 q_p = &ehci->pshadow [frame];
2361 hw_p = &ehci->periodic [frame];
2362 q.ptr = q_p->ptr;
2363 type = Q_NEXT_TYPE(ehci, *hw_p);
2364 modified = 0;
2365
2366 while (q.ptr != NULL) {
2367 unsigned uf;
2368 union ehci_shadow temp;
2369 int live;
2370
2371 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2372 switch (hc32_to_cpu(ehci, type)) {
2373 case Q_TYPE_QH:
2374 /* handle any completions */
2375 temp.qh = qh_get (q.qh);
2376 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2377 q = q.qh->qh_next;
2378 modified = qh_completions (ehci, temp.qh);
2379 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2380 temp.qh->needs_rescan))
2381 intr_deschedule (ehci, temp.qh);
2382 qh_put (temp.qh);
2383 break;
2384 case Q_TYPE_FSTN:
2385 /* for "save place" FSTNs, look at QH entries
2386 * in the previous frame for completions.
2387 */
2388 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2389 dbg ("ignoring completions from FSTNs");
2390 }
2391 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2392 q = q.fstn->fstn_next;
2393 break;
2394 case Q_TYPE_ITD:
2395 /* If this ITD is still active, leave it for
2396 * later processing ... check the next entry.
2397 * No need to check for activity unless the
2398 * frame is current.
2399 */
2400 if (frame == clock_frame && live) {
2401 rmb();
2402 for (uf = 0; uf < 8; uf++) {
2403 if (q.itd->hw_transaction[uf] &
2404 ITD_ACTIVE(ehci))
2405 break;
2406 }
2407 if (uf < 8) {
2408 incomplete = true;
2409 q_p = &q.itd->itd_next;
2410 hw_p = &q.itd->hw_next;
2411 type = Q_NEXT_TYPE(ehci,
2412 q.itd->hw_next);
2413 q = *q_p;
2414 break;
2415 }
2416 }
2417
2418 /* Take finished ITDs out of the schedule
2419 * and process them: recycle, maybe report
2420 * URB completion. HC won't cache the
2421 * pointer for much longer, if at all.
2422 */
2423 *q_p = q.itd->itd_next;
2424 if (!ehci->use_dummy_qh ||
2425 q.itd->hw_next != EHCI_LIST_END(ehci))
2426 *hw_p = q.itd->hw_next;
2427 else
2428 *hw_p = ehci->dummy->qh_dma;
2429 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2430 wmb();
2431 modified = itd_complete (ehci, q.itd);
2432 q = *q_p;
2433 break;
2434 case Q_TYPE_SITD:
2435 /* If this SITD is still active, leave it for
2436 * later processing ... check the next entry.
2437 * No need to check for activity unless the
2438 * frame is current.
2439 */
2440 if (((frame == clock_frame) ||
2441 (((frame + 1) & (ehci->periodic_size - 1))
2442 == clock_frame))
2443 && live
2444 && (q.sitd->hw_results &
2445 SITD_ACTIVE(ehci))) {
2446
2447 incomplete = true;
2448 q_p = &q.sitd->sitd_next;
2449 hw_p = &q.sitd->hw_next;
2450 type = Q_NEXT_TYPE(ehci,
2451 q.sitd->hw_next);
2452 q = *q_p;
2453 break;
2454 }
2455
2456 /* Take finished SITDs out of the schedule
2457 * and process them: recycle, maybe report
2458 * URB completion.
2459 */
2460 *q_p = q.sitd->sitd_next;
2461 if (!ehci->use_dummy_qh ||
2462 q.sitd->hw_next != EHCI_LIST_END(ehci))
2463 *hw_p = q.sitd->hw_next;
2464 else
2465 *hw_p = ehci->dummy->qh_dma;
2466 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2467 wmb();
2468 modified = sitd_complete (ehci, q.sitd);
2469 q = *q_p;
2470 break;
2471 default:
2472 dbg ("corrupt type %d frame %d shadow %p",
2473 type, frame, q.ptr);
2474 // BUG ();
2475 q.ptr = NULL;
2476 }
2477
2478 /* assume completion callbacks modify the queue */
2479 if (unlikely (modified)) {
2480 if (likely(ehci->periodic_sched > 0))
2481 goto restart;
2482 /* short-circuit this scan */
2483 now_uframe = clock;
2484 break;
2485 }
2486 }
2487
2488 /* If we can tell we caught up to the hardware, stop now.
2489 * We can't advance our scan without collecting the ISO
2490 * transfers that are still pending in this frame.
2491 */
2492 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2493 ehci->next_uframe = now_uframe;
2494 break;
2495 }
2496
2497 // FIXME: this assumes we won't get lapped when
2498 // latencies climb; that should be rare, but...
2499 // detect it, and just go all the way around.
2500 // FLR might help detect this case, so long as latencies
2501 // don't exceed periodic_size msec (default 1.024 sec).
2502
2503 // FIXME: likewise assumes HC doesn't halt mid-scan
2504
2505 if (now_uframe == clock) {
2506 unsigned now;
2507
2508 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2509 || ehci->periodic_sched == 0)
2510 break;
2511 ehci->next_uframe = now_uframe;
2512 now = ehci_readl(ehci, &ehci->regs->frame_index) &
2513 (mod - 1);
2514 if (now_uframe == now)
2515 break;
2516
2517 /* rescan the rest of this frame, then ... */
2518 clock = now;
2519 clock_frame = clock >> 3;
2520 if (ehci->clock_frame != clock_frame) {
2521 free_cached_lists(ehci);
2522 ehci->clock_frame = clock_frame;
2523 }
2524 } else {
2525 now_uframe++;
2526 now_uframe &= mod - 1;
2527 }
2528 }
2529 }
linux-next