drivers/usb/host/pci-quirks.c

   1 /*
   2  * This file contains code to reset and initialize USB host controllers.
   3  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
   4  * It may need to run early during booting -- before USB would normally
   5  * initialize -- to ensure that Linux doesn't use any legacy modes.
   6  *
   7  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   8  *  (and others)
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/acpi.h>
  17 #include "pci-quirks.h"
  18 #include "xhci-ext-caps.h"
  19
  20
  21 #define UHCI_USBLEGSUP          0xc0            /* legacy support */
  22 #define UHCI_USBCMD             0               /* command register */
  23 #define UHCI_USBINTR            4               /* interrupt register */
  24 #define UHCI_USBLEGSUP_RWC      0x8f00          /* the R/WC bits */
  25 #define UHCI_USBLEGSUP_RO       0x5040          /* R/O and reserved bits */
  26 #define UHCI_USBCMD_RUN         0x0001          /* RUN/STOP bit */
  27 #define UHCI_USBCMD_HCRESET     0x0002          /* Host Controller reset */
  28 #define UHCI_USBCMD_EGSM        0x0008          /* Global Suspend Mode */
  29 #define UHCI_USBCMD_CONFIGURE   0x0040          /* Config Flag */
  30 #define UHCI_USBINTR_RESUME     0x0002          /* Resume interrupt enable */
  31
  32 #define OHCI_CONTROL            0x04
  33 #define OHCI_CMDSTATUS          0x08
  34 #define OHCI_INTRSTATUS         0x0c
  35 #define OHCI_INTRENABLE         0x10
  36 #define OHCI_INTRDISABLE        0x14
  37 #define OHCI_OCR                (1 << 3)        /* ownership change request */
  38 #define OHCI_CTRL_RWC           (1 << 9)        /* remote wakeup connected */
  39 #define OHCI_CTRL_IR            (1 << 8)        /* interrupt routing */
  40 #define OHCI_INTR_OC            (1 << 30)       /* ownership change */
  41
  42 #define EHCI_HCC_PARAMS         0x08            /* extended capabilities */
  43 #define EHCI_USBCMD             0               /* command register */
  44 #define EHCI_USBCMD_RUN         (1 << 0)        /* RUN/STOP bit */
  45 #define EHCI_USBSTS             4               /* status register */
  46 #define EHCI_USBSTS_HALTED      (1 << 12)       /* HCHalted bit */
  47 #define EHCI_USBINTR            8               /* interrupt register */
  48 #define EHCI_CONFIGFLAG         0x40            /* configured flag register */
  49 #define EHCI_USBLEGSUP          0               /* legacy support register */
  50 #define EHCI_USBLEGSUP_BIOS     (1 << 16)       /* BIOS semaphore */
  51 #define EHCI_USBLEGSUP_OS       (1 << 24)       /* OS semaphore */
  52 #define EHCI_USBLEGCTLSTS       4               /* legacy control/status */
  53 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)       /* SMI on ownership change */
  54
  55
  56 /*
  57  * Make sure the controller is completely inactive, unable to
  58  * generate interrupts or do DMA.
  59  */
  60 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
  61 {
  62         /* Turn off PIRQ enable and SMI enable.  (This also turns off the
  63          * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
  64          */
  65         pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
  66
  67         /* Reset the HC - this will force us to get a
  68          * new notification of any already connected
  69          * ports due to the virtual disconnect that it
  70          * implies.
  71          */
  72         outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
  73         mb();
  74         udelay(5);
  75         if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
  76                 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
  77
  78         /* Just to be safe, disable interrupt requests and
  79          * make sure the controller is stopped.
  80          */
  81         outw(0, base + UHCI_USBINTR);
  82         outw(0, base + UHCI_USBCMD);
  83 }
  84 EXPORT_SYMBOL_GPL(uhci_reset_hc);
  85
  86 /*
  87  * Initialize a controller that was newly discovered or has just been
  88  * resumed.  In either case we can't be sure of its previous state.
  89  *
  90  * Returns: 1 if the controller was reset, 0 otherwise.
  91  */
  92 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
  93 {
  94         u16 legsup;
  95         unsigned int cmd, intr;
  96
  97         /*
  98          * When restarting a suspended controller, we expect all the
  99          * settings to be the same as we left them:
 100          *
 101          *      PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
 102          *      Controller is stopped and configured with EGSM set;
 103          *      No interrupts enabled except possibly Resume Detect.
 104          *
 105          * If any of these conditions are violated we do a complete reset.
 106          */
 107         pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
 108         if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
 109                 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
 110                                 __func__, legsup);
 111                 goto reset_needed;
 112         }
 113
 114         cmd = inw(base + UHCI_USBCMD);
 115         if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
 116                         !(cmd & UHCI_USBCMD_EGSM)) {
 117                 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
 118                                 __func__, cmd);
 119                 goto reset_needed;
 120         }
 121
 122         intr = inw(base + UHCI_USBINTR);
 123         if (intr & (~UHCI_USBINTR_RESUME)) {
 124                 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
 125                                 __func__, intr);
 126                 goto reset_needed;
 127         }
 128         return 0;
 129
 130 reset_needed:
 131         dev_dbg(&pdev->dev, "Performing full reset\n");
 132         uhci_reset_hc(pdev, base);
 133         return 1;
 134 }
 135 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
 136
 137 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
 138 {
 139         u16 cmd;
 140         return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
 141 }
 142
 143 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
 144 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
 145
 146 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
 147 {
 148         unsigned long base = 0;
 149         int i;
 150
 151         if (!pio_enabled(pdev))
 152                 return;
 153
 154         for (i = 0; i < PCI_ROM_RESOURCE; i++)
 155                 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
 156                         base = pci_resource_start(pdev, i);
 157                         break;
 158                 }
 159
 160         if (base)
 161                 uhci_check_and_reset_hc(pdev, base);
 162 }
 163
 164 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
 165 {
 166         return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
 167 }
 168
 169 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
 170 {
 171         void __iomem *base;
 172         u32 control;
 173
 174         if (!mmio_resource_enabled(pdev, 0))
 175                 return;
 176
 177         base = pci_ioremap_bar(pdev, 0);
 178         if (base == NULL)
 179                 return;
 180
 181         control = readl(base + OHCI_CONTROL);
 182
 183 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
 184 #ifdef __hppa__
 185 #define OHCI_CTRL_MASK          (OHCI_CTRL_RWC | OHCI_CTRL_IR)
 186 #else
 187 #define OHCI_CTRL_MASK          OHCI_CTRL_RWC
 188
 189         if (control & OHCI_CTRL_IR) {
 190                 int wait_time = 500; /* arbitrary; 5 seconds */
 191                 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
 192                 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
 193                 while (wait_time > 0 &&
 194                                 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
 195                         wait_time -= 10;
 196                         msleep(10);
 197                 }
 198                 if (wait_time <= 0)
 199                         dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
 200                                         " (BIOS bug?) %08x\n",
 201                                         readl(base + OHCI_CONTROL));
 202         }
 203 #endif
 204
 205         /* reset controller, preserving RWC (and possibly IR) */
 206         writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
 207
 208         /*
 209          * disable interrupts
 210          */
 211         writel(~(u32)0, base + OHCI_INTRDISABLE);
 212         writel(~(u32)0, base + OHCI_INTRSTATUS);
 213
 214         iounmap(base);
 215 }
 216
 217 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
 218 {
 219         int wait_time, delta;
 220         void __iomem *base, *op_reg_base;
 221         u32     hcc_params, val;
 222         u8      offset, cap_length;
 223         int     count = 256/4;
 224         int     tried_handoff = 0;
 225
 226         if (!mmio_resource_enabled(pdev, 0))
 227                 return;
 228
 229         base = pci_ioremap_bar(pdev, 0);
 230         if (base == NULL)
 231                 return;
 232
 233         cap_length = readb(base);
 234         op_reg_base = base + cap_length;
 235
 236         /* EHCI 0.96 and later may have "extended capabilities"
 237          * spec section 5.1 explains the bios handoff, e.g. for
 238          * booting from USB disk or using a usb keyboard
 239          */
 240         hcc_params = readl(base + EHCI_HCC_PARAMS);
 241         offset = (hcc_params >> 8) & 0xff;
 242         while (offset && --count) {
 243                 u32             cap;
 244                 int             msec;
 245
 246                 pci_read_config_dword(pdev, offset, &cap);
 247                 switch (cap & 0xff) {
 248                 case 1:                 /* BIOS/SMM/... handoff support */
 249                         if ((cap & EHCI_USBLEGSUP_BIOS)) {
 250                                 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
 251
 252 #if 0
 253 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
 254  * but that seems dubious in general (the BIOS left it off intentionally)
 255  * and is known to prevent some systems from booting.  so we won't do this
 256  * unless maybe we can determine when we're on a system that needs SMI forced.
 257  */
 258                                 /* BIOS workaround (?): be sure the
 259                                  * pre-Linux code receives the SMI
 260                                  */
 261                                 pci_read_config_dword(pdev,
 262                                                 offset + EHCI_USBLEGCTLSTS,
 263                                                 &val);
 264                                 pci_write_config_dword(pdev,
 265                                                 offset + EHCI_USBLEGCTLSTS,
 266                                                 val | EHCI_USBLEGCTLSTS_SOOE);
 267 #endif
 268
 269                                 /* some systems get upset if this semaphore is
 270                                  * set for any other reason than forcing a BIOS
 271                                  * handoff..
 272                                  */
 273                                 pci_write_config_byte(pdev, offset + 3, 1);
 274                         }
 275
 276                         /* if boot firmware now owns EHCI, spin till
 277                          * it hands it over.
 278                          */
 279                         msec = 1000;
 280                         while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
 281                                 tried_handoff = 1;
 282                                 msleep(10);
 283                                 msec -= 10;
 284                                 pci_read_config_dword(pdev, offset, &cap);
 285                         }
 286
 287                         if (cap & EHCI_USBLEGSUP_BIOS) {
 288                                 /* well, possibly buggy BIOS... try to shut
 289                                  * it down, and hope nothing goes too wrong
 290                                  */
 291                                 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
 292                                                 " (BIOS bug?) %08x\n", cap);
 293                                 pci_write_config_byte(pdev, offset + 2, 0);
 294                         }
 295
 296                         /* just in case, always disable EHCI SMIs */
 297                         pci_write_config_dword(pdev,
 298                                         offset + EHCI_USBLEGCTLSTS,
 299                                         0);
 300
 301                         /* If the BIOS ever owned the controller then we
 302                          * can't expect any power sessions to remain intact.
 303                          */
 304                         if (tried_handoff)
 305                                 writel(0, op_reg_base + EHCI_CONFIGFLAG);
 306                         break;
 307                 case 0:                 /* illegal reserved capability */
 308                         cap = 0;
 309                         /* FALLTHROUGH */
 310                 default:
 311                         dev_warn(&pdev->dev, "EHCI: unrecognized capability "
 312                                         "%02x\n", cap & 0xff);
 313                         break;
 314                 }
 315                 offset = (cap >> 8) & 0xff;
 316         }
 317         if (!count)
 318                 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
 319
 320         /*
 321          * halt EHCI & disable its interrupts in any case
 322          */
 323         val = readl(op_reg_base + EHCI_USBSTS);
 324         if ((val & EHCI_USBSTS_HALTED) == 0) {
 325                 val = readl(op_reg_base + EHCI_USBCMD);
 326                 val &= ~EHCI_USBCMD_RUN;
 327                 writel(val, op_reg_base + EHCI_USBCMD);
 328
 329                 wait_time = 2000;
 330                 delta = 100;
 331                 do {
 332                         writel(0x3f, op_reg_base + EHCI_USBSTS);
 333                         udelay(delta);
 334                         wait_time -= delta;
 335                         val = readl(op_reg_base + EHCI_USBSTS);
 336                         if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
 337                                 break;
 338                         }
 339                 } while (wait_time > 0);
 340         }
 341         writel(0, op_reg_base + EHCI_USBINTR);
 342         writel(0x3f, op_reg_base + EHCI_USBSTS);
 343
 344         iounmap(base);
 345 }
 346
 347 /*
 348  * handshake - spin reading a register until handshake completes
 349  * @ptr: address of hc register to be read
 350  * @mask: bits to look at in result of read
 351  * @done: value of those bits when handshake succeeds
 352  * @wait_usec: timeout in microseconds
 353  * @delay_usec: delay in microseconds to wait between polling
 354  *
 355  * Polls a register every delay_usec microseconds.
 356  * Returns 0 when the mask bits have the value done.
 357  * Returns -ETIMEDOUT if this condition is not true after
 358  * wait_usec microseconds have passed.
 359  */
 360 static int handshake(void __iomem *ptr, u32 mask, u32 done,
 361                 int wait_usec, int delay_usec)
 362 {
 363         u32     result;
 364
 365         do {
 366                 result = readl(ptr);
 367                 result &= mask;
 368                 if (result == done)
 369                         return 0;
 370                 udelay(delay_usec);
 371                 wait_usec -= delay_usec;
 372         } while (wait_usec > 0);
 373         return -ETIMEDOUT;
 374 }
 375
 376 /**
 377  * PCI Quirks for xHCI.
 378  *
 379  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
 380  * It signals to the BIOS that the OS wants control of the host controller,
 381  * and then waits 5 seconds for the BIOS to hand over control.
 382  * If we timeout, assume the BIOS is broken and take control anyway.
 383  */
 384 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
 385 {
 386         void __iomem *base;
 387         int ext_cap_offset;
 388         void __iomem *op_reg_base;
 389         u32 val;
 390         int timeout;
 391
 392         if (!mmio_resource_enabled(pdev, 0))
 393                 return;
 394
 395         base = ioremap_nocache(pci_resource_start(pdev, 0),
 396                                 pci_resource_len(pdev, 0));
 397         if (base == NULL)
 398                 return;
 399
 400         /*
 401          * Find the Legacy Support Capability register -
 402          * this is optional for xHCI host controllers.
 403          */
 404         ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
 405         do {
 406                 if (!ext_cap_offset)
 407                         /* We've reached the end of the extended capabilities */
 408                         goto hc_init;
 409                 val = readl(base + ext_cap_offset);
 410                 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
 411                         break;
 412                 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
 413         } while (1);
 414
 415         /* If the BIOS owns the HC, signal that the OS wants it, and wait */
 416         if (val & XHCI_HC_BIOS_OWNED) {
 417                 writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset);
 418
 419                 /* Wait for 5 seconds with 10 microsecond polling interval */
 420                 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
 421                                 0, 5000, 10);
 422
 423                 /* Assume a buggy BIOS and take HC ownership anyway */
 424                 if (timeout) {
 425                         dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
 426                                         " (BIOS bug ?) %08x\n", val);
 427                         writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
 428                 }
 429         }
 430
 431         /* Disable any BIOS SMIs */
 432         writel(XHCI_LEGACY_DISABLE_SMI,
 433                         base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 434
 435 hc_init:
 436         op_reg_base = base + XHCI_HC_LENGTH(readl(base));
 437
 438         /* Wait for the host controller to be ready before writing any
 439          * operational or runtime registers.  Wait 5 seconds and no more.
 440          */
 441         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
 442                         5000, 10);
 443         /* Assume a buggy HC and start HC initialization anyway */
 444         if (timeout) {
 445                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 446                 dev_warn(&pdev->dev,
 447                                 "xHCI HW not ready after 5 sec (HC bug?) "
 448                                 "status = 0x%x\n", val);
 449         }
 450
 451         /* Send the halt and disable interrupts command */
 452         val = readl(op_reg_base + XHCI_CMD_OFFSET);
 453         val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
 454         writel(val, op_reg_base + XHCI_CMD_OFFSET);
 455
 456         /* Wait for the HC to halt - poll every 125 usec (one microframe). */
 457         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
 458                         XHCI_MAX_HALT_USEC, 125);
 459         if (timeout) {
 460                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 461                 dev_warn(&pdev->dev,
 462                                 "xHCI HW did not halt within %d usec "
 463                                 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
 464         }
 465
 466         iounmap(base);
 467 }
 468
 469 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
 470 {
 471         if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
 472                 quirk_usb_handoff_uhci(pdev);
 473         else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
 474                 quirk_usb_handoff_ohci(pdev);
 475         else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
 476                 quirk_usb_disable_ehci(pdev);
 477         else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
 478                 quirk_usb_handoff_xhci(pdev);
 479 }
 480 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);