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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / usb / musb / musb_core.c
blob07cf394e491b01bddc5bd84fdcbc31016c174655
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #include "musb_core.h"
103
104 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
105
106
107 unsigned musb_debug;
108 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
109 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
110
111 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
112 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113
114 #define MUSB_VERSION "6.0"
115
116 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117
118 #define MUSB_DRIVER_NAME "musb-hdrc"
119 const char musb_driver_name[] = MUSB_DRIVER_NAME;
120
121 MODULE_DESCRIPTION(DRIVER_INFO);
122 MODULE_AUTHOR(DRIVER_AUTHOR);
123 MODULE_LICENSE("GPL");
124 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125
126
127 /*-------------------------------------------------------------------------*/
128
129 static inline struct musb *dev_to_musb(struct device *dev)
130 {
131 #ifdef CONFIG_USB_MUSB_HDRC_HCD
132 /* usbcore insists dev->driver_data is a "struct hcd *" */
133 return hcd_to_musb(dev_get_drvdata(dev));
134 #else
135 return dev_get_drvdata(dev);
136 #endif
137 }
138
139 /*-------------------------------------------------------------------------*/
140
141 #ifndef CONFIG_BLACKFIN
142 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
143 {
144 void __iomem *addr = otg->io_priv;
145 int i = 0;
146 u8 r;
147 u8 power;
148
149 /* Make sure the transceiver is not in low power mode */
150 power = musb_readb(addr, MUSB_POWER);
151 power &= ~MUSB_POWER_SUSPENDM;
152 musb_writeb(addr, MUSB_POWER, power);
153
154 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
155 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
156 */
157
158 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
159 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
160 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
161
162 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
163 & MUSB_ULPI_REG_CMPLT)) {
164 i++;
165 if (i == 10000) {
166 DBG(3, "ULPI read timed out\n");
167 return -ETIMEDOUT;
168 }
169
170 }
171 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
172 r &= ~MUSB_ULPI_REG_CMPLT;
173 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
174
175 return musb_readb(addr, MUSB_ULPI_REG_DATA);
176 }
177
178 static int musb_ulpi_write(struct otg_transceiver *otg,
179 u32 offset, u32 data)
180 {
181 void __iomem *addr = otg->io_priv;
182 int i = 0;
183 u8 r = 0;
184 u8 power;
185
186 /* Make sure the transceiver is not in low power mode */
187 power = musb_readb(addr, MUSB_POWER);
188 power &= ~MUSB_POWER_SUSPENDM;
189 musb_writeb(addr, MUSB_POWER, power);
190
191 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
192 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
193 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
194
195 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
196 & MUSB_ULPI_REG_CMPLT)) {
197 i++;
198 if (i == 10000) {
199 DBG(3, "ULPI write timed out\n");
200 return -ETIMEDOUT;
201 }
202 }
203
204 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
205 r &= ~MUSB_ULPI_REG_CMPLT;
206 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
207
208 return 0;
209 }
210 #else
211 #define musb_ulpi_read NULL
212 #define musb_ulpi_write NULL
213 #endif
214
215 static struct otg_io_access_ops musb_ulpi_access = {
216 .read = musb_ulpi_read,
217 .write = musb_ulpi_write,
218 };
219
220 /*-------------------------------------------------------------------------*/
221
222 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
223
224 /*
225 * Load an endpoint's FIFO
226 */
227 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
228 {
229 void __iomem *fifo = hw_ep->fifo;
230
231 prefetch((u8 *)src);
232
233 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
234 'T', hw_ep->epnum, fifo, len, src);
235
236 /* we can't assume unaligned reads work */
237 if (likely((0x01 & (unsigned long) src) == 0)) {
238 u16 index = 0;
239
240 /* best case is 32bit-aligned source address */
241 if ((0x02 & (unsigned long) src) == 0) {
242 if (len >= 4) {
243 writesl(fifo, src + index, len >> 2);
244 index += len & ~0x03;
245 }
246 if (len & 0x02) {
247 musb_writew(fifo, 0, *(u16 *)&src[index]);
248 index += 2;
249 }
250 } else {
251 if (len >= 2) {
252 writesw(fifo, src + index, len >> 1);
253 index += len & ~0x01;
254 }
255 }
256 if (len & 0x01)
257 musb_writeb(fifo, 0, src[index]);
258 } else {
259 /* byte aligned */
260 writesb(fifo, src, len);
261 }
262 }
263
264 #if !defined(CONFIG_USB_MUSB_AM35X)
265 /*
266 * Unload an endpoint's FIFO
267 */
268 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
269 {
270 void __iomem *fifo = hw_ep->fifo;
271
272 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
273 'R', hw_ep->epnum, fifo, len, dst);
274
275 /* we can't assume unaligned writes work */
276 if (likely((0x01 & (unsigned long) dst) == 0)) {
277 u16 index = 0;
278
279 /* best case is 32bit-aligned destination address */
280 if ((0x02 & (unsigned long) dst) == 0) {
281 if (len >= 4) {
282 readsl(fifo, dst, len >> 2);
283 index = len & ~0x03;
284 }
285 if (len & 0x02) {
286 *(u16 *)&dst[index] = musb_readw(fifo, 0);
287 index += 2;
288 }
289 } else {
290 if (len >= 2) {
291 readsw(fifo, dst, len >> 1);
292 index = len & ~0x01;
293 }
294 }
295 if (len & 0x01)
296 dst[index] = musb_readb(fifo, 0);
297 } else {
298 /* byte aligned */
299 readsb(fifo, dst, len);
300 }
301 }
302 #endif
303
304 #endif /* normal PIO */
305
306
307 /*-------------------------------------------------------------------------*/
308
309 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
310 static const u8 musb_test_packet[53] = {
311 /* implicit SYNC then DATA0 to start */
312
313 /* JKJKJKJK x9 */
314 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
315 /* JJKKJJKK x8 */
316 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
317 /* JJJJKKKK x8 */
318 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
319 /* JJJJJJJKKKKKKK x8 */
320 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
321 /* JJJJJJJK x8 */
322 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
323 /* JKKKKKKK x10, JK */
324 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
325
326 /* implicit CRC16 then EOP to end */
327 };
328
329 void musb_load_testpacket(struct musb *musb)
330 {
331 void __iomem *regs = musb->endpoints[0].regs;
332
333 musb_ep_select(musb->mregs, 0);
334 musb_write_fifo(musb->control_ep,
335 sizeof(musb_test_packet), musb_test_packet);
336 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
337 }
338
339 /*-------------------------------------------------------------------------*/
340
341 const char *otg_state_string(struct musb *musb)
342 {
343 switch (musb->xceiv->state) {
344 case OTG_STATE_A_IDLE: return "a_idle";
345 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
346 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
347 case OTG_STATE_A_HOST: return "a_host";
348 case OTG_STATE_A_SUSPEND: return "a_suspend";
349 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
350 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
351 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
352 case OTG_STATE_B_IDLE: return "b_idle";
353 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
354 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
355 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
356 case OTG_STATE_B_HOST: return "b_host";
357 default: return "UNDEFINED";
358 }
359 }
360
361 #ifdef CONFIG_USB_MUSB_OTG
362
363 /*
364 * Handles OTG hnp timeouts, such as b_ase0_brst
365 */
366 void musb_otg_timer_func(unsigned long data)
367 {
368 struct musb *musb = (struct musb *)data;
369 unsigned long flags;
370
371 spin_lock_irqsave(&musb->lock, flags);
372 switch (musb->xceiv->state) {
373 case OTG_STATE_B_WAIT_ACON:
374 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
375 musb_g_disconnect(musb);
376 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
377 musb->is_active = 0;
378 break;
379 case OTG_STATE_A_SUSPEND:
380 case OTG_STATE_A_WAIT_BCON:
381 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
382 musb_platform_set_vbus(musb, 0);
383 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
384 break;
385 default:
386 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
387 }
388 musb->ignore_disconnect = 0;
389 spin_unlock_irqrestore(&musb->lock, flags);
390 }
391
392 /*
393 * Stops the HNP transition. Caller must take care of locking.
394 */
395 void musb_hnp_stop(struct musb *musb)
396 {
397 struct usb_hcd *hcd = musb_to_hcd(musb);
398 void __iomem *mbase = musb->mregs;
399 u8 reg;
400
401 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
402
403 switch (musb->xceiv->state) {
404 case OTG_STATE_A_PERIPHERAL:
405 musb_g_disconnect(musb);
406 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
407 break;
408 case OTG_STATE_B_HOST:
409 DBG(1, "HNP: Disabling HR\n");
410 hcd->self.is_b_host = 0;
411 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
412 MUSB_DEV_MODE(musb);
413 reg = musb_readb(mbase, MUSB_POWER);
414 reg |= MUSB_POWER_SUSPENDM;
415 musb_writeb(mbase, MUSB_POWER, reg);
416 /* REVISIT: Start SESSION_REQUEST here? */
417 break;
418 default:
419 DBG(1, "HNP: Stopping in unknown state %s\n",
420 otg_state_string(musb));
421 }
422
423 /*
424 * When returning to A state after HNP, avoid hub_port_rebounce(),
425 * which cause occasional OPT A "Did not receive reset after connect"
426 * errors.
427 */
428 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
429 }
430
431 #endif
432
433 /*
434 * Interrupt Service Routine to record USB "global" interrupts.
435 * Since these do not happen often and signify things of
436 * paramount importance, it seems OK to check them individually;
437 * the order of the tests is specified in the manual
438 *
439 * @param musb instance pointer
440 * @param int_usb register contents
441 * @param devctl
442 * @param power
443 */
444
445 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
446 u8 devctl, u8 power)
447 {
448 irqreturn_t handled = IRQ_NONE;
449
450 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
451 int_usb);
452
453 /* in host mode, the peripheral may issue remote wakeup.
454 * in peripheral mode, the host may resume the link.
455 * spurious RESUME irqs happen too, paired with SUSPEND.
456 */
457 if (int_usb & MUSB_INTR_RESUME) {
458 handled = IRQ_HANDLED;
459 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
460
461 if (devctl & MUSB_DEVCTL_HM) {
462 #ifdef CONFIG_USB_MUSB_HDRC_HCD
463 void __iomem *mbase = musb->mregs;
464
465 switch (musb->xceiv->state) {
466 case OTG_STATE_A_SUSPEND:
467 /* remote wakeup? later, GetPortStatus
468 * will stop RESUME signaling
469 */
470
471 if (power & MUSB_POWER_SUSPENDM) {
472 /* spurious */
473 musb->int_usb &= ~MUSB_INTR_SUSPEND;
474 DBG(2, "Spurious SUSPENDM\n");
475 break;
476 }
477
478 power &= ~MUSB_POWER_SUSPENDM;
479 musb_writeb(mbase, MUSB_POWER,
480 power | MUSB_POWER_RESUME);
481
482 musb->port1_status |=
483 (USB_PORT_STAT_C_SUSPEND << 16)
484 | MUSB_PORT_STAT_RESUME;
485 musb->rh_timer = jiffies
486 + msecs_to_jiffies(20);
487
488 musb->xceiv->state = OTG_STATE_A_HOST;
489 musb->is_active = 1;
490 usb_hcd_resume_root_hub(musb_to_hcd(musb));
491 break;
492 case OTG_STATE_B_WAIT_ACON:
493 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
494 musb->is_active = 1;
495 MUSB_DEV_MODE(musb);
496 break;
497 default:
498 WARNING("bogus %s RESUME (%s)\n",
499 "host",
500 otg_state_string(musb));
501 }
502 #endif
503 } else {
504 switch (musb->xceiv->state) {
505 #ifdef CONFIG_USB_MUSB_HDRC_HCD
506 case OTG_STATE_A_SUSPEND:
507 /* possibly DISCONNECT is upcoming */
508 musb->xceiv->state = OTG_STATE_A_HOST;
509 usb_hcd_resume_root_hub(musb_to_hcd(musb));
510 break;
511 #endif
512 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
513 case OTG_STATE_B_WAIT_ACON:
514 case OTG_STATE_B_PERIPHERAL:
515 /* disconnect while suspended? we may
516 * not get a disconnect irq...
517 */
518 if ((devctl & MUSB_DEVCTL_VBUS)
519 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
520 ) {
521 musb->int_usb |= MUSB_INTR_DISCONNECT;
522 musb->int_usb &= ~MUSB_INTR_SUSPEND;
523 break;
524 }
525 musb_g_resume(musb);
526 break;
527 case OTG_STATE_B_IDLE:
528 musb->int_usb &= ~MUSB_INTR_SUSPEND;
529 break;
530 #endif
531 default:
532 WARNING("bogus %s RESUME (%s)\n",
533 "peripheral",
534 otg_state_string(musb));
535 }
536 }
537 }
538
539 #ifdef CONFIG_USB_MUSB_HDRC_HCD
540 /* see manual for the order of the tests */
541 if (int_usb & MUSB_INTR_SESSREQ) {
542 void __iomem *mbase = musb->mregs;
543
544 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
545 && (devctl & MUSB_DEVCTL_BDEVICE)) {
546 DBG(3, "SessReq while on B state\n");
547 return IRQ_HANDLED;
548 }
549
550 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
551
552 /* IRQ arrives from ID pin sense or (later, if VBUS power
553 * is removed) SRP. responses are time critical:
554 * - turn on VBUS (with silicon-specific mechanism)
555 * - go through A_WAIT_VRISE
556 * - ... to A_WAIT_BCON.
557 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
558 */
559 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
560 musb->ep0_stage = MUSB_EP0_START;
561 musb->xceiv->state = OTG_STATE_A_IDLE;
562 MUSB_HST_MODE(musb);
563 musb_platform_set_vbus(musb, 1);
564
565 handled = IRQ_HANDLED;
566 }
567
568 if (int_usb & MUSB_INTR_VBUSERROR) {
569 int ignore = 0;
570
571 /* During connection as an A-Device, we may see a short
572 * current spikes causing voltage drop, because of cable
573 * and peripheral capacitance combined with vbus draw.
574 * (So: less common with truly self-powered devices, where
575 * vbus doesn't act like a power supply.)
576 *
577 * Such spikes are short; usually less than ~500 usec, max
578 * of ~2 msec. That is, they're not sustained overcurrent
579 * errors, though they're reported using VBUSERROR irqs.
580 *
581 * Workarounds: (a) hardware: use self powered devices.
582 * (b) software: ignore non-repeated VBUS errors.
583 *
584 * REVISIT: do delays from lots of DEBUG_KERNEL checks
585 * make trouble here, keeping VBUS < 4.4V ?
586 */
587 switch (musb->xceiv->state) {
588 case OTG_STATE_A_HOST:
589 /* recovery is dicey once we've gotten past the
590 * initial stages of enumeration, but if VBUS
591 * stayed ok at the other end of the link, and
592 * another reset is due (at least for high speed,
593 * to redo the chirp etc), it might work OK...
594 */
595 case OTG_STATE_A_WAIT_BCON:
596 case OTG_STATE_A_WAIT_VRISE:
597 if (musb->vbuserr_retry) {
598 void __iomem *mbase = musb->mregs;
599
600 musb->vbuserr_retry--;
601 ignore = 1;
602 devctl |= MUSB_DEVCTL_SESSION;
603 musb_writeb(mbase, MUSB_DEVCTL, devctl);
604 } else {
605 musb->port1_status |=
606 USB_PORT_STAT_OVERCURRENT
607 | (USB_PORT_STAT_C_OVERCURRENT << 16);
608 }
609 break;
610 default:
611 break;
612 }
613
614 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
615 otg_state_string(musb),
616 devctl,
617 ({ char *s;
618 switch (devctl & MUSB_DEVCTL_VBUS) {
619 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
620 s = "<SessEnd"; break;
621 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
622 s = "<AValid"; break;
623 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
624 s = "<VBusValid"; break;
625 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
626 default:
627 s = "VALID"; break;
628 }; s; }),
629 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
630 musb->port1_status);
631
632 /* go through A_WAIT_VFALL then start a new session */
633 if (!ignore)
634 musb_platform_set_vbus(musb, 0);
635 handled = IRQ_HANDLED;
636 }
637
638 #endif
639 if (int_usb & MUSB_INTR_SUSPEND) {
640 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
641 otg_state_string(musb), devctl, power);
642 handled = IRQ_HANDLED;
643
644 switch (musb->xceiv->state) {
645 #ifdef CONFIG_USB_MUSB_OTG
646 case OTG_STATE_A_PERIPHERAL:
647 /* We also come here if the cable is removed, since
648 * this silicon doesn't report ID-no-longer-grounded.
649 *
650 * We depend on T(a_wait_bcon) to shut us down, and
651 * hope users don't do anything dicey during this
652 * undesired detour through A_WAIT_BCON.
653 */
654 musb_hnp_stop(musb);
655 usb_hcd_resume_root_hub(musb_to_hcd(musb));
656 musb_root_disconnect(musb);
657 musb_platform_try_idle(musb, jiffies
658 + msecs_to_jiffies(musb->a_wait_bcon
659 ? : OTG_TIME_A_WAIT_BCON));
660
661 break;
662 #endif
663 case OTG_STATE_B_IDLE:
664 if (!musb->is_active)
665 break;
666 case OTG_STATE_B_PERIPHERAL:
667 musb_g_suspend(musb);
668 musb->is_active = is_otg_enabled(musb)
669 && musb->xceiv->gadget->b_hnp_enable;
670 if (musb->is_active) {
671 #ifdef CONFIG_USB_MUSB_OTG
672 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
673 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
674 mod_timer(&musb->otg_timer, jiffies
675 + msecs_to_jiffies(
676 OTG_TIME_B_ASE0_BRST));
677 #endif
678 }
679 break;
680 case OTG_STATE_A_WAIT_BCON:
681 if (musb->a_wait_bcon != 0)
682 musb_platform_try_idle(musb, jiffies
683 + msecs_to_jiffies(musb->a_wait_bcon));
684 break;
685 case OTG_STATE_A_HOST:
686 musb->xceiv->state = OTG_STATE_A_SUSPEND;
687 musb->is_active = is_otg_enabled(musb)
688 && musb->xceiv->host->b_hnp_enable;
689 break;
690 case OTG_STATE_B_HOST:
691 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
692 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
693 break;
694 default:
695 /* "should not happen" */
696 musb->is_active = 0;
697 break;
698 }
699 }
700
701 #ifdef CONFIG_USB_MUSB_HDRC_HCD
702 if (int_usb & MUSB_INTR_CONNECT) {
703 struct usb_hcd *hcd = musb_to_hcd(musb);
704
705 handled = IRQ_HANDLED;
706 musb->is_active = 1;
707 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
708
709 musb->ep0_stage = MUSB_EP0_START;
710
711 #ifdef CONFIG_USB_MUSB_OTG
712 /* flush endpoints when transitioning from Device Mode */
713 if (is_peripheral_active(musb)) {
714 /* REVISIT HNP; just force disconnect */
715 }
716 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
717 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
718 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
719 #endif
720 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
721 |USB_PORT_STAT_HIGH_SPEED
722 |USB_PORT_STAT_ENABLE
723 );
724 musb->port1_status |= USB_PORT_STAT_CONNECTION
725 |(USB_PORT_STAT_C_CONNECTION << 16);
726
727 /* high vs full speed is just a guess until after reset */
728 if (devctl & MUSB_DEVCTL_LSDEV)
729 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
730
731 /* indicate new connection to OTG machine */
732 switch (musb->xceiv->state) {
733 case OTG_STATE_B_PERIPHERAL:
734 if (int_usb & MUSB_INTR_SUSPEND) {
735 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
736 int_usb &= ~MUSB_INTR_SUSPEND;
737 goto b_host;
738 } else
739 DBG(1, "CONNECT as b_peripheral???\n");
740 break;
741 case OTG_STATE_B_WAIT_ACON:
742 DBG(1, "HNP: CONNECT, now b_host\n");
743 b_host:
744 musb->xceiv->state = OTG_STATE_B_HOST;
745 hcd->self.is_b_host = 1;
746 musb->ignore_disconnect = 0;
747 del_timer(&musb->otg_timer);
748 break;
749 default:
750 if ((devctl & MUSB_DEVCTL_VBUS)
751 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
752 musb->xceiv->state = OTG_STATE_A_HOST;
753 hcd->self.is_b_host = 0;
754 }
755 break;
756 }
757
758 /* poke the root hub */
759 MUSB_HST_MODE(musb);
760 if (hcd->status_urb)
761 usb_hcd_poll_rh_status(hcd);
762 else
763 usb_hcd_resume_root_hub(hcd);
764
765 DBG(1, "CONNECT (%s) devctl %02x\n",
766 otg_state_string(musb), devctl);
767 }
768 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
769
770 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
771 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
772 otg_state_string(musb),
773 MUSB_MODE(musb), devctl);
774 handled = IRQ_HANDLED;
775
776 switch (musb->xceiv->state) {
777 #ifdef CONFIG_USB_MUSB_HDRC_HCD
778 case OTG_STATE_A_HOST:
779 case OTG_STATE_A_SUSPEND:
780 usb_hcd_resume_root_hub(musb_to_hcd(musb));
781 musb_root_disconnect(musb);
782 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
783 musb_platform_try_idle(musb, jiffies
784 + msecs_to_jiffies(musb->a_wait_bcon));
785 break;
786 #endif /* HOST */
787 #ifdef CONFIG_USB_MUSB_OTG
788 case OTG_STATE_B_HOST:
789 /* REVISIT this behaves for "real disconnect"
790 * cases; make sure the other transitions from
791 * from B_HOST act right too. The B_HOST code
792 * in hnp_stop() is currently not used...
793 */
794 musb_root_disconnect(musb);
795 musb_to_hcd(musb)->self.is_b_host = 0;
796 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
797 MUSB_DEV_MODE(musb);
798 musb_g_disconnect(musb);
799 break;
800 case OTG_STATE_A_PERIPHERAL:
801 musb_hnp_stop(musb);
802 musb_root_disconnect(musb);
803 /* FALLTHROUGH */
804 case OTG_STATE_B_WAIT_ACON:
805 /* FALLTHROUGH */
806 #endif /* OTG */
807 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
808 case OTG_STATE_B_PERIPHERAL:
809 case OTG_STATE_B_IDLE:
810 musb_g_disconnect(musb);
811 break;
812 #endif /* GADGET */
813 default:
814 WARNING("unhandled DISCONNECT transition (%s)\n",
815 otg_state_string(musb));
816 break;
817 }
818 }
819
820 /* mentor saves a bit: bus reset and babble share the same irq.
821 * only host sees babble; only peripheral sees bus reset.
822 */
823 if (int_usb & MUSB_INTR_RESET) {
824 handled = IRQ_HANDLED;
825 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
826 /*
827 * Looks like non-HS BABBLE can be ignored, but
828 * HS BABBLE is an error condition. For HS the solution
829 * is to avoid babble in the first place and fix what
830 * caused BABBLE. When HS BABBLE happens we can only
831 * stop the session.
832 */
833 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
834 DBG(1, "BABBLE devctl: %02x\n", devctl);
835 else {
836 ERR("Stopping host session -- babble\n");
837 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
838 }
839 } else if (is_peripheral_capable()) {
840 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
841 switch (musb->xceiv->state) {
842 #ifdef CONFIG_USB_OTG
843 case OTG_STATE_A_SUSPEND:
844 /* We need to ignore disconnect on suspend
845 * otherwise tusb 2.0 won't reconnect after a
846 * power cycle, which breaks otg compliance.
847 */
848 musb->ignore_disconnect = 1;
849 musb_g_reset(musb);
850 /* FALLTHROUGH */
851 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
852 /* never use invalid T(a_wait_bcon) */
853 DBG(1, "HNP: in %s, %d msec timeout\n",
854 otg_state_string(musb),
855 TA_WAIT_BCON(musb));
856 mod_timer(&musb->otg_timer, jiffies
857 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
858 break;
859 case OTG_STATE_A_PERIPHERAL:
860 musb->ignore_disconnect = 0;
861 del_timer(&musb->otg_timer);
862 musb_g_reset(musb);
863 break;
864 case OTG_STATE_B_WAIT_ACON:
865 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
866 otg_state_string(musb));
867 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
868 musb_g_reset(musb);
869 break;
870 #endif
871 case OTG_STATE_B_IDLE:
872 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
873 /* FALLTHROUGH */
874 case OTG_STATE_B_PERIPHERAL:
875 musb_g_reset(musb);
876 break;
877 default:
878 DBG(1, "Unhandled BUS RESET as %s\n",
879 otg_state_string(musb));
880 }
881 }
882 }
883
884 #if 0
885 /* REVISIT ... this would be for multiplexing periodic endpoints, or
886 * supporting transfer phasing to prevent exceeding ISO bandwidth
887 * limits of a given frame or microframe.
888 *
889 * It's not needed for peripheral side, which dedicates endpoints;
890 * though it _might_ use SOF irqs for other purposes.
891 *
892 * And it's not currently needed for host side, which also dedicates
893 * endpoints, relies on TX/RX interval registers, and isn't claimed
894 * to support ISO transfers yet.
895 */
896 if (int_usb & MUSB_INTR_SOF) {
897 void __iomem *mbase = musb->mregs;
898 struct musb_hw_ep *ep;
899 u8 epnum;
900 u16 frame;
901
902 DBG(6, "START_OF_FRAME\n");
903 handled = IRQ_HANDLED;
904
905 /* start any periodic Tx transfers waiting for current frame */
906 frame = musb_readw(mbase, MUSB_FRAME);
907 ep = musb->endpoints;
908 for (epnum = 1; (epnum < musb->nr_endpoints)
909 && (musb->epmask >= (1 << epnum));
910 epnum++, ep++) {
911 /*
912 * FIXME handle framecounter wraps (12 bits)
913 * eliminate duplicated StartUrb logic
914 */
915 if (ep->dwWaitFrame >= frame) {
916 ep->dwWaitFrame = 0;
917 pr_debug("SOF --> periodic TX%s on %d\n",
918 ep->tx_channel ? " DMA" : "",
919 epnum);
920 if (!ep->tx_channel)
921 musb_h_tx_start(musb, epnum);
922 else
923 cppi_hostdma_start(musb, epnum);
924 }
925 } /* end of for loop */
926 }
927 #endif
928
929 schedule_work(&musb->irq_work);
930
931 return handled;
932 }
933
934 /*-------------------------------------------------------------------------*/
935
936 /*
937 * Program the HDRC to start (enable interrupts, dma, etc.).
938 */
939 void musb_start(struct musb *musb)
940 {
941 void __iomem *regs = musb->mregs;
942 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
943
944 DBG(2, "<== devctl %02x\n", devctl);
945
946 /* Set INT enable registers, enable interrupts */
947 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
948 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
949 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
950
951 musb_writeb(regs, MUSB_TESTMODE, 0);
952
953 /* put into basic highspeed mode and start session */
954 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
955 | MUSB_POWER_SOFTCONN
956 | MUSB_POWER_HSENAB
957 /* ENSUSPEND wedges tusb */
958 /* | MUSB_POWER_ENSUSPEND */
959 );
960
961 musb->is_active = 0;
962 devctl = musb_readb(regs, MUSB_DEVCTL);
963 devctl &= ~MUSB_DEVCTL_SESSION;
964
965 if (is_otg_enabled(musb)) {
966 /* session started after:
967 * (a) ID-grounded irq, host mode;
968 * (b) vbus present/connect IRQ, peripheral mode;
969 * (c) peripheral initiates, using SRP
970 */
971 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
972 musb->is_active = 1;
973 else
974 devctl |= MUSB_DEVCTL_SESSION;
975
976 } else if (is_host_enabled(musb)) {
977 /* assume ID pin is hard-wired to ground */
978 devctl |= MUSB_DEVCTL_SESSION;
979
980 } else /* peripheral is enabled */ {
981 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
982 musb->is_active = 1;
983 }
984 musb_platform_enable(musb);
985 musb_writeb(regs, MUSB_DEVCTL, devctl);
986 }
987
988
989 static void musb_generic_disable(struct musb *musb)
990 {
991 void __iomem *mbase = musb->mregs;
992 u16 temp;
993
994 /* disable interrupts */
995 musb_writeb(mbase, MUSB_INTRUSBE, 0);
996 musb_writew(mbase, MUSB_INTRTXE, 0);
997 musb_writew(mbase, MUSB_INTRRXE, 0);
998
999 /* off */
1000 musb_writeb(mbase, MUSB_DEVCTL, 0);
1001
1002 /* flush pending interrupts */
1003 temp = musb_readb(mbase, MUSB_INTRUSB);
1004 temp = musb_readw(mbase, MUSB_INTRTX);
1005 temp = musb_readw(mbase, MUSB_INTRRX);
1006
1007 }
1008
1009 /*
1010 * Make the HDRC stop (disable interrupts, etc.);
1011 * reversible by musb_start
1012 * called on gadget driver unregister
1013 * with controller locked, irqs blocked
1014 * acts as a NOP unless some role activated the hardware
1015 */
1016 void musb_stop(struct musb *musb)
1017 {
1018 /* stop IRQs, timers, ... */
1019 musb_platform_disable(musb);
1020 musb_generic_disable(musb);
1021 DBG(3, "HDRC disabled\n");
1022
1023 /* FIXME
1024 * - mark host and/or peripheral drivers unusable/inactive
1025 * - disable DMA (and enable it in HdrcStart)
1026 * - make sure we can musb_start() after musb_stop(); with
1027 * OTG mode, gadget driver module rmmod/modprobe cycles that
1028 * - ...
1029 */
1030 musb_platform_try_idle(musb, 0);
1031 }
1032
1033 static void musb_shutdown(struct platform_device *pdev)
1034 {
1035 struct musb *musb = dev_to_musb(&pdev->dev);
1036 unsigned long flags;
1037
1038 spin_lock_irqsave(&musb->lock, flags);
1039 musb_platform_disable(musb);
1040 musb_generic_disable(musb);
1041 spin_unlock_irqrestore(&musb->lock, flags);
1042
1043 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1044 usb_remove_hcd(musb_to_hcd(musb));
1045 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1046 musb_platform_exit(musb);
1047
1048 /* FIXME power down */
1049 }
1050
1051
1052 /*-------------------------------------------------------------------------*/
1053
1054 /*
1055 * The silicon either has hard-wired endpoint configurations, or else
1056 * "dynamic fifo" sizing. The driver has support for both, though at this
1057 * writing only the dynamic sizing is very well tested. Since we switched
1058 * away from compile-time hardware parameters, we can no longer rely on
1059 * dead code elimination to leave only the relevant one in the object file.
1060 *
1061 * We don't currently use dynamic fifo setup capability to do anything
1062 * more than selecting one of a bunch of predefined configurations.
1063 */
1064 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1065 || defined(CONFIG_USB_MUSB_AM35X)
1066 static ushort __initdata fifo_mode = 4;
1067 #elif defined(CONFIG_USB_MUSB_UX500)
1068 static ushort __initdata fifo_mode = 5;
1069 #else
1070 static ushort __initdata fifo_mode = 2;
1071 #endif
1072
1073 /* "modprobe ... fifo_mode=1" etc */
1074 module_param(fifo_mode, ushort, 0);
1075 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1076
1077 /*
1078 * tables defining fifo_mode values. define more if you like.
1079 * for host side, make sure both halves of ep1 are set up.
1080 */
1081
1082 /* mode 0 - fits in 2KB */
1083 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1084 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1087 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1088 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1089 };
1090
1091 /* mode 1 - fits in 4KB */
1092 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1093 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1094 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1095 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1096 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1097 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1098 };
1099
1100 /* mode 2 - fits in 4KB */
1101 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1102 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1107 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1108 };
1109
1110 /* mode 3 - fits in 4KB */
1111 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1112 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1113 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1114 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1117 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1118 };
1119
1120 /* mode 4 - fits in 16KB */
1121 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1122 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1123 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1124 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1125 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1126 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1127 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1128 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1129 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1130 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1131 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1132 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1133 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1134 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1141 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1142 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1143 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1144 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1145 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1146 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1147 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1148 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1149 };
1150
1151 /* mode 5 - fits in 8KB */
1152 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1153 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1154 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1155 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1156 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1157 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1158 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1159 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1160 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1161 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1162 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1163 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1164 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1165 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1166 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1167 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1168 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1169 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1170 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1171 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1172 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1173 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1174 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1175 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1176 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1177 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1178 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1179 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1180 };
1181
1182 /*
1183 * configure a fifo; for non-shared endpoints, this may be called
1184 * once for a tx fifo and once for an rx fifo.
1185 *
1186 * returns negative errno or offset for next fifo.
1187 */
1188 static int __init
1189 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1190 const struct musb_fifo_cfg *cfg, u16 offset)
1191 {
1192 void __iomem *mbase = musb->mregs;
1193 int size = 0;
1194 u16 maxpacket = cfg->maxpacket;
1195 u16 c_off = offset >> 3;
1196 u8 c_size;
1197
1198 /* expect hw_ep has already been zero-initialized */
1199
1200 size = ffs(max(maxpacket, (u16) 8)) - 1;
1201 maxpacket = 1 << size;
1202
1203 c_size = size - 3;
1204 if (cfg->mode == BUF_DOUBLE) {
1205 if ((offset + (maxpacket << 1)) >
1206 (1 << (musb->config->ram_bits + 2)))
1207 return -EMSGSIZE;
1208 c_size |= MUSB_FIFOSZ_DPB;
1209 } else {
1210 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1211 return -EMSGSIZE;
1212 }
1213
1214 /* configure the FIFO */
1215 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1216
1217 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1218 /* EP0 reserved endpoint for control, bidirectional;
1219 * EP1 reserved for bulk, two unidirection halves.
1220 */
1221 if (hw_ep->epnum == 1)
1222 musb->bulk_ep = hw_ep;
1223 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1224 #endif
1225 switch (cfg->style) {
1226 case FIFO_TX:
1227 musb_write_txfifosz(mbase, c_size);
1228 musb_write_txfifoadd(mbase, c_off);
1229 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1230 hw_ep->max_packet_sz_tx = maxpacket;
1231 break;
1232 case FIFO_RX:
1233 musb_write_rxfifosz(mbase, c_size);
1234 musb_write_rxfifoadd(mbase, c_off);
1235 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1236 hw_ep->max_packet_sz_rx = maxpacket;
1237 break;
1238 case FIFO_RXTX:
1239 musb_write_txfifosz(mbase, c_size);
1240 musb_write_txfifoadd(mbase, c_off);
1241 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1242 hw_ep->max_packet_sz_rx = maxpacket;
1243
1244 musb_write_rxfifosz(mbase, c_size);
1245 musb_write_rxfifoadd(mbase, c_off);
1246 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1247 hw_ep->max_packet_sz_tx = maxpacket;
1248
1249 hw_ep->is_shared_fifo = true;
1250 break;
1251 }
1252
1253 /* NOTE rx and tx endpoint irqs aren't managed separately,
1254 * which happens to be ok
1255 */
1256 musb->epmask |= (1 << hw_ep->epnum);
1257
1258 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1259 }
1260
1261 static struct musb_fifo_cfg __initdata ep0_cfg = {
1262 .style = FIFO_RXTX, .maxpacket = 64,
1263 };
1264
1265 static int __init ep_config_from_table(struct musb *musb)
1266 {
1267 const struct musb_fifo_cfg *cfg;
1268 unsigned i, n;
1269 int offset;
1270 struct musb_hw_ep *hw_ep = musb->endpoints;
1271
1272 if (musb->config->fifo_cfg) {
1273 cfg = musb->config->fifo_cfg;
1274 n = musb->config->fifo_cfg_size;
1275 goto done;
1276 }
1277
1278 switch (fifo_mode) {
1279 default:
1280 fifo_mode = 0;
1281 /* FALLTHROUGH */
1282 case 0:
1283 cfg = mode_0_cfg;
1284 n = ARRAY_SIZE(mode_0_cfg);
1285 break;
1286 case 1:
1287 cfg = mode_1_cfg;
1288 n = ARRAY_SIZE(mode_1_cfg);
1289 break;
1290 case 2:
1291 cfg = mode_2_cfg;
1292 n = ARRAY_SIZE(mode_2_cfg);
1293 break;
1294 case 3:
1295 cfg = mode_3_cfg;
1296 n = ARRAY_SIZE(mode_3_cfg);
1297 break;
1298 case 4:
1299 cfg = mode_4_cfg;
1300 n = ARRAY_SIZE(mode_4_cfg);
1301 break;
1302 case 5:
1303 cfg = mode_5_cfg;
1304 n = ARRAY_SIZE(mode_5_cfg);
1305 break;
1306 }
1307
1308 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1309 musb_driver_name, fifo_mode);
1310
1311
1312 done:
1313 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1314 /* assert(offset > 0) */
1315
1316 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1317 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1318 */
1319
1320 for (i = 0; i < n; i++) {
1321 u8 epn = cfg->hw_ep_num;
1322
1323 if (epn >= musb->config->num_eps) {
1324 pr_debug("%s: invalid ep %d\n",
1325 musb_driver_name, epn);
1326 return -EINVAL;
1327 }
1328 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1329 if (offset < 0) {
1330 pr_debug("%s: mem overrun, ep %d\n",
1331 musb_driver_name, epn);
1332 return -EINVAL;
1333 }
1334 epn++;
1335 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1336 }
1337
1338 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1339 musb_driver_name,
1340 n + 1, musb->config->num_eps * 2 - 1,
1341 offset, (1 << (musb->config->ram_bits + 2)));
1342
1343 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1344 if (!musb->bulk_ep) {
1345 pr_debug("%s: missing bulk\n", musb_driver_name);
1346 return -EINVAL;
1347 }
1348 #endif
1349
1350 return 0;
1351 }
1352
1353
1354 /*
1355 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1356 * @param musb the controller
1357 */
1358 static int __init ep_config_from_hw(struct musb *musb)
1359 {
1360 u8 epnum = 0;
1361 struct musb_hw_ep *hw_ep;
1362 void *mbase = musb->mregs;
1363 int ret = 0;
1364
1365 DBG(2, "<== static silicon ep config\n");
1366
1367 /* FIXME pick up ep0 maxpacket size */
1368
1369 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1370 musb_ep_select(mbase, epnum);
1371 hw_ep = musb->endpoints + epnum;
1372
1373 ret = musb_read_fifosize(musb, hw_ep, epnum);
1374 if (ret < 0)
1375 break;
1376
1377 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1378
1379 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1380 /* pick an RX/TX endpoint for bulk */
1381 if (hw_ep->max_packet_sz_tx < 512
1382 || hw_ep->max_packet_sz_rx < 512)
1383 continue;
1384
1385 /* REVISIT: this algorithm is lazy, we should at least
1386 * try to pick a double buffered endpoint.
1387 */
1388 if (musb->bulk_ep)
1389 continue;
1390 musb->bulk_ep = hw_ep;
1391 #endif
1392 }
1393
1394 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1395 if (!musb->bulk_ep) {
1396 pr_debug("%s: missing bulk\n", musb_driver_name);
1397 return -EINVAL;
1398 }
1399 #endif
1400
1401 return 0;
1402 }
1403
1404 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1405
1406 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1407 * configure endpoints, or take their config from silicon
1408 */
1409 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1410 {
1411 u8 reg;
1412 char *type;
1413 char aInfo[90], aRevision[32], aDate[12];
1414 void __iomem *mbase = musb->mregs;
1415 int status = 0;
1416 int i;
1417
1418 /* log core options (read using indexed model) */
1419 reg = musb_read_configdata(mbase);
1420
1421 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1422 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1423 strcat(aInfo, ", dyn FIFOs");
1424 musb->dyn_fifo = true;
1425 }
1426 if (reg & MUSB_CONFIGDATA_MPRXE) {
1427 strcat(aInfo, ", bulk combine");
1428 musb->bulk_combine = true;
1429 }
1430 if (reg & MUSB_CONFIGDATA_MPTXE) {
1431 strcat(aInfo, ", bulk split");
1432 musb->bulk_split = true;
1433 }
1434 if (reg & MUSB_CONFIGDATA_HBRXE) {
1435 strcat(aInfo, ", HB-ISO Rx");
1436 musb->hb_iso_rx = true;
1437 }
1438 if (reg & MUSB_CONFIGDATA_HBTXE) {
1439 strcat(aInfo, ", HB-ISO Tx");
1440 musb->hb_iso_tx = true;
1441 }
1442 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1443 strcat(aInfo, ", SoftConn");
1444
1445 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1446 musb_driver_name, reg, aInfo);
1447
1448 aDate[0] = 0;
1449 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1450 musb->is_multipoint = 1;
1451 type = "M";
1452 } else {
1453 musb->is_multipoint = 0;
1454 type = "";
1455 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1456 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1457 printk(KERN_ERR
1458 "%s: kernel must blacklist external hubs\n",
1459 musb_driver_name);
1460 #endif
1461 #endif
1462 }
1463
1464 /* log release info */
1465 musb->hwvers = musb_read_hwvers(mbase);
1466 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1467 MUSB_HWVERS_MINOR(musb->hwvers),
1468 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1469 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1470 musb_driver_name, type, aRevision, aDate);
1471
1472 /* configure ep0 */
1473 musb_configure_ep0(musb);
1474
1475 /* discover endpoint configuration */
1476 musb->nr_endpoints = 1;
1477 musb->epmask = 1;
1478
1479 if (musb->dyn_fifo)
1480 status = ep_config_from_table(musb);
1481 else
1482 status = ep_config_from_hw(musb);
1483
1484 if (status < 0)
1485 return status;
1486
1487 /* finish init, and print endpoint config */
1488 for (i = 0; i < musb->nr_endpoints; i++) {
1489 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1490
1491 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1492 #ifdef CONFIG_USB_MUSB_TUSB6010
1493 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1494 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1495 hw_ep->fifo_sync_va =
1496 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1497
1498 if (i == 0)
1499 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1500 else
1501 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1502 #endif
1503
1504 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1505 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1506 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1507 hw_ep->rx_reinit = 1;
1508 hw_ep->tx_reinit = 1;
1509 #endif
1510
1511 if (hw_ep->max_packet_sz_tx) {
1512 DBG(1,
1513 "%s: hw_ep %d%s, %smax %d\n",
1514 musb_driver_name, i,
1515 hw_ep->is_shared_fifo ? "shared" : "tx",
1516 hw_ep->tx_double_buffered
1517 ? "doublebuffer, " : "",
1518 hw_ep->max_packet_sz_tx);
1519 }
1520 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1521 DBG(1,
1522 "%s: hw_ep %d%s, %smax %d\n",
1523 musb_driver_name, i,
1524 "rx",
1525 hw_ep->rx_double_buffered
1526 ? "doublebuffer, " : "",
1527 hw_ep->max_packet_sz_rx);
1528 }
1529 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1530 DBG(1, "hw_ep %d not configured\n", i);
1531 }
1532
1533 return 0;
1534 }
1535
1536 /*-------------------------------------------------------------------------*/
1537
1538 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1539 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
1540 defined(CONFIG_ARCH_U5500)
1541
1542 static irqreturn_t generic_interrupt(int irq, void *__hci)
1543 {
1544 unsigned long flags;
1545 irqreturn_t retval = IRQ_NONE;
1546 struct musb *musb = __hci;
1547
1548 spin_lock_irqsave(&musb->lock, flags);
1549
1550 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1551 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1552 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1553
1554 if (musb->int_usb || musb->int_tx || musb->int_rx)
1555 retval = musb_interrupt(musb);
1556
1557 spin_unlock_irqrestore(&musb->lock, flags);
1558
1559 return retval;
1560 }
1561
1562 #else
1563 #define generic_interrupt NULL
1564 #endif
1565
1566 /*
1567 * handle all the irqs defined by the HDRC core. for now we expect: other
1568 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1569 * will be assigned, and the irq will already have been acked.
1570 *
1571 * called in irq context with spinlock held, irqs blocked
1572 */
1573 irqreturn_t musb_interrupt(struct musb *musb)
1574 {
1575 irqreturn_t retval = IRQ_NONE;
1576 u8 devctl, power;
1577 int ep_num;
1578 u32 reg;
1579
1580 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1581 power = musb_readb(musb->mregs, MUSB_POWER);
1582
1583 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1584 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1585 musb->int_usb, musb->int_tx, musb->int_rx);
1586
1587 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1588 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1589 if (!musb->gadget_driver) {
1590 DBG(5, "No gadget driver loaded\n");
1591 return IRQ_HANDLED;
1592 }
1593 #endif
1594
1595 /* the core can interrupt us for multiple reasons; docs have
1596 * a generic interrupt flowchart to follow
1597 */
1598 if (musb->int_usb)
1599 retval |= musb_stage0_irq(musb, musb->int_usb,
1600 devctl, power);
1601
1602 /* "stage 1" is handling endpoint irqs */
1603
1604 /* handle endpoint 0 first */
1605 if (musb->int_tx & 1) {
1606 if (devctl & MUSB_DEVCTL_HM)
1607 retval |= musb_h_ep0_irq(musb);
1608 else
1609 retval |= musb_g_ep0_irq(musb);
1610 }
1611
1612 /* RX on endpoints 1-15 */
1613 reg = musb->int_rx >> 1;
1614 ep_num = 1;
1615 while (reg) {
1616 if (reg & 1) {
1617 /* musb_ep_select(musb->mregs, ep_num); */
1618 /* REVISIT just retval = ep->rx_irq(...) */
1619 retval = IRQ_HANDLED;
1620 if (devctl & MUSB_DEVCTL_HM) {
1621 if (is_host_capable())
1622 musb_host_rx(musb, ep_num);
1623 } else {
1624 if (is_peripheral_capable())
1625 musb_g_rx(musb, ep_num);
1626 }
1627 }
1628
1629 reg >>= 1;
1630 ep_num++;
1631 }
1632
1633 /* TX on endpoints 1-15 */
1634 reg = musb->int_tx >> 1;
1635 ep_num = 1;
1636 while (reg) {
1637 if (reg & 1) {
1638 /* musb_ep_select(musb->mregs, ep_num); */
1639 /* REVISIT just retval |= ep->tx_irq(...) */
1640 retval = IRQ_HANDLED;
1641 if (devctl & MUSB_DEVCTL_HM) {
1642 if (is_host_capable())
1643 musb_host_tx(musb, ep_num);
1644 } else {
1645 if (is_peripheral_capable())
1646 musb_g_tx(musb, ep_num);
1647 }
1648 }
1649 reg >>= 1;
1650 ep_num++;
1651 }
1652
1653 return retval;
1654 }
1655
1656
1657 #ifndef CONFIG_MUSB_PIO_ONLY
1658 static int __initdata use_dma = 1;
1659
1660 /* "modprobe ... use_dma=0" etc */
1661 module_param(use_dma, bool, 0);
1662 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1663
1664 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1665 {
1666 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1667
1668 /* called with controller lock already held */
1669
1670 if (!epnum) {
1671 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1672 if (!is_cppi_enabled()) {
1673 /* endpoint 0 */
1674 if (devctl & MUSB_DEVCTL_HM)
1675 musb_h_ep0_irq(musb);
1676 else
1677 musb_g_ep0_irq(musb);
1678 }
1679 #endif
1680 } else {
1681 /* endpoints 1..15 */
1682 if (transmit) {
1683 if (devctl & MUSB_DEVCTL_HM) {
1684 if (is_host_capable())
1685 musb_host_tx(musb, epnum);
1686 } else {
1687 if (is_peripheral_capable())
1688 musb_g_tx(musb, epnum);
1689 }
1690 } else {
1691 /* receive */
1692 if (devctl & MUSB_DEVCTL_HM) {
1693 if (is_host_capable())
1694 musb_host_rx(musb, epnum);
1695 } else {
1696 if (is_peripheral_capable())
1697 musb_g_rx(musb, epnum);
1698 }
1699 }
1700 }
1701 }
1702
1703 #else
1704 #define use_dma 0
1705 #endif
1706
1707 /*-------------------------------------------------------------------------*/
1708
1709 #ifdef CONFIG_SYSFS
1710
1711 static ssize_t
1712 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1713 {
1714 struct musb *musb = dev_to_musb(dev);
1715 unsigned long flags;
1716 int ret = -EINVAL;
1717
1718 spin_lock_irqsave(&musb->lock, flags);
1719 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1720 spin_unlock_irqrestore(&musb->lock, flags);
1721
1722 return ret;
1723 }
1724
1725 static ssize_t
1726 musb_mode_store(struct device *dev, struct device_attribute *attr,
1727 const char *buf, size_t n)
1728 {
1729 struct musb *musb = dev_to_musb(dev);
1730 unsigned long flags;
1731 int status;
1732
1733 spin_lock_irqsave(&musb->lock, flags);
1734 if (sysfs_streq(buf, "host"))
1735 status = musb_platform_set_mode(musb, MUSB_HOST);
1736 else if (sysfs_streq(buf, "peripheral"))
1737 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1738 else if (sysfs_streq(buf, "otg"))
1739 status = musb_platform_set_mode(musb, MUSB_OTG);
1740 else
1741 status = -EINVAL;
1742 spin_unlock_irqrestore(&musb->lock, flags);
1743
1744 return (status == 0) ? n : status;
1745 }
1746 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1747
1748 static ssize_t
1749 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1750 const char *buf, size_t n)
1751 {
1752 struct musb *musb = dev_to_musb(dev);
1753 unsigned long flags;
1754 unsigned long val;
1755
1756 if (sscanf(buf, "%lu", &val) < 1) {
1757 dev_err(dev, "Invalid VBUS timeout ms value\n");
1758 return -EINVAL;
1759 }
1760
1761 spin_lock_irqsave(&musb->lock, flags);
1762 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1763 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1764 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1765 musb->is_active = 0;
1766 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1767 spin_unlock_irqrestore(&musb->lock, flags);
1768
1769 return n;
1770 }
1771
1772 static ssize_t
1773 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1774 {
1775 struct musb *musb = dev_to_musb(dev);
1776 unsigned long flags;
1777 unsigned long val;
1778 int vbus;
1779
1780 spin_lock_irqsave(&musb->lock, flags);
1781 val = musb->a_wait_bcon;
1782 /* FIXME get_vbus_status() is normally #defined as false...
1783 * and is effectively TUSB-specific.
1784 */
1785 vbus = musb_platform_get_vbus_status(musb);
1786 spin_unlock_irqrestore(&musb->lock, flags);
1787
1788 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1789 vbus ? "on" : "off", val);
1790 }
1791 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1792
1793 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1794
1795 /* Gadget drivers can't know that a host is connected so they might want
1796 * to start SRP, but users can. This allows userspace to trigger SRP.
1797 */
1798 static ssize_t
1799 musb_srp_store(struct device *dev, struct device_attribute *attr,
1800 const char *buf, size_t n)
1801 {
1802 struct musb *musb = dev_to_musb(dev);
1803 unsigned short srp;
1804
1805 if (sscanf(buf, "%hu", &srp) != 1
1806 || (srp != 1)) {
1807 dev_err(dev, "SRP: Value must be 1\n");
1808 return -EINVAL;
1809 }
1810
1811 if (srp == 1)
1812 musb_g_wakeup(musb);
1813
1814 return n;
1815 }
1816 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1817
1818 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1819
1820 static struct attribute *musb_attributes[] = {
1821 &dev_attr_mode.attr,
1822 &dev_attr_vbus.attr,
1823 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1824 &dev_attr_srp.attr,
1825 #endif
1826 NULL
1827 };
1828
1829 static const struct attribute_group musb_attr_group = {
1830 .attrs = musb_attributes,
1831 };
1832
1833 #endif /* sysfs */
1834
1835 /* Only used to provide driver mode change events */
1836 static void musb_irq_work(struct work_struct *data)
1837 {
1838 struct musb *musb = container_of(data, struct musb, irq_work);
1839 static int old_state;
1840
1841 if (musb->xceiv->state != old_state) {
1842 old_state = musb->xceiv->state;
1843 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1844 }
1845 }
1846
1847 /* --------------------------------------------------------------------------
1848 * Init support
1849 */
1850
1851 static struct musb *__init
1852 allocate_instance(struct device *dev,
1853 struct musb_hdrc_config *config, void __iomem *mbase)
1854 {
1855 struct musb *musb;
1856 struct musb_hw_ep *ep;
1857 int epnum;
1858 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1859 struct usb_hcd *hcd;
1860
1861 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1862 if (!hcd)
1863 return NULL;
1864 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1865
1866 musb = hcd_to_musb(hcd);
1867 INIT_LIST_HEAD(&musb->control);
1868 INIT_LIST_HEAD(&musb->in_bulk);
1869 INIT_LIST_HEAD(&musb->out_bulk);
1870
1871 hcd->uses_new_polling = 1;
1872
1873 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1874 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1875 #else
1876 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1877 if (!musb)
1878 return NULL;
1879 dev_set_drvdata(dev, musb);
1880
1881 #endif
1882
1883 musb->mregs = mbase;
1884 musb->ctrl_base = mbase;
1885 musb->nIrq = -ENODEV;
1886 musb->config = config;
1887 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1888 for (epnum = 0, ep = musb->endpoints;
1889 epnum < musb->config->num_eps;
1890 epnum++, ep++) {
1891 ep->musb = musb;
1892 ep->epnum = epnum;
1893 }
1894
1895 musb->controller = dev;
1896
1897 return musb;
1898 }
1899
1900 static void musb_free(struct musb *musb)
1901 {
1902 /* this has multiple entry modes. it handles fault cleanup after
1903 * probe(), where things may be partially set up, as well as rmmod
1904 * cleanup after everything's been de-activated.
1905 */
1906
1907 #ifdef CONFIG_SYSFS
1908 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1909 #endif
1910
1911 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1912 musb_gadget_cleanup(musb);
1913 #endif
1914
1915 if (musb->nIrq >= 0) {
1916 if (musb->irq_wake)
1917 disable_irq_wake(musb->nIrq);
1918 free_irq(musb->nIrq, musb);
1919 }
1920 if (is_dma_capable() && musb->dma_controller) {
1921 struct dma_controller *c = musb->dma_controller;
1922
1923 (void) c->stop(c);
1924 dma_controller_destroy(c);
1925 }
1926
1927 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1928 usb_put_hcd(musb_to_hcd(musb));
1929 #else
1930 kfree(musb);
1931 #endif
1932 }
1933
1934 /*
1935 * Perform generic per-controller initialization.
1936 *
1937 * @pDevice: the controller (already clocked, etc)
1938 * @nIrq: irq
1939 * @mregs: virtual address of controller registers,
1940 * not yet corrected for platform-specific offsets
1941 */
1942 static int __init
1943 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1944 {
1945 int status;
1946 struct musb *musb;
1947 struct musb_hdrc_platform_data *plat = dev->platform_data;
1948
1949 /* The driver might handle more features than the board; OK.
1950 * Fail when the board needs a feature that's not enabled.
1951 */
1952 if (!plat) {
1953 dev_dbg(dev, "no platform_data?\n");
1954 status = -ENODEV;
1955 goto fail0;
1956 }
1957
1958 switch (plat->mode) {
1959 case MUSB_HOST:
1960 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1961 break;
1962 #else
1963 goto bad_config;
1964 #endif
1965 case MUSB_PERIPHERAL:
1966 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1967 break;
1968 #else
1969 goto bad_config;
1970 #endif
1971 case MUSB_OTG:
1972 #ifdef CONFIG_USB_MUSB_OTG
1973 break;
1974 #else
1975 bad_config:
1976 #endif
1977 default:
1978 dev_err(dev, "incompatible Kconfig role setting\n");
1979 status = -EINVAL;
1980 goto fail0;
1981 }
1982
1983 /* allocate */
1984 musb = allocate_instance(dev, plat->config, ctrl);
1985 if (!musb) {
1986 status = -ENOMEM;
1987 goto fail0;
1988 }
1989
1990 spin_lock_init(&musb->lock);
1991 musb->board_mode = plat->mode;
1992 musb->board_set_power = plat->set_power;
1993 musb->min_power = plat->min_power;
1994 musb->ops = plat->platform_ops;
1995
1996 /* The musb_platform_init() call:
1997 * - adjusts musb->mregs and musb->isr if needed,
1998 * - may initialize an integrated tranceiver
1999 * - initializes musb->xceiv, usually by otg_get_transceiver()
2000 * - stops powering VBUS
2001 *
2002 * There are various transciever configurations. Blackfin,
2003 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2004 * external/discrete ones in various flavors (twl4030 family,
2005 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2006 */
2007 musb->isr = generic_interrupt;
2008 status = musb_platform_init(musb);
2009 if (status < 0)
2010 goto fail1;
2011
2012 if (!musb->isr) {
2013 status = -ENODEV;
2014 goto fail3;
2015 }
2016
2017 if (!musb->xceiv->io_ops) {
2018 musb->xceiv->io_priv = musb->mregs;
2019 musb->xceiv->io_ops = &musb_ulpi_access;
2020 }
2021
2022 #ifndef CONFIG_MUSB_PIO_ONLY
2023 if (use_dma && dev->dma_mask) {
2024 struct dma_controller *c;
2025
2026 c = dma_controller_create(musb, musb->mregs);
2027 musb->dma_controller = c;
2028 if (c)
2029 (void) c->start(c);
2030 }
2031 #endif
2032 /* ideally this would be abstracted in platform setup */
2033 if (!is_dma_capable() || !musb->dma_controller)
2034 dev->dma_mask = NULL;
2035
2036 /* be sure interrupts are disabled before connecting ISR */
2037 musb_platform_disable(musb);
2038 musb_generic_disable(musb);
2039
2040 /* setup musb parts of the core (especially endpoints) */
2041 status = musb_core_init(plat->config->multipoint
2042 ? MUSB_CONTROLLER_MHDRC
2043 : MUSB_CONTROLLER_HDRC, musb);
2044 if (status < 0)
2045 goto fail3;
2046
2047 #ifdef CONFIG_USB_MUSB_OTG
2048 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2049 #endif
2050
2051 /* Init IRQ workqueue before request_irq */
2052 INIT_WORK(&musb->irq_work, musb_irq_work);
2053
2054 /* attach to the IRQ */
2055 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2056 dev_err(dev, "request_irq %d failed!\n", nIrq);
2057 status = -ENODEV;
2058 goto fail3;
2059 }
2060 musb->nIrq = nIrq;
2061 /* FIXME this handles wakeup irqs wrong */
2062 if (enable_irq_wake(nIrq) == 0) {
2063 musb->irq_wake = 1;
2064 device_init_wakeup(dev, 1);
2065 } else {
2066 musb->irq_wake = 0;
2067 }
2068
2069 /* host side needs more setup */
2070 if (is_host_enabled(musb)) {
2071 struct usb_hcd *hcd = musb_to_hcd(musb);
2072
2073 otg_set_host(musb->xceiv, &hcd->self);
2074
2075 if (is_otg_enabled(musb))
2076 hcd->self.otg_port = 1;
2077 musb->xceiv->host = &hcd->self;
2078 hcd->power_budget = 2 * (plat->power ? : 250);
2079
2080 /* program PHY to use external vBus if required */
2081 if (plat->extvbus) {
2082 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2083 busctl |= MUSB_ULPI_USE_EXTVBUS;
2084 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2085 }
2086 }
2087
2088 /* For the host-only role, we can activate right away.
2089 * (We expect the ID pin to be forcibly grounded!!)
2090 * Otherwise, wait till the gadget driver hooks up.
2091 */
2092 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2093 struct usb_hcd *hcd = musb_to_hcd(musb);
2094
2095 MUSB_HST_MODE(musb);
2096 musb->xceiv->default_a = 1;
2097 musb->xceiv->state = OTG_STATE_A_IDLE;
2098
2099 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2100
2101 hcd->self.uses_pio_for_control = 1;
2102 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2103 "HOST", status,
2104 musb_readb(musb->mregs, MUSB_DEVCTL),
2105 (musb_readb(musb->mregs, MUSB_DEVCTL)
2106 & MUSB_DEVCTL_BDEVICE
2107 ? 'B' : 'A'));
2108
2109 } else /* peripheral is enabled */ {
2110 MUSB_DEV_MODE(musb);
2111 musb->xceiv->default_a = 0;
2112 musb->xceiv->state = OTG_STATE_B_IDLE;
2113
2114 status = musb_gadget_setup(musb);
2115
2116 DBG(1, "%s mode, status %d, dev%02x\n",
2117 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2118 status,
2119 musb_readb(musb->mregs, MUSB_DEVCTL));
2120
2121 }
2122 if (status < 0)
2123 goto fail3;
2124
2125 status = musb_init_debugfs(musb);
2126 if (status < 0)
2127 goto fail4;
2128
2129 #ifdef CONFIG_SYSFS
2130 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2131 if (status)
2132 goto fail5;
2133 #endif
2134
2135 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2136 ({char *s;
2137 switch (musb->board_mode) {
2138 case MUSB_HOST: s = "Host"; break;
2139 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2140 default: s = "OTG"; break;
2141 }; s; }),
2142 ctrl,
2143 (is_dma_capable() && musb->dma_controller)
2144 ? "DMA" : "PIO",
2145 musb->nIrq);
2146
2147 return 0;
2148
2149 fail5:
2150 musb_exit_debugfs(musb);
2151
2152 fail4:
2153 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2154 usb_remove_hcd(musb_to_hcd(musb));
2155 else
2156 musb_gadget_cleanup(musb);
2157
2158 fail3:
2159 if (musb->irq_wake)
2160 device_init_wakeup(dev, 0);
2161 musb_platform_exit(musb);
2162
2163 fail1:
2164 dev_err(musb->controller,
2165 "musb_init_controller failed with status %d\n", status);
2166
2167 musb_free(musb);
2168
2169 fail0:
2170
2171 return status;
2172
2173 }
2174
2175 /*-------------------------------------------------------------------------*/
2176
2177 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2178 * bridge to a platform device; this driver then suffices.
2179 */
2180
2181 #ifndef CONFIG_MUSB_PIO_ONLY
2182 static u64 *orig_dma_mask;
2183 #endif
2184
2185 static int __init musb_probe(struct platform_device *pdev)
2186 {
2187 struct device *dev = &pdev->dev;
2188 int irq = platform_get_irq_byname(pdev, "mc");
2189 int status;
2190 struct resource *iomem;
2191 void __iomem *base;
2192
2193 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2194 if (!iomem || irq == 0)
2195 return -ENODEV;
2196
2197 base = ioremap(iomem->start, resource_size(iomem));
2198 if (!base) {
2199 dev_err(dev, "ioremap failed\n");
2200 return -ENOMEM;
2201 }
2202
2203 #ifndef CONFIG_MUSB_PIO_ONLY
2204 /* clobbered by use_dma=n */
2205 orig_dma_mask = dev->dma_mask;
2206 #endif
2207 status = musb_init_controller(dev, irq, base);
2208 if (status < 0)
2209 iounmap(base);
2210
2211 return status;
2212 }
2213
2214 static int __exit musb_remove(struct platform_device *pdev)
2215 {
2216 struct musb *musb = dev_to_musb(&pdev->dev);
2217 void __iomem *ctrl_base = musb->ctrl_base;
2218
2219 /* this gets called on rmmod.
2220 * - Host mode: host may still be active
2221 * - Peripheral mode: peripheral is deactivated (or never-activated)
2222 * - OTG mode: both roles are deactivated (or never-activated)
2223 */
2224 musb_exit_debugfs(musb);
2225 musb_shutdown(pdev);
2226
2227 musb_free(musb);
2228 iounmap(ctrl_base);
2229 device_init_wakeup(&pdev->dev, 0);
2230 #ifndef CONFIG_MUSB_PIO_ONLY
2231 pdev->dev.dma_mask = orig_dma_mask;
2232 #endif
2233 return 0;
2234 }
2235
2236 #ifdef CONFIG_PM
2237
2238 static void musb_save_context(struct musb *musb)
2239 {
2240 int i;
2241 void __iomem *musb_base = musb->mregs;
2242 void __iomem *epio;
2243
2244 if (is_host_enabled(musb)) {
2245 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2246 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2247 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2248 }
2249 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2250 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2251 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2252 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2253 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2254 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2255
2256 for (i = 0; i < musb->config->num_eps; ++i) {
2257 epio = musb->endpoints[i].regs;
2258 musb->context.index_regs[i].txmaxp =
2259 musb_readw(epio, MUSB_TXMAXP);
2260 musb->context.index_regs[i].txcsr =
2261 musb_readw(epio, MUSB_TXCSR);
2262 musb->context.index_regs[i].rxmaxp =
2263 musb_readw(epio, MUSB_RXMAXP);
2264 musb->context.index_regs[i].rxcsr =
2265 musb_readw(epio, MUSB_RXCSR);
2266
2267 if (musb->dyn_fifo) {
2268 musb->context.index_regs[i].txfifoadd =
2269 musb_read_txfifoadd(musb_base);
2270 musb->context.index_regs[i].rxfifoadd =
2271 musb_read_rxfifoadd(musb_base);
2272 musb->context.index_regs[i].txfifosz =
2273 musb_read_txfifosz(musb_base);
2274 musb->context.index_regs[i].rxfifosz =
2275 musb_read_rxfifosz(musb_base);
2276 }
2277 if (is_host_enabled(musb)) {
2278 musb->context.index_regs[i].txtype =
2279 musb_readb(epio, MUSB_TXTYPE);
2280 musb->context.index_regs[i].txinterval =
2281 musb_readb(epio, MUSB_TXINTERVAL);
2282 musb->context.index_regs[i].rxtype =
2283 musb_readb(epio, MUSB_RXTYPE);
2284 musb->context.index_regs[i].rxinterval =
2285 musb_readb(epio, MUSB_RXINTERVAL);
2286
2287 musb->context.index_regs[i].txfunaddr =
2288 musb_read_txfunaddr(musb_base, i);
2289 musb->context.index_regs[i].txhubaddr =
2290 musb_read_txhubaddr(musb_base, i);
2291 musb->context.index_regs[i].txhubport =
2292 musb_read_txhubport(musb_base, i);
2293
2294 musb->context.index_regs[i].rxfunaddr =
2295 musb_read_rxfunaddr(musb_base, i);
2296 musb->context.index_regs[i].rxhubaddr =
2297 musb_read_rxhubaddr(musb_base, i);
2298 musb->context.index_regs[i].rxhubport =
2299 musb_read_rxhubport(musb_base, i);
2300 }
2301 }
2302 }
2303
2304 static void musb_restore_context(struct musb *musb)
2305 {
2306 int i;
2307 void __iomem *musb_base = musb->mregs;
2308 void __iomem *ep_target_regs;
2309 void __iomem *epio;
2310
2311 if (is_host_enabled(musb)) {
2312 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2313 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2314 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2315 }
2316 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2317 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2318 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2319 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2320 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2321
2322 for (i = 0; i < musb->config->num_eps; ++i) {
2323 epio = musb->endpoints[i].regs;
2324 musb_writew(epio, MUSB_TXMAXP,
2325 musb->context.index_regs[i].txmaxp);
2326 musb_writew(epio, MUSB_TXCSR,
2327 musb->context.index_regs[i].txcsr);
2328 musb_writew(epio, MUSB_RXMAXP,
2329 musb->context.index_regs[i].rxmaxp);
2330 musb_writew(epio, MUSB_RXCSR,
2331 musb->context.index_regs[i].rxcsr);
2332
2333 if (musb->dyn_fifo) {
2334 musb_write_txfifosz(musb_base,
2335 musb->context.index_regs[i].txfifosz);
2336 musb_write_rxfifosz(musb_base,
2337 musb->context.index_regs[i].rxfifosz);
2338 musb_write_txfifoadd(musb_base,
2339 musb->context.index_regs[i].txfifoadd);
2340 musb_write_rxfifoadd(musb_base,
2341 musb->context.index_regs[i].rxfifoadd);
2342 }
2343
2344 if (is_host_enabled(musb)) {
2345 musb_writeb(epio, MUSB_TXTYPE,
2346 musb->context.index_regs[i].txtype);
2347 musb_writeb(epio, MUSB_TXINTERVAL,
2348 musb->context.index_regs[i].txinterval);
2349 musb_writeb(epio, MUSB_RXTYPE,
2350 musb->context.index_regs[i].rxtype);
2351 musb_writeb(epio, MUSB_RXINTERVAL,
2352
2353 musb->context.index_regs[i].rxinterval);
2354 musb_write_txfunaddr(musb_base, i,
2355 musb->context.index_regs[i].txfunaddr);
2356 musb_write_txhubaddr(musb_base, i,
2357 musb->context.index_regs[i].txhubaddr);
2358 musb_write_txhubport(musb_base, i,
2359 musb->context.index_regs[i].txhubport);
2360
2361 ep_target_regs =
2362 musb_read_target_reg_base(i, musb_base);
2363
2364 musb_write_rxfunaddr(ep_target_regs,
2365 musb->context.index_regs[i].rxfunaddr);
2366 musb_write_rxhubaddr(ep_target_regs,
2367 musb->context.index_regs[i].rxhubaddr);
2368 musb_write_rxhubport(ep_target_regs,
2369 musb->context.index_regs[i].rxhubport);
2370 }
2371 }
2372 }
2373
2374 static int musb_suspend(struct device *dev)
2375 {
2376 struct platform_device *pdev = to_platform_device(dev);
2377 unsigned long flags;
2378 struct musb *musb = dev_to_musb(&pdev->dev);
2379
2380 spin_lock_irqsave(&musb->lock, flags);
2381
2382 if (is_peripheral_active(musb)) {
2383 /* FIXME force disconnect unless we know USB will wake
2384 * the system up quickly enough to respond ...
2385 */
2386 } else if (is_host_active(musb)) {
2387 /* we know all the children are suspended; sometimes
2388 * they will even be wakeup-enabled.
2389 */
2390 }
2391
2392 musb_save_context(musb);
2393
2394 spin_unlock_irqrestore(&musb->lock, flags);
2395 return 0;
2396 }
2397
2398 static int musb_resume_noirq(struct device *dev)
2399 {
2400 struct platform_device *pdev = to_platform_device(dev);
2401 struct musb *musb = dev_to_musb(&pdev->dev);
2402
2403 musb_restore_context(musb);
2404
2405 /* for static cmos like DaVinci, register values were preserved
2406 * unless for some reason the whole soc powered down or the USB
2407 * module got reset through the PSC (vs just being disabled).
2408 */
2409 return 0;
2410 }
2411
2412 static const struct dev_pm_ops musb_dev_pm_ops = {
2413 .suspend = musb_suspend,
2414 .resume_noirq = musb_resume_noirq,
2415 };
2416
2417 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2418 #else
2419 #define MUSB_DEV_PM_OPS NULL
2420 #endif
2421
2422 static struct platform_driver musb_driver = {
2423 .driver = {
2424 .name = (char *)musb_driver_name,
2425 .bus = &platform_bus_type,
2426 .owner = THIS_MODULE,
2427 .pm = MUSB_DEV_PM_OPS,
2428 },
2429 .remove = __exit_p(musb_remove),
2430 .shutdown = musb_shutdown,
2431 };
2432
2433 /*-------------------------------------------------------------------------*/
2434
2435 static int __init musb_init(void)
2436 {
2437 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2438 if (usb_disabled())
2439 return 0;
2440 #endif
2441
2442 pr_info("%s: version " MUSB_VERSION ", "
2443 #ifdef CONFIG_MUSB_PIO_ONLY
2444 "pio"
2445 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2446 "cppi-dma"
2447 #elif defined(CONFIG_USB_INVENTRA_DMA)
2448 "musb-dma"
2449 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2450 "tusb-omap-dma"
2451 #else
2452 "?dma?"
2453 #endif
2454 ", "
2455 #ifdef CONFIG_USB_MUSB_OTG
2456 "otg (peripheral+host)"
2457 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2458 "peripheral"
2459 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2460 "host"
2461 #endif
2462 ", debug=%d\n",
2463 musb_driver_name, musb_debug);
2464 return platform_driver_probe(&musb_driver, musb_probe);
2465 }
2466
2467 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2468 * and before usb gadget and host-side drivers start to register
2469 */
2470 fs_initcall(musb_init);
2471
2472 static void __exit musb_cleanup(void)
2473 {
2474 platform_driver_unregister(&musb_driver);
2475 }
2476 module_exit(musb_cleanup);
linux-next