1 MPC5121 PSC Device Tree Bindings
6 For PSC in UART mode the needed PSC serial devices
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is requered there:
11 fsl,mpc5121-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
16 - cell-index : Index of the PSC in hardware
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
19 PSC FIFO Controller and b is a field that represents an
20 encoding of the sense and level information for the interrupt.
21 - interrupt-parent : the phandle for the interrupt controller that
22 services interrupts for this device.
24 Recommended properties :
25 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
26 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
29 fsl,mpc5121-psc-fifo node
30 -------------------------
33 - compatible : Should be "fsl,mpc5121-psc-fifo"
34 - reg : Offset and length of the register set for the PSC
36 - interrupts : <a b> where a is the interrupt number of the
37 PSC FIFO Controller and b is a field that represents an
38 encoding of the sense and level information for the interrupt.
39 - interrupt-parent : the phandle for the interrupt controller that
40 services interrupts for this device.
43 Example for a board using PSC0 and PSC1 devices in serial mode:
46 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
48 reg = <0x11000 0x100>;
49 interrupts = <40 0x8>;
50 interrupt-parent = < &ipic >;
51 fsl,rx-fifo-size = <16>;
52 fsl,tx-fifo-size = <16>;
56 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
58 reg = <0x11100 0x100>;
59 interrupts = <40 0x8>;
60 interrupt-parent = < &ipic >;
61 fsl,rx-fifo-size = <16>;
62 fsl,tx-fifo-size = <16>;
66 compatible = "fsl,mpc5121-psc-fifo";
67 reg = <0x11f00 0x100>;
68 interrupts = <40 0x8>;
69 interrupt-parent = < &ipic >;