2 * ARMv6 Performance counter handling code.
4 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
6 * ARMv6 has 2 configurable performance counters and a single cycle counter.
7 * They all share a single reset bit but can be written to zero so we can use
10 * The counters can't be individually enabled or disabled so when we remove
11 * one event and replace it with another we could get spurious counts from the
12 * wrong event. However, we can take advantage of the fact that the
13 * performance counters can export events to the event bus, and the event bus
14 * itself can be monitored. This requires that we *don't* export the events to
15 * the event bus. The procedure for disabling a configurable counter is:
16 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
17 * effectively stops the counter from counting.
18 * - disable the counter's interrupt generation (each counter has it's
19 * own interrupt enable bit).
20 * Once stopped, the counter value can be written as 0 to reset.
22 * To enable a counter:
23 * - enable the counter's interrupt generation.
24 * - set the new event type.
26 * Note: the dedicated cycle counter only counts cycles and can't be
27 * enabled/disabled independently of the others. When we want to disable the
28 * cycle counter, we have to just disable the interrupt reporting and start
29 * ignoring that counter. When re-enabling, we have to reset the value and
30 * enable the interrupt.
33 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
34 enum armv6_perf_types
{
35 ARMV6_PERFCTR_ICACHE_MISS
= 0x0,
36 ARMV6_PERFCTR_IBUF_STALL
= 0x1,
37 ARMV6_PERFCTR_DDEP_STALL
= 0x2,
38 ARMV6_PERFCTR_ITLB_MISS
= 0x3,
39 ARMV6_PERFCTR_DTLB_MISS
= 0x4,
40 ARMV6_PERFCTR_BR_EXEC
= 0x5,
41 ARMV6_PERFCTR_BR_MISPREDICT
= 0x6,
42 ARMV6_PERFCTR_INSTR_EXEC
= 0x7,
43 ARMV6_PERFCTR_DCACHE_HIT
= 0x9,
44 ARMV6_PERFCTR_DCACHE_ACCESS
= 0xA,
45 ARMV6_PERFCTR_DCACHE_MISS
= 0xB,
46 ARMV6_PERFCTR_DCACHE_WBACK
= 0xC,
47 ARMV6_PERFCTR_SW_PC_CHANGE
= 0xD,
48 ARMV6_PERFCTR_MAIN_TLB_MISS
= 0xF,
49 ARMV6_PERFCTR_EXPL_D_ACCESS
= 0x10,
50 ARMV6_PERFCTR_LSU_FULL_STALL
= 0x11,
51 ARMV6_PERFCTR_WBUF_DRAINED
= 0x12,
52 ARMV6_PERFCTR_CPU_CYCLES
= 0xFF,
53 ARMV6_PERFCTR_NOP
= 0x20,
57 ARMV6_CYCLE_COUNTER
= 1,
63 * The hardware events that we support. We do support cache operations but
64 * we have harvard caches and no way to combine instruction and data
65 * accesses/misses in hardware.
67 static const unsigned armv6_perf_map
[PERF_COUNT_HW_MAX
] = {
68 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV6_PERFCTR_CPU_CYCLES
,
69 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV6_PERFCTR_INSTR_EXEC
,
70 [PERF_COUNT_HW_CACHE_REFERENCES
] = HW_OP_UNSUPPORTED
,
71 [PERF_COUNT_HW_CACHE_MISSES
] = HW_OP_UNSUPPORTED
,
72 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV6_PERFCTR_BR_EXEC
,
73 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV6_PERFCTR_BR_MISPREDICT
,
74 [PERF_COUNT_HW_BUS_CYCLES
] = HW_OP_UNSUPPORTED
,
77 static const unsigned armv6_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
78 [PERF_COUNT_HW_CACHE_OP_MAX
]
79 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
82 * The performance counters don't differentiate between read
83 * and write accesses/misses so this isn't strictly correct,
84 * but it's the best we can do. Writes and reads get
88 [C(RESULT_ACCESS
)] = ARMV6_PERFCTR_DCACHE_ACCESS
,
89 [C(RESULT_MISS
)] = ARMV6_PERFCTR_DCACHE_MISS
,
92 [C(RESULT_ACCESS
)] = ARMV6_PERFCTR_DCACHE_ACCESS
,
93 [C(RESULT_MISS
)] = ARMV6_PERFCTR_DCACHE_MISS
,
96 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
97 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
102 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
103 [C(RESULT_MISS
)] = ARMV6_PERFCTR_ICACHE_MISS
,
106 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
107 [C(RESULT_MISS
)] = ARMV6_PERFCTR_ICACHE_MISS
,
110 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
111 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
116 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
117 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
120 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
121 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
124 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
125 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
130 * The ARM performance counters can count micro DTLB misses,
131 * micro ITLB misses and main TLB misses. There isn't an event
132 * for TLB misses, so use the micro misses here and if users
133 * want the main TLB misses they can use a raw counter.
136 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
137 [C(RESULT_MISS
)] = ARMV6_PERFCTR_DTLB_MISS
,
140 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
141 [C(RESULT_MISS
)] = ARMV6_PERFCTR_DTLB_MISS
,
144 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
145 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
150 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
151 [C(RESULT_MISS
)] = ARMV6_PERFCTR_ITLB_MISS
,
154 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
155 [C(RESULT_MISS
)] = ARMV6_PERFCTR_ITLB_MISS
,
158 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
159 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
164 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
165 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
168 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
169 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
172 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
173 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
178 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
179 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
182 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
183 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
186 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
187 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
192 enum armv6mpcore_perf_types
{
193 ARMV6MPCORE_PERFCTR_ICACHE_MISS
= 0x0,
194 ARMV6MPCORE_PERFCTR_IBUF_STALL
= 0x1,
195 ARMV6MPCORE_PERFCTR_DDEP_STALL
= 0x2,
196 ARMV6MPCORE_PERFCTR_ITLB_MISS
= 0x3,
197 ARMV6MPCORE_PERFCTR_DTLB_MISS
= 0x4,
198 ARMV6MPCORE_PERFCTR_BR_EXEC
= 0x5,
199 ARMV6MPCORE_PERFCTR_BR_NOTPREDICT
= 0x6,
200 ARMV6MPCORE_PERFCTR_BR_MISPREDICT
= 0x7,
201 ARMV6MPCORE_PERFCTR_INSTR_EXEC
= 0x8,
202 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS
= 0xA,
203 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS
= 0xB,
204 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS
= 0xC,
205 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS
= 0xD,
206 ARMV6MPCORE_PERFCTR_DCACHE_EVICTION
= 0xE,
207 ARMV6MPCORE_PERFCTR_SW_PC_CHANGE
= 0xF,
208 ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS
= 0x10,
209 ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS
= 0x11,
210 ARMV6MPCORE_PERFCTR_LSU_FULL_STALL
= 0x12,
211 ARMV6MPCORE_PERFCTR_WBUF_DRAINED
= 0x13,
212 ARMV6MPCORE_PERFCTR_CPU_CYCLES
= 0xFF,
216 * The hardware events that we support. We do support cache operations but
217 * we have harvard caches and no way to combine instruction and data
218 * accesses/misses in hardware.
220 static const unsigned armv6mpcore_perf_map
[PERF_COUNT_HW_MAX
] = {
221 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV6MPCORE_PERFCTR_CPU_CYCLES
,
222 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV6MPCORE_PERFCTR_INSTR_EXEC
,
223 [PERF_COUNT_HW_CACHE_REFERENCES
] = HW_OP_UNSUPPORTED
,
224 [PERF_COUNT_HW_CACHE_MISSES
] = HW_OP_UNSUPPORTED
,
225 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV6MPCORE_PERFCTR_BR_EXEC
,
226 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT
,
227 [PERF_COUNT_HW_BUS_CYCLES
] = HW_OP_UNSUPPORTED
,
230 static const unsigned armv6mpcore_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
231 [PERF_COUNT_HW_CACHE_OP_MAX
]
232 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
236 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS
,
238 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS
,
242 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS
,
244 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS
,
247 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
248 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
253 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
254 [C(RESULT_MISS
)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS
,
257 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
258 [C(RESULT_MISS
)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS
,
261 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
262 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
267 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
268 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
271 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
272 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
275 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
276 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
281 * The ARM performance counters can count micro DTLB misses,
282 * micro ITLB misses and main TLB misses. There isn't an event
283 * for TLB misses, so use the micro misses here and if users
284 * want the main TLB misses they can use a raw counter.
287 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
288 [C(RESULT_MISS
)] = ARMV6MPCORE_PERFCTR_DTLB_MISS
,
291 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
292 [C(RESULT_MISS
)] = ARMV6MPCORE_PERFCTR_DTLB_MISS
,
295 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
296 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
301 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
302 [C(RESULT_MISS
)] = ARMV6MPCORE_PERFCTR_ITLB_MISS
,
305 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
306 [C(RESULT_MISS
)] = ARMV6MPCORE_PERFCTR_ITLB_MISS
,
309 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
310 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
315 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
316 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
319 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
320 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
323 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
324 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
329 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
330 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
333 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
334 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
337 [C(RESULT_ACCESS
)] = CACHE_OP_UNSUPPORTED
,
338 [C(RESULT_MISS
)] = CACHE_OP_UNSUPPORTED
,
343 static inline unsigned long
344 armv6_pmcr_read(void)
347 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val
));
352 armv6_pmcr_write(unsigned long val
)
354 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val
));
357 #define ARMV6_PMCR_ENABLE (1 << 0)
358 #define ARMV6_PMCR_CTR01_RESET (1 << 1)
359 #define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
360 #define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
361 #define ARMV6_PMCR_COUNT0_IEN (1 << 4)
362 #define ARMV6_PMCR_COUNT1_IEN (1 << 5)
363 #define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
364 #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
365 #define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
366 #define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
367 #define ARMV6_PMCR_EVT_COUNT0_SHIFT 20
368 #define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
369 #define ARMV6_PMCR_EVT_COUNT1_SHIFT 12
370 #define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
372 #define ARMV6_PMCR_OVERFLOWED_MASK \
373 (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
374 ARMV6_PMCR_CCOUNT_OVERFLOW)
377 armv6_pmcr_has_overflowed(unsigned long pmcr
)
379 return pmcr
& ARMV6_PMCR_OVERFLOWED_MASK
;
383 armv6_pmcr_counter_has_overflowed(unsigned long pmcr
,
384 enum armv6_counters counter
)
388 if (ARMV6_CYCLE_COUNTER
== counter
)
389 ret
= pmcr
& ARMV6_PMCR_CCOUNT_OVERFLOW
;
390 else if (ARMV6_COUNTER0
== counter
)
391 ret
= pmcr
& ARMV6_PMCR_COUNT0_OVERFLOW
;
392 else if (ARMV6_COUNTER1
== counter
)
393 ret
= pmcr
& ARMV6_PMCR_COUNT1_OVERFLOW
;
395 WARN_ONCE(1, "invalid counter number (%d)\n", counter
);
401 armv6pmu_read_counter(int counter
)
403 unsigned long value
= 0;
405 if (ARMV6_CYCLE_COUNTER
== counter
)
406 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value
));
407 else if (ARMV6_COUNTER0
== counter
)
408 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value
));
409 else if (ARMV6_COUNTER1
== counter
)
410 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value
));
412 WARN_ONCE(1, "invalid counter number (%d)\n", counter
);
418 armv6pmu_write_counter(int counter
,
421 if (ARMV6_CYCLE_COUNTER
== counter
)
422 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value
));
423 else if (ARMV6_COUNTER0
== counter
)
424 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value
));
425 else if (ARMV6_COUNTER1
== counter
)
426 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value
));
428 WARN_ONCE(1, "invalid counter number (%d)\n", counter
);
432 armv6pmu_enable_event(struct hw_perf_event
*hwc
,
435 unsigned long val
, mask
, evt
, flags
;
437 if (ARMV6_CYCLE_COUNTER
== idx
) {
439 evt
= ARMV6_PMCR_CCOUNT_IEN
;
440 } else if (ARMV6_COUNTER0
== idx
) {
441 mask
= ARMV6_PMCR_EVT_COUNT0_MASK
;
442 evt
= (hwc
->config_base
<< ARMV6_PMCR_EVT_COUNT0_SHIFT
) |
443 ARMV6_PMCR_COUNT0_IEN
;
444 } else if (ARMV6_COUNTER1
== idx
) {
445 mask
= ARMV6_PMCR_EVT_COUNT1_MASK
;
446 evt
= (hwc
->config_base
<< ARMV6_PMCR_EVT_COUNT1_SHIFT
) |
447 ARMV6_PMCR_COUNT1_IEN
;
449 WARN_ONCE(1, "invalid counter number (%d)\n", idx
);
454 * Mask out the current event and set the counter to count the event
455 * that we're interested in.
457 raw_spin_lock_irqsave(&pmu_lock
, flags
);
458 val
= armv6_pmcr_read();
461 armv6_pmcr_write(val
);
462 raw_spin_unlock_irqrestore(&pmu_lock
, flags
);
466 armv6pmu_handle_irq(int irq_num
,
469 unsigned long pmcr
= armv6_pmcr_read();
470 struct perf_sample_data data
;
471 struct cpu_hw_events
*cpuc
;
472 struct pt_regs
*regs
;
475 if (!armv6_pmcr_has_overflowed(pmcr
))
478 regs
= get_irq_regs();
481 * The interrupts are cleared by writing the overflow flags back to
482 * the control register. All of the other bits don't have any effect
483 * if they are rewritten, so write the whole value back.
485 armv6_pmcr_write(pmcr
);
487 perf_sample_data_init(&data
, 0);
489 cpuc
= &__get_cpu_var(cpu_hw_events
);
490 for (idx
= 0; idx
<= armpmu
->num_events
; ++idx
) {
491 struct perf_event
*event
= cpuc
->events
[idx
];
492 struct hw_perf_event
*hwc
;
494 if (!test_bit(idx
, cpuc
->active_mask
))
498 * We have a single interrupt for all counters. Check that
499 * each counter has overflowed before we process it.
501 if (!armv6_pmcr_counter_has_overflowed(pmcr
, idx
))
505 armpmu_event_update(event
, hwc
, idx
, 1);
506 data
.period
= event
->hw
.last_period
;
507 if (!armpmu_event_set_period(event
, hwc
, idx
))
510 if (perf_event_overflow(event
, &data
, regs
))
511 armpmu
->disable(hwc
, idx
);
515 * Handle the pending perf events.
517 * Note: this call *must* be run with interrupts disabled. For
518 * platforms that can have the PMU interrupts raised as an NMI, this
529 unsigned long flags
, val
;
531 raw_spin_lock_irqsave(&pmu_lock
, flags
);
532 val
= armv6_pmcr_read();
533 val
|= ARMV6_PMCR_ENABLE
;
534 armv6_pmcr_write(val
);
535 raw_spin_unlock_irqrestore(&pmu_lock
, flags
);
541 unsigned long flags
, val
;
543 raw_spin_lock_irqsave(&pmu_lock
, flags
);
544 val
= armv6_pmcr_read();
545 val
&= ~ARMV6_PMCR_ENABLE
;
546 armv6_pmcr_write(val
);
547 raw_spin_unlock_irqrestore(&pmu_lock
, flags
);
551 armv6pmu_get_event_idx(struct cpu_hw_events
*cpuc
,
552 struct hw_perf_event
*event
)
554 /* Always place a cycle counter into the cycle counter. */
555 if (ARMV6_PERFCTR_CPU_CYCLES
== event
->config_base
) {
556 if (test_and_set_bit(ARMV6_CYCLE_COUNTER
, cpuc
->used_mask
))
559 return ARMV6_CYCLE_COUNTER
;
562 * For anything other than a cycle counter, try and use
563 * counter0 and counter1.
565 if (!test_and_set_bit(ARMV6_COUNTER1
, cpuc
->used_mask
))
566 return ARMV6_COUNTER1
;
568 if (!test_and_set_bit(ARMV6_COUNTER0
, cpuc
->used_mask
))
569 return ARMV6_COUNTER0
;
571 /* The counters are all in use. */
577 armv6pmu_disable_event(struct hw_perf_event
*hwc
,
580 unsigned long val
, mask
, evt
, flags
;
582 if (ARMV6_CYCLE_COUNTER
== idx
) {
583 mask
= ARMV6_PMCR_CCOUNT_IEN
;
585 } else if (ARMV6_COUNTER0
== idx
) {
586 mask
= ARMV6_PMCR_COUNT0_IEN
| ARMV6_PMCR_EVT_COUNT0_MASK
;
587 evt
= ARMV6_PERFCTR_NOP
<< ARMV6_PMCR_EVT_COUNT0_SHIFT
;
588 } else if (ARMV6_COUNTER1
== idx
) {
589 mask
= ARMV6_PMCR_COUNT1_IEN
| ARMV6_PMCR_EVT_COUNT1_MASK
;
590 evt
= ARMV6_PERFCTR_NOP
<< ARMV6_PMCR_EVT_COUNT1_SHIFT
;
592 WARN_ONCE(1, "invalid counter number (%d)\n", idx
);
597 * Mask out the current event and set the counter to count the number
598 * of ETM bus signal assertion cycles. The external reporting should
599 * be disabled and so this should never increment.
601 raw_spin_lock_irqsave(&pmu_lock
, flags
);
602 val
= armv6_pmcr_read();
605 armv6_pmcr_write(val
);
606 raw_spin_unlock_irqrestore(&pmu_lock
, flags
);
610 armv6mpcore_pmu_disable_event(struct hw_perf_event
*hwc
,
613 unsigned long val
, mask
, flags
, evt
= 0;
615 if (ARMV6_CYCLE_COUNTER
== idx
) {
616 mask
= ARMV6_PMCR_CCOUNT_IEN
;
617 } else if (ARMV6_COUNTER0
== idx
) {
618 mask
= ARMV6_PMCR_COUNT0_IEN
;
619 } else if (ARMV6_COUNTER1
== idx
) {
620 mask
= ARMV6_PMCR_COUNT1_IEN
;
622 WARN_ONCE(1, "invalid counter number (%d)\n", idx
);
627 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
628 * simply disable the interrupt reporting.
630 raw_spin_lock_irqsave(&pmu_lock
, flags
);
631 val
= armv6_pmcr_read();
634 armv6_pmcr_write(val
);
635 raw_spin_unlock_irqrestore(&pmu_lock
, flags
);
638 static const struct arm_pmu armv6pmu
= {
639 .id
= ARM_PERF_PMU_ID_V6
,
641 .handle_irq
= armv6pmu_handle_irq
,
642 .enable
= armv6pmu_enable_event
,
643 .disable
= armv6pmu_disable_event
,
644 .read_counter
= armv6pmu_read_counter
,
645 .write_counter
= armv6pmu_write_counter
,
646 .get_event_idx
= armv6pmu_get_event_idx
,
647 .start
= armv6pmu_start
,
648 .stop
= armv6pmu_stop
,
649 .cache_map
= &armv6_perf_cache_map
,
650 .event_map
= &armv6_perf_map
,
651 .raw_event_mask
= 0xFF,
653 .max_period
= (1LLU << 32) - 1,
656 static const struct arm_pmu
*__init
armv6pmu_init(void)
662 * ARMv6mpcore is almost identical to single core ARMv6 with the exception
663 * that some of the events have different enumerations and that there is no
664 * *hack* to stop the programmable counters. To stop the counters we simply
665 * disable the interrupt reporting and update the event. When unthrottling we
666 * reset the period and enable the interrupt reporting.
668 static const struct arm_pmu armv6mpcore_pmu
= {
669 .id
= ARM_PERF_PMU_ID_V6MP
,
671 .handle_irq
= armv6pmu_handle_irq
,
672 .enable
= armv6pmu_enable_event
,
673 .disable
= armv6mpcore_pmu_disable_event
,
674 .read_counter
= armv6pmu_read_counter
,
675 .write_counter
= armv6pmu_write_counter
,
676 .get_event_idx
= armv6pmu_get_event_idx
,
677 .start
= armv6pmu_start
,
678 .stop
= armv6pmu_stop
,
679 .cache_map
= &armv6mpcore_perf_cache_map
,
680 .event_map
= &armv6mpcore_perf_map
,
681 .raw_event_mask
= 0xFF,
683 .max_period
= (1LLU << 32) - 1,
686 static const struct arm_pmu
*__init
armv6mpcore_pmu_init(void)
688 return &armv6mpcore_pmu
;
691 static const struct arm_pmu
*__init
armv6pmu_init(void)
696 static const struct arm_pmu
*__init
armv6mpcore_pmu_init(void)
700 #endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */