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Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / arm / mach-at91 / at91sam9g45_devices.c
blobc3dfb1b3b1e3a6032e554c273f05bf81699579a8
1 /*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/platform_device.h>
18 #include <linux/i2c-gpio.h>
19 #include <linux/atmel-mci.h>
20
21 #include <linux/fb.h>
22 #include <video/atmel_lcdc.h>
23
24 #include <mach/board.h>
25 #include <mach/at91sam9g45.h>
26 #include <mach/at91sam9g45_matrix.h>
27 #include <mach/at91sam9_smc.h>
28 #include <mach/at_hdmac.h>
29 #include <mach/atmel-mci.h>
30
31 #include "generic.h"
32
33
34 /* --------------------------------------------------------------------
35 * HDMAC - AHB DMA Controller
36 * -------------------------------------------------------------------- */
37
38 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
39 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
40
41 static struct at_dma_platform_data atdma_pdata = {
42 .nr_channels = 8,
43 };
44
45 static struct resource hdmac_resources[] = {
46 [0] = {
47 .start = AT91_BASE_SYS + AT91_DMA,
48 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
49 .flags = IORESOURCE_MEM,
50 },
51 [1] = {
52 .start = AT91SAM9G45_ID_DMA,
53 .end = AT91SAM9G45_ID_DMA,
54 .flags = IORESOURCE_IRQ,
55 },
56 };
57
58 static struct platform_device at_hdmac_device = {
59 .name = "at_hdmac",
60 .id = -1,
61 .dev = {
62 .dma_mask = &hdmac_dmamask,
63 .coherent_dma_mask = DMA_BIT_MASK(32),
64 .platform_data = &atdma_pdata,
65 },
66 .resource = hdmac_resources,
67 .num_resources = ARRAY_SIZE(hdmac_resources),
68 };
69
70 void __init at91_add_device_hdmac(void)
71 {
72 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
73 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
74 platform_device_register(&at_hdmac_device);
75 }
76 #else
77 void __init at91_add_device_hdmac(void) {}
78 #endif
79
80
81 /* --------------------------------------------------------------------
82 * USB Host (OHCI)
83 * -------------------------------------------------------------------- */
84
85 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
86 static u64 ohci_dmamask = DMA_BIT_MASK(32);
87 static struct at91_usbh_data usbh_ohci_data;
88
89 static struct resource usbh_ohci_resources[] = {
90 [0] = {
91 .start = AT91SAM9G45_OHCI_BASE,
92 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = AT91SAM9G45_ID_UHPHS,
97 .end = AT91SAM9G45_ID_UHPHS,
98 .flags = IORESOURCE_IRQ,
99 },
100 };
101
102 static struct platform_device at91_usbh_ohci_device = {
103 .name = "at91_ohci",
104 .id = -1,
105 .dev = {
106 .dma_mask = &ohci_dmamask,
107 .coherent_dma_mask = DMA_BIT_MASK(32),
108 .platform_data = &usbh_ohci_data,
109 },
110 .resource = usbh_ohci_resources,
111 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
112 };
113
114 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
115 {
116 int i;
117
118 if (!data)
119 return;
120
121 /* Enable VBus control for UHP ports */
122 for (i = 0; i < data->ports; i++) {
123 if (data->vbus_pin[i])
124 at91_set_gpio_output(data->vbus_pin[i], 0);
125 }
126
127 usbh_ohci_data = *data;
128 platform_device_register(&at91_usbh_ohci_device);
129 }
130 #else
131 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
132 #endif
133
134
135 /* --------------------------------------------------------------------
136 * USB Host HS (EHCI)
137 * Needs an OHCI host for low and full speed management
138 * -------------------------------------------------------------------- */
139
140 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
141 static u64 ehci_dmamask = DMA_BIT_MASK(32);
142 static struct at91_usbh_data usbh_ehci_data;
143
144 static struct resource usbh_ehci_resources[] = {
145 [0] = {
146 .start = AT91SAM9G45_EHCI_BASE,
147 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = AT91SAM9G45_ID_UHPHS,
152 .end = AT91SAM9G45_ID_UHPHS,
153 .flags = IORESOURCE_IRQ,
154 },
155 };
156
157 static struct platform_device at91_usbh_ehci_device = {
158 .name = "atmel-ehci",
159 .id = -1,
160 .dev = {
161 .dma_mask = &ehci_dmamask,
162 .coherent_dma_mask = DMA_BIT_MASK(32),
163 .platform_data = &usbh_ehci_data,
164 },
165 .resource = usbh_ehci_resources,
166 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
167 };
168
169 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
170 {
171 int i;
172
173 if (!data)
174 return;
175
176 /* Enable VBus control for UHP ports */
177 for (i = 0; i < data->ports; i++) {
178 if (data->vbus_pin[i])
179 at91_set_gpio_output(data->vbus_pin[i], 0);
180 }
181
182 usbh_ehci_data = *data;
183 platform_device_register(&at91_usbh_ehci_device);
184 }
185 #else
186 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
187 #endif
188
189
190 /* --------------------------------------------------------------------
191 * USB HS Device (Gadget)
192 * -------------------------------------------------------------------- */
193
194 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
195 static struct resource usba_udc_resources[] = {
196 [0] = {
197 .start = AT91SAM9G45_UDPHS_FIFO,
198 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
199 .flags = IORESOURCE_MEM,
200 },
201 [1] = {
202 .start = AT91SAM9G45_BASE_UDPHS,
203 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
204 .flags = IORESOURCE_MEM,
205 },
206 [2] = {
207 .start = AT91SAM9G45_ID_UDPHS,
208 .end = AT91SAM9G45_ID_UDPHS,
209 .flags = IORESOURCE_IRQ,
210 },
211 };
212
213 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
214 [idx] = { \
215 .name = nam, \
216 .index = idx, \
217 .fifo_size = maxpkt, \
218 .nr_banks = maxbk, \
219 .can_dma = dma, \
220 .can_isoc = isoc, \
221 }
222
223 static struct usba_ep_data usba_udc_ep[] __initdata = {
224 EP("ep0", 0, 64, 1, 0, 0),
225 EP("ep1", 1, 1024, 2, 1, 1),
226 EP("ep2", 2, 1024, 2, 1, 1),
227 EP("ep3", 3, 1024, 3, 1, 0),
228 EP("ep4", 4, 1024, 3, 1, 0),
229 EP("ep5", 5, 1024, 3, 1, 1),
230 EP("ep6", 6, 1024, 3, 1, 1),
231 };
232
233 #undef EP
234
235 /*
236 * pdata doesn't have room for any endpoints, so we need to
237 * append room for the ones we need right after it.
238 */
239 static struct {
240 struct usba_platform_data pdata;
241 struct usba_ep_data ep[7];
242 } usba_udc_data;
243
244 static struct platform_device at91_usba_udc_device = {
245 .name = "atmel_usba_udc",
246 .id = -1,
247 .dev = {
248 .platform_data = &usba_udc_data.pdata,
249 },
250 .resource = usba_udc_resources,
251 .num_resources = ARRAY_SIZE(usba_udc_resources),
252 };
253
254 void __init at91_add_device_usba(struct usba_platform_data *data)
255 {
256 usba_udc_data.pdata.vbus_pin = -EINVAL;
257 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
258 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
259
260 if (data && data->vbus_pin > 0) {
261 at91_set_gpio_input(data->vbus_pin, 0);
262 at91_set_deglitch(data->vbus_pin, 1);
263 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
264 }
265
266 /* Pullup pin is handled internally by USB device peripheral */
267
268 platform_device_register(&at91_usba_udc_device);
269 }
270 #else
271 void __init at91_add_device_usba(struct usba_platform_data *data) {}
272 #endif
273
274
275 /* --------------------------------------------------------------------
276 * Ethernet
277 * -------------------------------------------------------------------- */
278
279 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
280 static u64 eth_dmamask = DMA_BIT_MASK(32);
281 static struct at91_eth_data eth_data;
282
283 static struct resource eth_resources[] = {
284 [0] = {
285 .start = AT91SAM9G45_BASE_EMAC,
286 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
290 .start = AT91SAM9G45_ID_EMAC,
291 .end = AT91SAM9G45_ID_EMAC,
292 .flags = IORESOURCE_IRQ,
293 },
294 };
295
296 static struct platform_device at91sam9g45_eth_device = {
297 .name = "macb",
298 .id = -1,
299 .dev = {
300 .dma_mask = &eth_dmamask,
301 .coherent_dma_mask = DMA_BIT_MASK(32),
302 .platform_data = &eth_data,
303 },
304 .resource = eth_resources,
305 .num_resources = ARRAY_SIZE(eth_resources),
306 };
307
308 void __init at91_add_device_eth(struct at91_eth_data *data)
309 {
310 if (!data)
311 return;
312
313 if (data->phy_irq_pin) {
314 at91_set_gpio_input(data->phy_irq_pin, 0);
315 at91_set_deglitch(data->phy_irq_pin, 1);
316 }
317
318 /* Pins used for MII and RMII */
319 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
320 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
321 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
322 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
323 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
324 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
325 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
326 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
327 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
328 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
329
330 if (!data->is_rmii) {
331 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
332 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
333 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
334 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
335 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
336 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
337 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
338 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
339 }
340
341 eth_data = *data;
342 platform_device_register(&at91sam9g45_eth_device);
343 }
344 #else
345 void __init at91_add_device_eth(struct at91_eth_data *data) {}
346 #endif
347
348
349 /* --------------------------------------------------------------------
350 * MMC / SD
351 * -------------------------------------------------------------------- */
352
353 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
354 static u64 mmc_dmamask = DMA_BIT_MASK(32);
355 static struct mci_platform_data mmc0_data, mmc1_data;
356
357 static struct resource mmc0_resources[] = {
358 [0] = {
359 .start = AT91SAM9G45_BASE_MCI0,
360 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
361 .flags = IORESOURCE_MEM,
362 },
363 [1] = {
364 .start = AT91SAM9G45_ID_MCI0,
365 .end = AT91SAM9G45_ID_MCI0,
366 .flags = IORESOURCE_IRQ,
367 },
368 };
369
370 static struct platform_device at91sam9g45_mmc0_device = {
371 .name = "atmel_mci",
372 .id = 0,
373 .dev = {
374 .dma_mask = &mmc_dmamask,
375 .coherent_dma_mask = DMA_BIT_MASK(32),
376 .platform_data = &mmc0_data,
377 },
378 .resource = mmc0_resources,
379 .num_resources = ARRAY_SIZE(mmc0_resources),
380 };
381
382 static struct resource mmc1_resources[] = {
383 [0] = {
384 .start = AT91SAM9G45_BASE_MCI1,
385 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = AT91SAM9G45_ID_MCI1,
390 .end = AT91SAM9G45_ID_MCI1,
391 .flags = IORESOURCE_IRQ,
392 },
393 };
394
395 static struct platform_device at91sam9g45_mmc1_device = {
396 .name = "atmel_mci",
397 .id = 1,
398 .dev = {
399 .dma_mask = &mmc_dmamask,
400 .coherent_dma_mask = DMA_BIT_MASK(32),
401 .platform_data = &mmc1_data,
402 },
403 .resource = mmc1_resources,
404 .num_resources = ARRAY_SIZE(mmc1_resources),
405 };
406
407 /* Consider only one slot : slot 0 */
408 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
409 {
410
411 if (!data)
412 return;
413
414 /* Must have at least one usable slot */
415 if (!data->slot[0].bus_width)
416 return;
417
418 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
419 {
420 struct at_dma_slave *atslave;
421 struct mci_dma_data *alt_atslave;
422
423 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
424 atslave = &alt_atslave->sdata;
425
426 /* DMA slave channel configuration */
427 atslave->dma_dev = &at_hdmac_device.dev;
428 atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
429 atslave->cfg = ATC_FIFOCFG_HALFFIFO
430 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
431 atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
432 if (mmc_id == 0) /* MCI0 */
433 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
434 | ATC_DST_PER(AT_DMA_ID_MCI0);
435
436 else /* MCI1 */
437 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
438 | ATC_DST_PER(AT_DMA_ID_MCI1);
439
440 data->dma_slave = alt_atslave;
441 }
442 #endif
443
444
445 /* input/irq */
446 if (data->slot[0].detect_pin) {
447 at91_set_gpio_input(data->slot[0].detect_pin, 1);
448 at91_set_deglitch(data->slot[0].detect_pin, 1);
449 }
450 if (data->slot[0].wp_pin)
451 at91_set_gpio_input(data->slot[0].wp_pin, 1);
452
453 if (mmc_id == 0) { /* MCI0 */
454
455 /* CLK */
456 at91_set_A_periph(AT91_PIN_PA0, 0);
457
458 /* CMD */
459 at91_set_A_periph(AT91_PIN_PA1, 1);
460
461 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
462 at91_set_A_periph(AT91_PIN_PA2, 1);
463 if (data->slot[0].bus_width == 4) {
464 at91_set_A_periph(AT91_PIN_PA3, 1);
465 at91_set_A_periph(AT91_PIN_PA4, 1);
466 at91_set_A_periph(AT91_PIN_PA5, 1);
467 if (data->slot[0].bus_width == 8) {
468 at91_set_A_periph(AT91_PIN_PA6, 1);
469 at91_set_A_periph(AT91_PIN_PA7, 1);
470 at91_set_A_periph(AT91_PIN_PA8, 1);
471 at91_set_A_periph(AT91_PIN_PA9, 1);
472 }
473 }
474
475 mmc0_data = *data;
476 platform_device_register(&at91sam9g45_mmc0_device);
477
478 } else { /* MCI1 */
479
480 /* CLK */
481 at91_set_A_periph(AT91_PIN_PA31, 0);
482
483 /* CMD */
484 at91_set_A_periph(AT91_PIN_PA22, 1);
485
486 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
487 at91_set_A_periph(AT91_PIN_PA23, 1);
488 if (data->slot[0].bus_width == 4) {
489 at91_set_A_periph(AT91_PIN_PA24, 1);
490 at91_set_A_periph(AT91_PIN_PA25, 1);
491 at91_set_A_periph(AT91_PIN_PA26, 1);
492 if (data->slot[0].bus_width == 8) {
493 at91_set_A_periph(AT91_PIN_PA27, 1);
494 at91_set_A_periph(AT91_PIN_PA28, 1);
495 at91_set_A_periph(AT91_PIN_PA29, 1);
496 at91_set_A_periph(AT91_PIN_PA30, 1);
497 }
498 }
499
500 mmc1_data = *data;
501 platform_device_register(&at91sam9g45_mmc1_device);
502
503 }
504 }
505 #else
506 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
507 #endif
508
509
510 /* --------------------------------------------------------------------
511 * NAND / SmartMedia
512 * -------------------------------------------------------------------- */
513
514 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
515 static struct atmel_nand_data nand_data;
516
517 #define NAND_BASE AT91_CHIPSELECT_3
518
519 static struct resource nand_resources[] = {
520 [0] = {
521 .start = NAND_BASE,
522 .end = NAND_BASE + SZ_256M - 1,
523 .flags = IORESOURCE_MEM,
524 },
525 [1] = {
526 .start = AT91_BASE_SYS + AT91_ECC,
527 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
528 .flags = IORESOURCE_MEM,
529 }
530 };
531
532 static struct platform_device at91sam9g45_nand_device = {
533 .name = "atmel_nand",
534 .id = -1,
535 .dev = {
536 .platform_data = &nand_data,
537 },
538 .resource = nand_resources,
539 .num_resources = ARRAY_SIZE(nand_resources),
540 };
541
542 void __init at91_add_device_nand(struct atmel_nand_data *data)
543 {
544 unsigned long csa;
545
546 if (!data)
547 return;
548
549 csa = at91_sys_read(AT91_MATRIX_EBICSA);
550 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
551
552 /* enable pin */
553 if (data->enable_pin)
554 at91_set_gpio_output(data->enable_pin, 1);
555
556 /* ready/busy pin */
557 if (data->rdy_pin)
558 at91_set_gpio_input(data->rdy_pin, 1);
559
560 /* card detect pin */
561 if (data->det_pin)
562 at91_set_gpio_input(data->det_pin, 1);
563
564 nand_data = *data;
565 platform_device_register(&at91sam9g45_nand_device);
566 }
567 #else
568 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
569 #endif
570
571
572 /* --------------------------------------------------------------------
573 * TWI (i2c)
574 * -------------------------------------------------------------------- */
575
576 /*
577 * Prefer the GPIO code since the TWI controller isn't robust
578 * (gets overruns and underruns under load) and can only issue
579 * repeated STARTs in one scenario (the driver doesn't yet handle them).
580 */
581 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
582 static struct i2c_gpio_platform_data pdata_i2c0 = {
583 .sda_pin = AT91_PIN_PA20,
584 .sda_is_open_drain = 1,
585 .scl_pin = AT91_PIN_PA21,
586 .scl_is_open_drain = 1,
587 .udelay = 5, /* ~100 kHz */
588 };
589
590 static struct platform_device at91sam9g45_twi0_device = {
591 .name = "i2c-gpio",
592 .id = 0,
593 .dev.platform_data = &pdata_i2c0,
594 };
595
596 static struct i2c_gpio_platform_data pdata_i2c1 = {
597 .sda_pin = AT91_PIN_PB10,
598 .sda_is_open_drain = 1,
599 .scl_pin = AT91_PIN_PB11,
600 .scl_is_open_drain = 1,
601 .udelay = 5, /* ~100 kHz */
602 };
603
604 static struct platform_device at91sam9g45_twi1_device = {
605 .name = "i2c-gpio",
606 .id = 1,
607 .dev.platform_data = &pdata_i2c1,
608 };
609
610 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
611 {
612 i2c_register_board_info(i2c_id, devices, nr_devices);
613
614 if (i2c_id == 0) {
615 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
616 at91_set_multi_drive(AT91_PIN_PA20, 1);
617
618 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
619 at91_set_multi_drive(AT91_PIN_PA21, 1);
620
621 platform_device_register(&at91sam9g45_twi0_device);
622 } else {
623 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
624 at91_set_multi_drive(AT91_PIN_PB10, 1);
625
626 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
627 at91_set_multi_drive(AT91_PIN_PB11, 1);
628
629 platform_device_register(&at91sam9g45_twi1_device);
630 }
631 }
632
633 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
634 static struct resource twi0_resources[] = {
635 [0] = {
636 .start = AT91SAM9G45_BASE_TWI0,
637 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
638 .flags = IORESOURCE_MEM,
639 },
640 [1] = {
641 .start = AT91SAM9G45_ID_TWI0,
642 .end = AT91SAM9G45_ID_TWI0,
643 .flags = IORESOURCE_IRQ,
644 },
645 };
646
647 static struct platform_device at91sam9g45_twi0_device = {
648 .name = "at91_i2c",
649 .id = 0,
650 .resource = twi0_resources,
651 .num_resources = ARRAY_SIZE(twi0_resources),
652 };
653
654 static struct resource twi1_resources[] = {
655 [0] = {
656 .start = AT91SAM9G45_BASE_TWI1,
657 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
658 .flags = IORESOURCE_MEM,
659 },
660 [1] = {
661 .start = AT91SAM9G45_ID_TWI1,
662 .end = AT91SAM9G45_ID_TWI1,
663 .flags = IORESOURCE_IRQ,
664 },
665 };
666
667 static struct platform_device at91sam9g45_twi1_device = {
668 .name = "at91_i2c",
669 .id = 1,
670 .resource = twi1_resources,
671 .num_resources = ARRAY_SIZE(twi1_resources),
672 };
673
674 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
675 {
676 i2c_register_board_info(i2c_id, devices, nr_devices);
677
678 /* pins used for TWI interface */
679 if (i2c_id == 0) {
680 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
681 at91_set_multi_drive(AT91_PIN_PA20, 1);
682
683 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
684 at91_set_multi_drive(AT91_PIN_PA21, 1);
685
686 platform_device_register(&at91sam9g45_twi0_device);
687 } else {
688 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
689 at91_set_multi_drive(AT91_PIN_PB10, 1);
690
691 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
692 at91_set_multi_drive(AT91_PIN_PB11, 1);
693
694 platform_device_register(&at91sam9g45_twi1_device);
695 }
696 }
697 #else
698 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
699 #endif
700
701
702 /* --------------------------------------------------------------------
703 * SPI
704 * -------------------------------------------------------------------- */
705
706 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
707 static u64 spi_dmamask = DMA_BIT_MASK(32);
708
709 static struct resource spi0_resources[] = {
710 [0] = {
711 .start = AT91SAM9G45_BASE_SPI0,
712 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
713 .flags = IORESOURCE_MEM,
714 },
715 [1] = {
716 .start = AT91SAM9G45_ID_SPI0,
717 .end = AT91SAM9G45_ID_SPI0,
718 .flags = IORESOURCE_IRQ,
719 },
720 };
721
722 static struct platform_device at91sam9g45_spi0_device = {
723 .name = "atmel_spi",
724 .id = 0,
725 .dev = {
726 .dma_mask = &spi_dmamask,
727 .coherent_dma_mask = DMA_BIT_MASK(32),
728 },
729 .resource = spi0_resources,
730 .num_resources = ARRAY_SIZE(spi0_resources),
731 };
732
733 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
734
735 static struct resource spi1_resources[] = {
736 [0] = {
737 .start = AT91SAM9G45_BASE_SPI1,
738 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
739 .flags = IORESOURCE_MEM,
740 },
741 [1] = {
742 .start = AT91SAM9G45_ID_SPI1,
743 .end = AT91SAM9G45_ID_SPI1,
744 .flags = IORESOURCE_IRQ,
745 },
746 };
747
748 static struct platform_device at91sam9g45_spi1_device = {
749 .name = "atmel_spi",
750 .id = 1,
751 .dev = {
752 .dma_mask = &spi_dmamask,
753 .coherent_dma_mask = DMA_BIT_MASK(32),
754 },
755 .resource = spi1_resources,
756 .num_resources = ARRAY_SIZE(spi1_resources),
757 };
758
759 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
760
761 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
762 {
763 int i;
764 unsigned long cs_pin;
765 short enable_spi0 = 0;
766 short enable_spi1 = 0;
767
768 /* Choose SPI chip-selects */
769 for (i = 0; i < nr_devices; i++) {
770 if (devices[i].controller_data)
771 cs_pin = (unsigned long) devices[i].controller_data;
772 else if (devices[i].bus_num == 0)
773 cs_pin = spi0_standard_cs[devices[i].chip_select];
774 else
775 cs_pin = spi1_standard_cs[devices[i].chip_select];
776
777 if (devices[i].bus_num == 0)
778 enable_spi0 = 1;
779 else
780 enable_spi1 = 1;
781
782 /* enable chip-select pin */
783 at91_set_gpio_output(cs_pin, 1);
784
785 /* pass chip-select pin to driver */
786 devices[i].controller_data = (void *) cs_pin;
787 }
788
789 spi_register_board_info(devices, nr_devices);
790
791 /* Configure SPI bus(es) */
792 if (enable_spi0) {
793 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
794 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
795 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
796
797 platform_device_register(&at91sam9g45_spi0_device);
798 }
799 if (enable_spi1) {
800 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
801 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
802 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
803
804 platform_device_register(&at91sam9g45_spi1_device);
805 }
806 }
807 #else
808 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
809 #endif
810
811
812 /* --------------------------------------------------------------------
813 * AC97
814 * -------------------------------------------------------------------- */
815
816 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
817 static u64 ac97_dmamask = DMA_BIT_MASK(32);
818 static struct ac97c_platform_data ac97_data;
819
820 static struct resource ac97_resources[] = {
821 [0] = {
822 .start = AT91SAM9G45_BASE_AC97C,
823 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
824 .flags = IORESOURCE_MEM,
825 },
826 [1] = {
827 .start = AT91SAM9G45_ID_AC97C,
828 .end = AT91SAM9G45_ID_AC97C,
829 .flags = IORESOURCE_IRQ,
830 },
831 };
832
833 static struct platform_device at91sam9g45_ac97_device = {
834 .name = "atmel_ac97c",
835 .id = 0,
836 .dev = {
837 .dma_mask = &ac97_dmamask,
838 .coherent_dma_mask = DMA_BIT_MASK(32),
839 .platform_data = &ac97_data,
840 },
841 .resource = ac97_resources,
842 .num_resources = ARRAY_SIZE(ac97_resources),
843 };
844
845 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
846 {
847 if (!data)
848 return;
849
850 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
851 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
852 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
853 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
854
855 /* reset */
856 if (data->reset_pin)
857 at91_set_gpio_output(data->reset_pin, 0);
858
859 ac97_data = *data;
860 platform_device_register(&at91sam9g45_ac97_device);
861 }
862 #else
863 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
864 #endif
865
866
867 /* --------------------------------------------------------------------
868 * LCD Controller
869 * -------------------------------------------------------------------- */
870
871 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
872 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
873 static struct atmel_lcdfb_info lcdc_data;
874
875 static struct resource lcdc_resources[] = {
876 [0] = {
877 .start = AT91SAM9G45_LCDC_BASE,
878 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
879 .flags = IORESOURCE_MEM,
880 },
881 [1] = {
882 .start = AT91SAM9G45_ID_LCDC,
883 .end = AT91SAM9G45_ID_LCDC,
884 .flags = IORESOURCE_IRQ,
885 },
886 };
887
888 static struct platform_device at91_lcdc_device = {
889 .name = "atmel_lcdfb",
890 .id = 0,
891 .dev = {
892 .dma_mask = &lcdc_dmamask,
893 .coherent_dma_mask = DMA_BIT_MASK(32),
894 .platform_data = &lcdc_data,
895 },
896 .resource = lcdc_resources,
897 .num_resources = ARRAY_SIZE(lcdc_resources),
898 };
899
900 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
901 {
902 if (!data)
903 return;
904
905 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
906
907 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
908 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
909 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
910 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
911 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
912 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
913 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
914 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
915 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
916 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
917 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
918 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
919 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
920 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
921 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
922 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
923 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
924 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
925 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
926 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
927 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
928 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
929 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
930 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
931 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
932 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
933 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
934 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
935 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
936
937 lcdc_data = *data;
938 platform_device_register(&at91_lcdc_device);
939 }
940 #else
941 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
942 #endif
943
944
945 /* --------------------------------------------------------------------
946 * Timer/Counter block
947 * -------------------------------------------------------------------- */
948
949 #ifdef CONFIG_ATMEL_TCLIB
950 static struct resource tcb0_resources[] = {
951 [0] = {
952 .start = AT91SAM9G45_BASE_TCB0,
953 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
954 .flags = IORESOURCE_MEM,
955 },
956 [1] = {
957 .start = AT91SAM9G45_ID_TCB,
958 .end = AT91SAM9G45_ID_TCB,
959 .flags = IORESOURCE_IRQ,
960 },
961 };
962
963 static struct platform_device at91sam9g45_tcb0_device = {
964 .name = "atmel_tcb",
965 .id = 0,
966 .resource = tcb0_resources,
967 .num_resources = ARRAY_SIZE(tcb0_resources),
968 };
969
970 /* TCB1 begins with TC3 */
971 static struct resource tcb1_resources[] = {
972 [0] = {
973 .start = AT91SAM9G45_BASE_TCB1,
974 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
975 .flags = IORESOURCE_MEM,
976 },
977 [1] = {
978 .start = AT91SAM9G45_ID_TCB,
979 .end = AT91SAM9G45_ID_TCB,
980 .flags = IORESOURCE_IRQ,
981 },
982 };
983
984 static struct platform_device at91sam9g45_tcb1_device = {
985 .name = "atmel_tcb",
986 .id = 1,
987 .resource = tcb1_resources,
988 .num_resources = ARRAY_SIZE(tcb1_resources),
989 };
990
991 static void __init at91_add_device_tc(void)
992 {
993 platform_device_register(&at91sam9g45_tcb0_device);
994 platform_device_register(&at91sam9g45_tcb1_device);
995 }
996 #else
997 static void __init at91_add_device_tc(void) { }
998 #endif
999
1000
1001 /* --------------------------------------------------------------------
1002 * RTC
1003 * -------------------------------------------------------------------- */
1004
1005 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1006 static struct platform_device at91sam9g45_rtc_device = {
1007 .name = "at91_rtc",
1008 .id = -1,
1009 .num_resources = 0,
1010 };
1011
1012 static void __init at91_add_device_rtc(void)
1013 {
1014 platform_device_register(&at91sam9g45_rtc_device);
1015 }
1016 #else
1017 static void __init at91_add_device_rtc(void) {}
1018 #endif
1019
1020
1021 /* --------------------------------------------------------------------
1022 * Touchscreen
1023 * -------------------------------------------------------------------- */
1024
1025 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1026 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1027 static struct at91_tsadcc_data tsadcc_data;
1028
1029 static struct resource tsadcc_resources[] = {
1030 [0] = {
1031 .start = AT91SAM9G45_BASE_TSC,
1032 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1033 .flags = IORESOURCE_MEM,
1034 },
1035 [1] = {
1036 .start = AT91SAM9G45_ID_TSC,
1037 .end = AT91SAM9G45_ID_TSC,
1038 .flags = IORESOURCE_IRQ,
1039 }
1040 };
1041
1042 static struct platform_device at91sam9g45_tsadcc_device = {
1043 .name = "atmel_tsadcc",
1044 .id = -1,
1045 .dev = {
1046 .dma_mask = &tsadcc_dmamask,
1047 .coherent_dma_mask = DMA_BIT_MASK(32),
1048 .platform_data = &tsadcc_data,
1049 },
1050 .resource = tsadcc_resources,
1051 .num_resources = ARRAY_SIZE(tsadcc_resources),
1052 };
1053
1054 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1055 {
1056 if (!data)
1057 return;
1058
1059 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1060 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1061 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1062 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1063
1064 tsadcc_data = *data;
1065 platform_device_register(&at91sam9g45_tsadcc_device);
1066 }
1067 #else
1068 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1069 #endif
1070
1071
1072 /* --------------------------------------------------------------------
1073 * RTT
1074 * -------------------------------------------------------------------- */
1075
1076 static struct resource rtt_resources[] = {
1077 {
1078 .start = AT91_BASE_SYS + AT91_RTT,
1079 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
1080 .flags = IORESOURCE_MEM,
1081 }
1082 };
1083
1084 static struct platform_device at91sam9g45_rtt_device = {
1085 .name = "at91_rtt",
1086 .id = 0,
1087 .resource = rtt_resources,
1088 .num_resources = ARRAY_SIZE(rtt_resources),
1089 };
1090
1091 static void __init at91_add_device_rtt(void)
1092 {
1093 platform_device_register(&at91sam9g45_rtt_device);
1094 }
1095
1096
1097 /* --------------------------------------------------------------------
1098 * Watchdog
1099 * -------------------------------------------------------------------- */
1100
1101 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1102 static struct platform_device at91sam9g45_wdt_device = {
1103 .name = "at91_wdt",
1104 .id = -1,
1105 .num_resources = 0,
1106 };
1107
1108 static void __init at91_add_device_watchdog(void)
1109 {
1110 platform_device_register(&at91sam9g45_wdt_device);
1111 }
1112 #else
1113 static void __init at91_add_device_watchdog(void) {}
1114 #endif
1115
1116
1117 /* --------------------------------------------------------------------
1118 * PWM
1119 * --------------------------------------------------------------------*/
1120
1121 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1122 static u32 pwm_mask;
1123
1124 static struct resource pwm_resources[] = {
1125 [0] = {
1126 .start = AT91SAM9G45_BASE_PWMC,
1127 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1128 .flags = IORESOURCE_MEM,
1129 },
1130 [1] = {
1131 .start = AT91SAM9G45_ID_PWMC,
1132 .end = AT91SAM9G45_ID_PWMC,
1133 .flags = IORESOURCE_IRQ,
1134 },
1135 };
1136
1137 static struct platform_device at91sam9g45_pwm0_device = {
1138 .name = "atmel_pwm",
1139 .id = -1,
1140 .dev = {
1141 .platform_data = &pwm_mask,
1142 },
1143 .resource = pwm_resources,
1144 .num_resources = ARRAY_SIZE(pwm_resources),
1145 };
1146
1147 void __init at91_add_device_pwm(u32 mask)
1148 {
1149 if (mask & (1 << AT91_PWM0))
1150 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1151
1152 if (mask & (1 << AT91_PWM1))
1153 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1154
1155 if (mask & (1 << AT91_PWM2))
1156 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1157
1158 if (mask & (1 << AT91_PWM3))
1159 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1160
1161 pwm_mask = mask;
1162
1163 platform_device_register(&at91sam9g45_pwm0_device);
1164 }
1165 #else
1166 void __init at91_add_device_pwm(u32 mask) {}
1167 #endif
1168
1169
1170 /* --------------------------------------------------------------------
1171 * SSC -- Synchronous Serial Controller
1172 * -------------------------------------------------------------------- */
1173
1174 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1175 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1176
1177 static struct resource ssc0_resources[] = {
1178 [0] = {
1179 .start = AT91SAM9G45_BASE_SSC0,
1180 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1181 .flags = IORESOURCE_MEM,
1182 },
1183 [1] = {
1184 .start = AT91SAM9G45_ID_SSC0,
1185 .end = AT91SAM9G45_ID_SSC0,
1186 .flags = IORESOURCE_IRQ,
1187 },
1188 };
1189
1190 static struct platform_device at91sam9g45_ssc0_device = {
1191 .name = "ssc",
1192 .id = 0,
1193 .dev = {
1194 .dma_mask = &ssc0_dmamask,
1195 .coherent_dma_mask = DMA_BIT_MASK(32),
1196 },
1197 .resource = ssc0_resources,
1198 .num_resources = ARRAY_SIZE(ssc0_resources),
1199 };
1200
1201 static inline void configure_ssc0_pins(unsigned pins)
1202 {
1203 if (pins & ATMEL_SSC_TF)
1204 at91_set_A_periph(AT91_PIN_PD1, 1);
1205 if (pins & ATMEL_SSC_TK)
1206 at91_set_A_periph(AT91_PIN_PD0, 1);
1207 if (pins & ATMEL_SSC_TD)
1208 at91_set_A_periph(AT91_PIN_PD2, 1);
1209 if (pins & ATMEL_SSC_RD)
1210 at91_set_A_periph(AT91_PIN_PD3, 1);
1211 if (pins & ATMEL_SSC_RK)
1212 at91_set_A_periph(AT91_PIN_PD4, 1);
1213 if (pins & ATMEL_SSC_RF)
1214 at91_set_A_periph(AT91_PIN_PD5, 1);
1215 }
1216
1217 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1218
1219 static struct resource ssc1_resources[] = {
1220 [0] = {
1221 .start = AT91SAM9G45_BASE_SSC1,
1222 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1223 .flags = IORESOURCE_MEM,
1224 },
1225 [1] = {
1226 .start = AT91SAM9G45_ID_SSC1,
1227 .end = AT91SAM9G45_ID_SSC1,
1228 .flags = IORESOURCE_IRQ,
1229 },
1230 };
1231
1232 static struct platform_device at91sam9g45_ssc1_device = {
1233 .name = "ssc",
1234 .id = 1,
1235 .dev = {
1236 .dma_mask = &ssc1_dmamask,
1237 .coherent_dma_mask = DMA_BIT_MASK(32),
1238 },
1239 .resource = ssc1_resources,
1240 .num_resources = ARRAY_SIZE(ssc1_resources),
1241 };
1242
1243 static inline void configure_ssc1_pins(unsigned pins)
1244 {
1245 if (pins & ATMEL_SSC_TF)
1246 at91_set_A_periph(AT91_PIN_PD14, 1);
1247 if (pins & ATMEL_SSC_TK)
1248 at91_set_A_periph(AT91_PIN_PD12, 1);
1249 if (pins & ATMEL_SSC_TD)
1250 at91_set_A_periph(AT91_PIN_PD10, 1);
1251 if (pins & ATMEL_SSC_RD)
1252 at91_set_A_periph(AT91_PIN_PD11, 1);
1253 if (pins & ATMEL_SSC_RK)
1254 at91_set_A_periph(AT91_PIN_PD13, 1);
1255 if (pins & ATMEL_SSC_RF)
1256 at91_set_A_periph(AT91_PIN_PD15, 1);
1257 }
1258
1259 /*
1260 * SSC controllers are accessed through library code, instead of any
1261 * kind of all-singing/all-dancing driver. For example one could be
1262 * used by a particular I2S audio codec's driver, while another one
1263 * on the same system might be used by a custom data capture driver.
1264 */
1265 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1266 {
1267 struct platform_device *pdev;
1268
1269 /*
1270 * NOTE: caller is responsible for passing information matching
1271 * "pins" to whatever will be using each particular controller.
1272 */
1273 switch (id) {
1274 case AT91SAM9G45_ID_SSC0:
1275 pdev = &at91sam9g45_ssc0_device;
1276 configure_ssc0_pins(pins);
1277 break;
1278 case AT91SAM9G45_ID_SSC1:
1279 pdev = &at91sam9g45_ssc1_device;
1280 configure_ssc1_pins(pins);
1281 break;
1282 default:
1283 return;
1284 }
1285
1286 platform_device_register(pdev);
1287 }
1288
1289 #else
1290 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1291 #endif
1292
1293
1294 /* --------------------------------------------------------------------
1295 * UART
1296 * -------------------------------------------------------------------- */
1297
1298 #if defined(CONFIG_SERIAL_ATMEL)
1299 static struct resource dbgu_resources[] = {
1300 [0] = {
1301 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1302 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1303 .flags = IORESOURCE_MEM,
1304 },
1305 [1] = {
1306 .start = AT91_ID_SYS,
1307 .end = AT91_ID_SYS,
1308 .flags = IORESOURCE_IRQ,
1309 },
1310 };
1311
1312 static struct atmel_uart_data dbgu_data = {
1313 .use_dma_tx = 0,
1314 .use_dma_rx = 0,
1315 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1316 };
1317
1318 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1319
1320 static struct platform_device at91sam9g45_dbgu_device = {
1321 .name = "atmel_usart",
1322 .id = 0,
1323 .dev = {
1324 .dma_mask = &dbgu_dmamask,
1325 .coherent_dma_mask = DMA_BIT_MASK(32),
1326 .platform_data = &dbgu_data,
1327 },
1328 .resource = dbgu_resources,
1329 .num_resources = ARRAY_SIZE(dbgu_resources),
1330 };
1331
1332 static inline void configure_dbgu_pins(void)
1333 {
1334 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1335 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1336 }
1337
1338 static struct resource uart0_resources[] = {
1339 [0] = {
1340 .start = AT91SAM9G45_BASE_US0,
1341 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1342 .flags = IORESOURCE_MEM,
1343 },
1344 [1] = {
1345 .start = AT91SAM9G45_ID_US0,
1346 .end = AT91SAM9G45_ID_US0,
1347 .flags = IORESOURCE_IRQ,
1348 },
1349 };
1350
1351 static struct atmel_uart_data uart0_data = {
1352 .use_dma_tx = 1,
1353 .use_dma_rx = 1,
1354 };
1355
1356 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1357
1358 static struct platform_device at91sam9g45_uart0_device = {
1359 .name = "atmel_usart",
1360 .id = 1,
1361 .dev = {
1362 .dma_mask = &uart0_dmamask,
1363 .coherent_dma_mask = DMA_BIT_MASK(32),
1364 .platform_data = &uart0_data,
1365 },
1366 .resource = uart0_resources,
1367 .num_resources = ARRAY_SIZE(uart0_resources),
1368 };
1369
1370 static inline void configure_usart0_pins(unsigned pins)
1371 {
1372 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1373 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1374
1375 if (pins & ATMEL_UART_RTS)
1376 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1377 if (pins & ATMEL_UART_CTS)
1378 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1379 }
1380
1381 static struct resource uart1_resources[] = {
1382 [0] = {
1383 .start = AT91SAM9G45_BASE_US1,
1384 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1385 .flags = IORESOURCE_MEM,
1386 },
1387 [1] = {
1388 .start = AT91SAM9G45_ID_US1,
1389 .end = AT91SAM9G45_ID_US1,
1390 .flags = IORESOURCE_IRQ,
1391 },
1392 };
1393
1394 static struct atmel_uart_data uart1_data = {
1395 .use_dma_tx = 1,
1396 .use_dma_rx = 1,
1397 };
1398
1399 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1400
1401 static struct platform_device at91sam9g45_uart1_device = {
1402 .name = "atmel_usart",
1403 .id = 2,
1404 .dev = {
1405 .dma_mask = &uart1_dmamask,
1406 .coherent_dma_mask = DMA_BIT_MASK(32),
1407 .platform_data = &uart1_data,
1408 },
1409 .resource = uart1_resources,
1410 .num_resources = ARRAY_SIZE(uart1_resources),
1411 };
1412
1413 static inline void configure_usart1_pins(unsigned pins)
1414 {
1415 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1416 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1417
1418 if (pins & ATMEL_UART_RTS)
1419 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1420 if (pins & ATMEL_UART_CTS)
1421 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1422 }
1423
1424 static struct resource uart2_resources[] = {
1425 [0] = {
1426 .start = AT91SAM9G45_BASE_US2,
1427 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1428 .flags = IORESOURCE_MEM,
1429 },
1430 [1] = {
1431 .start = AT91SAM9G45_ID_US2,
1432 .end = AT91SAM9G45_ID_US2,
1433 .flags = IORESOURCE_IRQ,
1434 },
1435 };
1436
1437 static struct atmel_uart_data uart2_data = {
1438 .use_dma_tx = 1,
1439 .use_dma_rx = 1,
1440 };
1441
1442 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1443
1444 static struct platform_device at91sam9g45_uart2_device = {
1445 .name = "atmel_usart",
1446 .id = 3,
1447 .dev = {
1448 .dma_mask = &uart2_dmamask,
1449 .coherent_dma_mask = DMA_BIT_MASK(32),
1450 .platform_data = &uart2_data,
1451 },
1452 .resource = uart2_resources,
1453 .num_resources = ARRAY_SIZE(uart2_resources),
1454 };
1455
1456 static inline void configure_usart2_pins(unsigned pins)
1457 {
1458 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1459 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1460
1461 if (pins & ATMEL_UART_RTS)
1462 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1463 if (pins & ATMEL_UART_CTS)
1464 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1465 }
1466
1467 static struct resource uart3_resources[] = {
1468 [0] = {
1469 .start = AT91SAM9G45_BASE_US3,
1470 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1471 .flags = IORESOURCE_MEM,
1472 },
1473 [1] = {
1474 .start = AT91SAM9G45_ID_US3,
1475 .end = AT91SAM9G45_ID_US3,
1476 .flags = IORESOURCE_IRQ,
1477 },
1478 };
1479
1480 static struct atmel_uart_data uart3_data = {
1481 .use_dma_tx = 1,
1482 .use_dma_rx = 1,
1483 };
1484
1485 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1486
1487 static struct platform_device at91sam9g45_uart3_device = {
1488 .name = "atmel_usart",
1489 .id = 4,
1490 .dev = {
1491 .dma_mask = &uart3_dmamask,
1492 .coherent_dma_mask = DMA_BIT_MASK(32),
1493 .platform_data = &uart3_data,
1494 },
1495 .resource = uart3_resources,
1496 .num_resources = ARRAY_SIZE(uart3_resources),
1497 };
1498
1499 static inline void configure_usart3_pins(unsigned pins)
1500 {
1501 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1502 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1503
1504 if (pins & ATMEL_UART_RTS)
1505 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1506 if (pins & ATMEL_UART_CTS)
1507 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1508 }
1509
1510 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1511 struct platform_device *atmel_default_console_device; /* the serial console device */
1512
1513 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1514 {
1515 struct platform_device *pdev;
1516 struct atmel_uart_data *pdata;
1517
1518 switch (id) {
1519 case 0: /* DBGU */
1520 pdev = &at91sam9g45_dbgu_device;
1521 configure_dbgu_pins();
1522 break;
1523 case AT91SAM9G45_ID_US0:
1524 pdev = &at91sam9g45_uart0_device;
1525 configure_usart0_pins(pins);
1526 break;
1527 case AT91SAM9G45_ID_US1:
1528 pdev = &at91sam9g45_uart1_device;
1529 configure_usart1_pins(pins);
1530 break;
1531 case AT91SAM9G45_ID_US2:
1532 pdev = &at91sam9g45_uart2_device;
1533 configure_usart2_pins(pins);
1534 break;
1535 case AT91SAM9G45_ID_US3:
1536 pdev = &at91sam9g45_uart3_device;
1537 configure_usart3_pins(pins);
1538 break;
1539 default:
1540 return;
1541 }
1542 pdata = pdev->dev.platform_data;
1543 pdata->num = portnr; /* update to mapped ID */
1544
1545 if (portnr < ATMEL_MAX_UART)
1546 at91_uarts[portnr] = pdev;
1547 }
1548
1549 void __init at91_set_serial_console(unsigned portnr)
1550 {
1551 if (portnr < ATMEL_MAX_UART) {
1552 atmel_default_console_device = at91_uarts[portnr];
1553 at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
1554 }
1555 }
1556
1557 void __init at91_add_device_serial(void)
1558 {
1559 int i;
1560
1561 for (i = 0; i < ATMEL_MAX_UART; i++) {
1562 if (at91_uarts[i])
1563 platform_device_register(at91_uarts[i]);
1564 }
1565
1566 if (!atmel_default_console_device)
1567 printk(KERN_INFO "AT91: No default serial console defined.\n");
1568 }
1569 #else
1570 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1571 void __init at91_set_serial_console(unsigned portnr) {}
1572 void __init at91_add_device_serial(void) {}
1573 #endif
1574
1575
1576 /* -------------------------------------------------------------------- */
1577 /*
1578 * These devices are always present and don't need any board-specific
1579 * setup.
1580 */
1581 static int __init at91_add_standard_devices(void)
1582 {
1583 at91_add_device_hdmac();
1584 at91_add_device_rtc();
1585 at91_add_device_rtt();
1586 at91_add_device_watchdog();
1587 at91_add_device_tc();
1588 return 0;
1589 }
1590
1591 arch_initcall(at91_add_standard_devices);
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