arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h

   1 /*****************************************************************************
   2 * Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
   3 *
   4 * Unless you and Broadcom execute a separate written software license
   5 * agreement governing use of this software, this software is licensed to you
   6 * under the terms of the GNU General Public License version 2, available at
   7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
   8 *
   9 * Notwithstanding the above, under no circumstances may you combine this
  10 * software in any way with any other Broadcom software provided under a
  11 * license other than the GPL, without Broadcom's express prior written
  12 * consent.
  13 *****************************************************************************/
  14
  15 /****************************************************************************/
  16 /**
  17 *  @file    intcHw_reg.h
  18 *
  19 *  @brief   platform specific interrupt controller bit assignments
  20 *
  21 *  @note
  22 *     None
  23 */
  24 /****************************************************************************/
  25
  26 #ifndef _INTCHW_REG_H
  27 #define _INTCHW_REG_H
  28
  29 /* ---- Include Files ---------------------------------------------------- */
  30 #include <csp/stdint.h>
  31 #include <csp/reg.h>
  32 #include <mach/csp/mm_io.h>
  33
  34 /* ---- Public Constants and Types --------------------------------------- */
  35
  36 #define INTCHW_NUM_IRQ_PER_INTC   32    /* Maximum number of interrupt controllers */
  37 #define INTCHW_NUM_INTC           3
  38
  39 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
  40 #define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
  41 #define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
  42 #define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
  43
  44 /* INTC0 - interrupt controller 0 */
  45 #define INTCHW_INTC0_PIF_BITNUM           31    /* Peripheral interface interrupt */
  46 #define INTCHW_INTC0_CLCD_BITNUM          30    /* LCD Controller interrupt */
  47 #define INTCHW_INTC0_GE_BITNUM            29    /* Graphic engine interrupt */
  48 #define INTCHW_INTC0_APM_BITNUM           28    /* Audio process module interrupt */
  49 #define INTCHW_INTC0_ESW_BITNUM           27    /* Ethernet switch interrupt */
  50 #define INTCHW_INTC0_SPIH_BITNUM          26    /* SPI host interrupt */
  51 #define INTCHW_INTC0_TIMER3_BITNUM        25    /* Timer3 interrupt */
  52 #define INTCHW_INTC0_TIMER2_BITNUM        24    /* Timer2 interrupt */
  53 #define INTCHW_INTC0_TIMER1_BITNUM        23    /* Timer1 interrupt */
  54 #define INTCHW_INTC0_TIMER0_BITNUM        22    /* Timer0 interrupt */
  55 #define INTCHW_INTC0_SDIOH1_BITNUM        21    /* SDIO1 host interrupt */
  56 #define INTCHW_INTC0_SDIOH0_BITNUM        20    /* SDIO0 host interrupt */
  57 #define INTCHW_INTC0_USBD_BITNUM          19    /* USB device interrupt */
  58 #define INTCHW_INTC0_USBH1_BITNUM         18    /* USB1 host interrupt */
  59 #define INTCHW_INTC0_USBHD2_BITNUM        17    /* USB host2/device2 interrupt */
  60 #define INTCHW_INTC0_VPM_BITNUM           16    /* Voice process module interrupt */
  61 #define INTCHW_INTC0_DMA1C7_BITNUM        15    /* DMA1 channel 7 interrupt */
  62 #define INTCHW_INTC0_DMA1C6_BITNUM        14    /* DMA1 channel 6 interrupt */
  63 #define INTCHW_INTC0_DMA1C5_BITNUM        13    /* DMA1 channel 5 interrupt */
  64 #define INTCHW_INTC0_DMA1C4_BITNUM        12    /* DMA1 channel 4 interrupt */
  65 #define INTCHW_INTC0_DMA1C3_BITNUM        11    /* DMA1 channel 3 interrupt */
  66 #define INTCHW_INTC0_DMA1C2_BITNUM        10    /* DMA1 channel 2 interrupt */
  67 #define INTCHW_INTC0_DMA1C1_BITNUM         9    /* DMA1 channel 1 interrupt */
  68 #define INTCHW_INTC0_DMA1C0_BITNUM         8    /* DMA1 channel 0 interrupt */
  69 #define INTCHW_INTC0_DMA0C7_BITNUM         7    /* DMA0 channel 7 interrupt */
  70 #define INTCHW_INTC0_DMA0C6_BITNUM         6    /* DMA0 channel 6 interrupt */
  71 #define INTCHW_INTC0_DMA0C5_BITNUM         5    /* DMA0 channel 5 interrupt */
  72 #define INTCHW_INTC0_DMA0C4_BITNUM         4    /* DMA0 channel 4 interrupt */
  73 #define INTCHW_INTC0_DMA0C3_BITNUM         3    /* DMA0 channel 3 interrupt */
  74 #define INTCHW_INTC0_DMA0C2_BITNUM         2    /* DMA0 channel 2 interrupt */
  75 #define INTCHW_INTC0_DMA0C1_BITNUM         1    /* DMA0 channel 1 interrupt */
  76 #define INTCHW_INTC0_DMA0C0_BITNUM         0    /* DMA0 channel 0 interrupt */
  77
  78 #define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
  79 #define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
  80 #define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
  81 #define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
  82 #define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
  83 #define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
  84 #define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
  85 #define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
  86 #define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
  87 #define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
  88 #define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
  89 #define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
  90 #define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
  91 #define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
  92 #define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
  93 #define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
  94 #define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
  95 #define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
  96 #define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
  97 #define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
  98 #define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
  99 #define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
 100 #define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
 101 #define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
 102 #define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
 103 #define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
 104 #define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
 105 #define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
 106 #define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
 107 #define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
 108 #define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
 109 #define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
 110
 111 /* INTC1 - interrupt controller 1 */
 112 #define INTCHW_INTC1_DDRVPMP_BITNUM       27    /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
 113 #define INTCHW_INTC1_DDRVPMT_BITNUM       26    /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
 114 #define INTCHW_INTC1_DDRP_BITNUM          26    /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
 115 #define INTCHW_INTC1_RTC2_BITNUM          25    /* Real time clock tamper interrupt */
 116 #define INTCHW_INTC1_VDEC_BITNUM          24    /* Hantro Video Decoder interrupt */
 117 /* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
 118 #define INTCHW_INTC1_SPUM_BITNUM          23    /* Secure process module interrupt */
 119 #define INTCHW_INTC1_RTC1_BITNUM          22    /* Real time clock one-shot interrupt */
 120 #define INTCHW_INTC1_RTC0_BITNUM          21    /* Real time clock periodic interrupt */
 121 #define INTCHW_INTC1_RNG_BITNUM           20    /* Random number generator interrupt */
 122 #define INTCHW_INTC1_FMPU_BITNUM          19    /* Flash memory parition unit interrupt */
 123 #define INTCHW_INTC1_VMPU_BITNUM          18    /* VRAM memory partition interrupt */
 124 #define INTCHW_INTC1_DMPU_BITNUM          17    /* DDR2 memory partition interrupt */
 125 #define INTCHW_INTC1_KEYC_BITNUM          16    /* Key pad controller interrupt */
 126 #define INTCHW_INTC1_TSC_BITNUM           15    /* Touch screen controller interrupt */
 127 #define INTCHW_INTC1_UART0_BITNUM         14    /* UART 0 */
 128 #define INTCHW_INTC1_WDOG_BITNUM          13    /* Watchdog timer interrupt */
 129
 130 #define INTCHW_INTC1_UART1_BITNUM         12    /* UART 1 */
 131 #define INTCHW_INTC1_PMUIRQ_BITNUM        11    /* ARM performance monitor interrupt */
 132 #define INTCHW_INTC1_COMMRX_BITNUM        10    /* ARM DDC receive interrupt */
 133 #define INTCHW_INTC1_COMMTX_BITNUM         9    /* ARM DDC transmit interrupt */
 134 #define INTCHW_INTC1_FLASHC_BITNUM         8    /* Flash controller interrupt */
 135 #define INTCHW_INTC1_GPHY_BITNUM           7    /* Gigabit Phy interrupt */
 136 #define INTCHW_INTC1_SPIS_BITNUM           6    /* SPI slave interrupt */
 137 #define INTCHW_INTC1_I2CS_BITNUM           5    /* I2C slave interrupt */
 138 #define INTCHW_INTC1_I2CH_BITNUM           4    /* I2C host interrupt */
 139 #define INTCHW_INTC1_I2S1_BITNUM           3    /* I2S1 interrupt */
 140 #define INTCHW_INTC1_I2S0_BITNUM           2    /* I2S0 interrupt */
 141 #define INTCHW_INTC1_GPIO1_BITNUM          1    /* GPIO bit 64//32 combined interrupt */
 142 #define INTCHW_INTC1_GPIO0_BITNUM          0    /* GPIO bit 31//0 combined interrupt */
 143
 144 #define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
 145 #define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
 146 #define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
 147 #define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
 148 #define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
 149 #define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
 150 #define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
 151 #define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
 152 #define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
 153 #define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
 154 #define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
 155 #define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
 156 #define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
 157 #define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
 158 #define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
 159 #define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
 160 #define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
 161 #define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
 162 #define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
 163 #define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
 164 #define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
 165 #define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
 166 #define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
 167 #define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
 168 #define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
 169 #define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
 170 #define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
 171 #define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
 172 #define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
 173
 174 /* SINTC secure int controller */
 175 #define INTCHW_SINTC_RTC2_BITNUM          15    /* Real time clock tamper interrupt */
 176 #define INTCHW_SINTC_TIMER3_BITNUM        14    /* Secure timer3 interrupt */
 177 #define INTCHW_SINTC_TIMER2_BITNUM        13    /* Secure timer2 interrupt */
 178 #define INTCHW_SINTC_TIMER1_BITNUM        12    /* Secure timer1 interrupt */
 179 #define INTCHW_SINTC_TIMER0_BITNUM        11    /* Secure timer0 interrupt */
 180 #define INTCHW_SINTC_SPUM_BITNUM          10    /* Secure process module interrupt */
 181 #define INTCHW_SINTC_RTC1_BITNUM           9    /* Real time clock one-shot interrupt */
 182 #define INTCHW_SINTC_RTC0_BITNUM           8    /* Real time clock periodic interrupt */
 183 #define INTCHW_SINTC_RNG_BITNUM            7    /* Random number generator interrupt */
 184 #define INTCHW_SINTC_FMPU_BITNUM           6    /* Flash memory parition unit interrupt */
 185 #define INTCHW_SINTC_VMPU_BITNUM           5    /* VRAM memory partition interrupt */
 186 #define INTCHW_SINTC_DMPU_BITNUM           4    /* DDR2 memory partition interrupt */
 187 #define INTCHW_SINTC_KEYC_BITNUM           3    /* Key pad controller interrupt */
 188 #define INTCHW_SINTC_TSC_BITNUM            2    /* Touch screen controller interrupt */
 189 #define INTCHW_SINTC_UART0_BITNUM          1    /* UART0 interrupt */
 190 #define INTCHW_SINTC_WDOG_BITNUM           0    /* Watchdog timer interrupt */
 191
 192 #define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
 193 #define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
 194 #define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
 195 #define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
 196 #define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
 197 #define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
 198 #define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
 199 #define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
 200 #define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
 201 #define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
 202 #define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
 203 #define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
 204 #define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
 205 #define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
 206 #define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
 207 #define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
 208
 209 /* PL192 Vectored Interrupt Controller (VIC) layout */
 210 #define INTCHW_IRQSTATUS      0x00      /* IRQ status register */
 211 #define INTCHW_FIQSTATUS      0x04      /* FIQ status register */
 212 #define INTCHW_RAWINTR        0x08      /* Raw Interrupt Status register */
 213 #define INTCHW_INTSELECT      0x0c      /* Interrupt Select Register */
 214 #define INTCHW_INTENABLE      0x10      /* Interrupt Enable Register */
 215 #define INTCHW_INTENCLEAR     0x14      /* Interrupt Enable Clear Register */
 216 #define INTCHW_SOFTINT        0x18      /* Soft Interrupt Register */
 217 #define INTCHW_SOFTINTCLEAR   0x1c      /* Soft Interrupt Clear Register */
 218 #define INTCHW_PROTECTION     0x20      /* Protection Enable Register */
 219 #define INTCHW_SWPRIOMASK     0x24      /* Software Priority Mask Register */
 220 #define INTCHW_PRIODAISY      0x28      /* Priority Daisy Chain Register */
 221 #define INTCHW_VECTADDR0      0x100     /* Vector Address Registers */
 222 #define INTCHW_VECTPRIO0      0x200     /* Vector Priority Registers 0-31 */
 223 #define INTCHW_ADDRESS        0xf00     /* Vector Address Register 0-31 */
 224 #define INTCHW_PID            0xfe0     /* Peripheral ID Register 0-3 */
 225 #define INTCHW_PCELLID        0xff0     /* PrimeCell ID Register 0-3 */
 226
 227 /* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
 228 /*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
 229 /*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
 230 /*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
 231
 232 /* ---- Public Variable Externs ------------------------------------------ */
 233 /* ---- Public Function Prototypes --------------------------------------- */
 234 /* Clear one or more IRQ interrupts. */
 235 static inline void intcHw_irq_disable(void *basep, uint32_t mask)
 236 {
 237         __REG32(basep + INTCHW_INTENCLEAR) = mask;
 238 }
 239
 240 /* Enables one or more IRQ interrupts. */
 241 static inline void intcHw_irq_enable(void *basep, uint32_t mask)
 242 {
 243         __REG32(basep + INTCHW_INTENABLE) = mask;
 244 }
 245
 246 #endif /* _INTCHW_REG_H */