arch/arm/mach-exynos4/irq-eint.c

   1 /* linux/arch/arm/mach-exynos4/irq-eint.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - IRQ EINT support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/io.h>
  17 #include <linux/sysdev.h>
  18 #include <linux/gpio.h>
  19
  20 #include <plat/pm.h>
  21 #include <plat/cpu.h>
  22 #include <plat/gpio-cfg.h>
  23
  24 #include <mach/regs-gpio.h>
  25
  26 #include <asm/mach/irq.h>
  27
  28 static DEFINE_SPINLOCK(eint_lock);
  29
  30 static unsigned int eint0_15_data[16];
  31
  32 static unsigned int exynos4_get_irq_nr(unsigned int number)
  33 {
  34         u32 ret = 0;
  35
  36         switch (number) {
  37         case 0 ... 3:
  38                 ret = (number + IRQ_EINT0);
  39                 break;
  40         case 4 ... 7:
  41                 ret = (number + (IRQ_EINT4 - 4));
  42                 break;
  43         case 8 ... 15:
  44                 ret = (number + (IRQ_EINT8 - 8));
  45                 break;
  46         default:
  47                 printk(KERN_ERR "number available : %d\n", number);
  48         }
  49
  50         return ret;
  51 }
  52
  53 static inline void exynos4_irq_eint_mask(struct irq_data *data)
  54 {
  55         u32 mask;
  56
  57         spin_lock(&eint_lock);
  58         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
  59         mask |= eint_irq_to_bit(data->irq);
  60         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
  61         spin_unlock(&eint_lock);
  62 }
  63
  64 static void exynos4_irq_eint_unmask(struct irq_data *data)
  65 {
  66         u32 mask;
  67
  68         spin_lock(&eint_lock);
  69         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
  70         mask &= ~(eint_irq_to_bit(data->irq));
  71         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
  72         spin_unlock(&eint_lock);
  73 }
  74
  75 static inline void exynos4_irq_eint_ack(struct irq_data *data)
  76 {
  77         __raw_writel(eint_irq_to_bit(data->irq),
  78                      S5P_EINT_PEND(EINT_REG_NR(data->irq)));
  79 }
  80
  81 static void exynos4_irq_eint_maskack(struct irq_data *data)
  82 {
  83         exynos4_irq_eint_mask(data);
  84         exynos4_irq_eint_ack(data);
  85 }
  86
  87 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
  88 {
  89         int offs = EINT_OFFSET(data->irq);
  90         int shift;
  91         u32 ctrl, mask;
  92         u32 newvalue = 0;
  93
  94         switch (type) {
  95         case IRQ_TYPE_EDGE_RISING:
  96                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
  97                 break;
  98
  99         case IRQ_TYPE_EDGE_FALLING:
 100                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 101                 break;
 102
 103         case IRQ_TYPE_EDGE_BOTH:
 104                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 105                 break;
 106
 107         case IRQ_TYPE_LEVEL_LOW:
 108                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 109                 break;
 110
 111         case IRQ_TYPE_LEVEL_HIGH:
 112                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 113                 break;
 114
 115         default:
 116                 printk(KERN_ERR "No such irq type %d", type);
 117                 return -EINVAL;
 118         }
 119
 120         shift = (offs & 0x7) * 4;
 121         mask = 0x7 << shift;
 122
 123         spin_lock(&eint_lock);
 124         ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
 125         ctrl &= ~mask;
 126         ctrl |= newvalue << shift;
 127         __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
 128         spin_unlock(&eint_lock);
 129
 130         switch (offs) {
 131         case 0 ... 7:
 132                 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
 133                 break;
 134         case 8 ... 15:
 135                 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
 136                 break;
 137         case 16 ... 23:
 138                 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
 139                 break;
 140         case 24 ... 31:
 141                 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
 142                 break;
 143         default:
 144                 printk(KERN_ERR "No such irq number %d", offs);
 145         }
 146
 147         return 0;
 148 }
 149
 150 static struct irq_chip exynos4_irq_eint = {
 151         .name           = "exynos4-eint",
 152         .irq_mask       = exynos4_irq_eint_mask,
 153         .irq_unmask     = exynos4_irq_eint_unmask,
 154         .irq_mask_ack   = exynos4_irq_eint_maskack,
 155         .irq_ack        = exynos4_irq_eint_ack,
 156         .irq_set_type   = exynos4_irq_eint_set_type,
 157 #ifdef CONFIG_PM
 158         .irq_set_wake   = s3c_irqext_wake,
 159 #endif
 160 };
 161
 162 /* exynos4_irq_demux_eint
 163  *
 164  * This function demuxes the IRQ from from EINTs 16 to 31.
 165  * It is designed to be inlined into the specific handler
 166  * s5p_irq_demux_eintX_Y.
 167  *
 168  * Each EINT pend/mask registers handle eight of them.
 169  */
 170 static inline void exynos4_irq_demux_eint(unsigned int start)
 171 {
 172         unsigned int irq;
 173
 174         u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
 175         u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
 176
 177         status &= ~mask;
 178         status &= 0xff;
 179
 180         while (status) {
 181                 irq = fls(status) - 1;
 182                 generic_handle_irq(irq + start);
 183                 status &= ~(1 << irq);
 184         }
 185 }
 186
 187 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 188 {
 189         struct irq_chip *chip = irq_get_chip(irq);
 190         chained_irq_enter(chip, desc);
 191         exynos4_irq_demux_eint(IRQ_EINT(16));
 192         exynos4_irq_demux_eint(IRQ_EINT(24));
 193         chained_irq_exit(chip, desc);
 194 }
 195
 196 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 197 {
 198         u32 *irq_data = irq_get_handler_data(irq);
 199         struct irq_chip *chip = irq_get_chip(irq);
 200
 201         chained_irq_enter(chip, desc);
 202         chip->irq_mask(&desc->irq_data);
 203
 204         if (chip->irq_ack)
 205                 chip->irq_ack(&desc->irq_data);
 206
 207         generic_handle_irq(*irq_data);
 208
 209         chip->irq_unmask(&desc->irq_data);
 210         chained_irq_exit(chip, desc);
 211 }
 212
 213 int __init exynos4_init_irq_eint(void)
 214 {
 215         int irq;
 216
 217         for (irq = 0 ; irq <= 31 ; irq++) {
 218                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
 219                                          handle_level_irq);
 220                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 221         }
 222
 223         irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 224
 225         for (irq = 0 ; irq <= 15 ; irq++) {
 226                 eint0_15_data[irq] = IRQ_EINT(irq);
 227
 228                 irq_set_handler_data(exynos4_get_irq_nr(irq),
 229                                      &eint0_15_data[irq]);
 230                 irq_set_chained_handler(exynos4_get_irq_nr(irq),
 231                                         exynos4_irq_eint0_15);
 232         }
 233
 234         return 0;
 235 }
 236
 237 arch_initcall(exynos4_init_irq_eint);